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crypto-qti-ice-regs.h

crypto-qti-ice-regs.h 6.2 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _CRYPTO_INLINE_CRYPTO_ENGINE_REGS_H_
    7. 

  7. #define _CRYPTO_INLINE_CRYPTO_ENGINE_REGS_H_
    8. 

  8. 

  9. #include <linux/io.h>
    10. 

  10. 

  11. /* Register bits for ICE version */
    12. 

  12. #define ICE_CORE_CURRENT_MAJOR_VERSION 0x03
    13. 

  13. 

  14. #define ICE_CORE_STEP_REV_MASK		0xFFFF
    15. 

  15. #define ICE_CORE_STEP_REV		0 /* bit 15-0 */
    16. 

  16. #define ICE_CORE_MAJOR_REV_MASK		0xFF000000
    17. 

  17. #define ICE_CORE_MAJOR_REV		24 /* bit 31-24 */
    18. 

  18. #define ICE_CORE_MINOR_REV_MASK		0xFF0000
    19. 

  19. #define ICE_CORE_MINOR_REV		16 /* bit 23-16 */
    20. 

  20. 

  21. #define ICE_BIST_STATUS_MASK		(0xF0000000)	/* bits 28-31 */
    22. 

  22. 

  23. #define ICE_FUSE_SETTING_MASK			0x1
    24. 

  24. #define ICE_FORCE_HW_KEY0_SETTING_MASK		0x2
    25. 

  25. #define ICE_FORCE_HW_KEY1_SETTING_MASK		0x4
    26. 

  26. 

  27. /* QTI ICE Registers from SWI */
    28. 

  28. #define ICE_REGS_CONTROL			0x0000
    29. 

  29. #define ICE_REGS_RESET				0x0004
    30. 

  30. #define ICE_REGS_VERSION			0x0008
    31. 

  31. #define ICE_REGS_FUSE_SETTING			0x0010
    32. 

  32. #define ICE_REGS_PARAMETERS_1			0x0014
    33. 

  33. #define ICE_REGS_PARAMETERS_2			0x0018
    34. 

  34. #define ICE_REGS_PARAMETERS_3			0x001C
    35. 

  35. #define ICE_REGS_PARAMETERS_4			0x0020
    36. 

  36. #define ICE_REGS_PARAMETERS_5			0x0024
    37. 

  37. 

  38. 

  39. /* QTI ICE v3.X only */
    40. 

  40. #define ICE_GENERAL_ERR_STTS			0x0040
    41. 

  41. #define ICE_INVALID_CCFG_ERR_STTS		0x0030
    42. 

  42. #define ICE_GENERAL_ERR_MASK			0x0044
    43. 

  43. 

  44. #define ICE_STREAM1_HWKM_RD_ERR_STTS	0x123C
    45. 

  45. #define ICE_STREAM2_HWKM_RD_ERR_STTS	0x1248
    46. 

  46. #define ICE_CONFIG_HWKM_WR_ERR_STTS		0x1254
    47. 

  47. 

  48. /* QTI ICE v2.X only */
    49. 

  49. #define ICE_REGS_NON_SEC_IRQ_STTS		0x0040
    50. 

  50. #define ICE_REGS_NON_SEC_IRQ_MASK		0x0044
    51. 

  51. 

  52. 

  53. #define ICE_REGS_NON_SEC_IRQ_CLR		0x0048
    54. 

  54. #define ICE_REGS_STREAM1_ERROR_SYNDROME1	0x0050
    55. 

  55. #define ICE_REGS_STREAM1_ERROR_SYNDROME2	0x0054
    56. 

  56. #define ICE_REGS_STREAM2_ERROR_SYNDROME1	0x0058
    57. 

  57. #define ICE_REGS_STREAM2_ERROR_SYNDROME2	0x005C
    58. 

  58. #define ICE_REGS_STREAM1_ERROR_SYNDROME3	0x0080
    59. 

  59. #define ICE_REGS_STREAM2_ERROR_SYNDROME3	0x0084
    60. 

  60. #define ICE_REGS_STREAM1_BIST_ERROR_VEC		0x0060
    61. 

  61. #define ICE_REGS_STREAM2_BIST_ERROR_VEC		0x0064
    62. 

  62. #define ICE_REGS_STREAM1_BIST_FINISH_VEC	0x0068
    63. 

  63. #define ICE_REGS_STREAM2_BIST_FINISH_VEC	0x006C
    64. 

  64. #define ICE_REGS_BIST_STATUS			0x0070
    65. 

  65. #define ICE_REGS_BYPASS_STATUS			0x0074
    66. 

  66. #define ICE_REGS_ADVANCED_CONTROL		0x1000
    67. 

  67. #define ICE_REGS_ENDIAN_SWAP			0x1004
    68. 

  68. #define ICE_REGS_TEST_BUS_CONTROL		0x1010
    69. 

  69. #define ICE_REGS_TEST_BUS_REG			0x1014
    70. 

  70. #define ICE_REGS_STREAM1_COUNTERS1		0x1100
    71. 

  71. #define ICE_REGS_STREAM1_COUNTERS2		0x1104
    72. 

  72. #define ICE_REGS_STREAM1_COUNTERS3		0x1108
    73. 

  73. #define ICE_REGS_STREAM1_COUNTERS4		0x110C
    74. 

  74. #define ICE_REGS_STREAM1_COUNTERS5_MSB		0x1110
    75. 

  75. #define ICE_REGS_STREAM1_COUNTERS5_LSB		0x1114
    76. 

  76. #define ICE_REGS_STREAM1_COUNTERS6_MSB		0x1118
    77. 

  77. #define ICE_REGS_STREAM1_COUNTERS6_LSB		0x111C
    78. 

  78. #define ICE_REGS_STREAM1_COUNTERS7_MSB		0x1120
    79. 

  79. #define ICE_REGS_STREAM1_COUNTERS7_LSB		0x1124
    80. 

  80. #define ICE_REGS_STREAM1_COUNTERS8_MSB		0x1128
    81. 

  81. #define ICE_REGS_STREAM1_COUNTERS8_LSB		0x112C
    82. 

  82. #define ICE_REGS_STREAM1_COUNTERS9_MSB		0x1130
    83. 

  83. #define ICE_REGS_STREAM1_COUNTERS9_LSB		0x1134
    84. 

  84. #define ICE_REGS_STREAM2_COUNTERS1		0x1200
    85. 

  85. #define ICE_REGS_STREAM2_COUNTERS2		0x1204
    86. 

  86. #define ICE_REGS_STREAM2_COUNTERS3		0x1208
    87. 

  87. #define ICE_REGS_STREAM2_COUNTERS4		0x120C
    88. 

  88. #define ICE_REGS_STREAM2_COUNTERS5_MSB		0x1210
    89. 

  89. #define ICE_REGS_STREAM2_COUNTERS5_LSB		0x1214
    90. 

  90. #define ICE_REGS_STREAM2_COUNTERS6_MSB		0x1218
    91. 

  91. #define ICE_REGS_STREAM2_COUNTERS6_LSB		0x121C
    92. 

  92. #define ICE_REGS_STREAM2_COUNTERS7_MSB		0x1220
    93. 

  93. #define ICE_REGS_STREAM2_COUNTERS7_LSB		0x1224
    94. 

  94. #define ICE_REGS_STREAM2_COUNTERS8_MSB		0x1228
    95. 

  95. #define ICE_REGS_STREAM2_COUNTERS8_LSB		0x122C
    96. 

  96. #define ICE_REGS_STREAM2_COUNTERS9_MSB		0x1230
    97. 

  97. #define ICE_REGS_STREAM2_COUNTERS9_LSB		0x1234
    98. 

  98. 

  99. #define ICE_STREAM1_PREMATURE_LBA_CHANGE	(1L << 0)
    100. 

  100. #define ICE_STREAM2_PREMATURE_LBA_CHANGE	(1L << 1)
    101. 

  101. #define ICE_STREAM1_NOT_EXPECTED_LBO		(1L << 2)
    102. 

  102. #define ICE_STREAM2_NOT_EXPECTED_LBO		(1L << 3)
    103. 

  103. #define ICE_STREAM1_NOT_EXPECTED_DUN		(1L << 4)
    104. 

  104. #define ICE_STREAM2_NOT_EXPECTED_DUN		(1L << 5)
    105. 

  105. #define ICE_STREAM1_NOT_EXPECTED_DUS		(1L << 6)
    106. 

  106. #define ICE_STREAM2_NOT_EXPECTED_DUS		(1L << 7)
    107. 

  107. #define ICE_STREAM1_NOT_EXPECTED_DBO		(1L << 8)
    108. 

  108. #define ICE_STREAM2_NOT_EXPECTED_DBO		(1L << 9)
    109. 

  109. #define ICE_STREAM1_NOT_EXPECTED_ENC_SEL	(1L << 10)
    110. 

  110. #define ICE_STREAM2_NOT_EXPECTED_ENC_SEL	(1L << 11)
    111. 

  111. #define ICE_STREAM1_NOT_EXPECTED_CONF_IDX	(1L << 12)
    112. 

  112. #define ICE_STREAM2_NOT_EXPECTED_CONF_IDX	(1L << 13)
    113. 

  113. #define ICE_STREAM1_NOT_EXPECTED_NEW_TRNS	(1L << 14)
    114. 

  114. #define ICE_STREAM2_NOT_EXPECTED_NEW_TRNS	(1L << 15)
    115. 

  115. 

  116. #define ICE_NON_SEC_IRQ_MASK				\
    117. 

  117. 			(ICE_STREAM1_PREMATURE_LBA_CHANGE |\
    118. 

  118. 			 ICE_STREAM2_PREMATURE_LBA_CHANGE |\
    119. 

  119. 			 ICE_STREAM1_NOT_EXPECTED_LBO |\
    120. 

  120. 			 ICE_STREAM2_NOT_EXPECTED_LBO |\
    121. 

  121. 			 ICE_STREAM1_NOT_EXPECTED_DUN |\
    122. 

  122. 			 ICE_STREAM2_NOT_EXPECTED_DUN |\
    123. 

  123. 			 ICE_STREAM2_NOT_EXPECTED_DUS |\
    124. 

  124. 			 ICE_STREAM1_NOT_EXPECTED_DBO |\
    125. 

  125. 			 ICE_STREAM2_NOT_EXPECTED_DBO |\
    126. 

  126. 			 ICE_STREAM1_NOT_EXPECTED_ENC_SEL |\
    127. 

  127. 			 ICE_STREAM2_NOT_EXPECTED_ENC_SEL |\
    128. 

  128. 			 ICE_STREAM1_NOT_EXPECTED_CONF_IDX |\
    129. 

  129. 			 ICE_STREAM1_NOT_EXPECTED_NEW_TRNS |\
    130. 

  130. 			 ICE_STREAM2_NOT_EXPECTED_NEW_TRNS)
    131. 

  131. 

  132. /* QTI ICE registers from secure side */
    133. 

  133. #define ICE_TEST_BUS_REG_SECURE_INTR            (1L << 28)
    134. 

  134. #define ICE_TEST_BUS_REG_NON_SECURE_INTR        (1L << 2)
    135. 

  135. 

  136. #define ICE_LUT_KEYS_CRYPTOCFG_R_16		0x4040
    137. 

  137. #define ICE_LUT_KEYS_CRYPTOCFG_R_17		0x4044
    138. 

  138. 

  139. #define ICE_LUT_KEYS_ICE_SEC_IRQ_STTS		0x6200
    140. 

  140. #define ICE_LUT_KEYS_ICE_SEC_IRQ_MASK		0x6204
    141. 

  141. #define ICE_LUT_KEYS_ICE_SEC_IRQ_CLR		0x6208
    142. 

  142. 

  143. #define ICE_LUT_KEYS_CRYPTOCFG_OFFSET           0x80
    144. 

  144. 

  145. /* Non HWKM Targets */
    146. 

  146. #define ICE_LUT_KEYS_SW_CRYPTOCFG_R_16		0x2040
    147. 

  147. #define ICE_LUT_KEYS_SW_CRYPTOCFG_R_17		0x2044
    148. 

  148. 

  149. #define ICE_LUT_KEYS_SW_ICE_SEC_IRQ_STTS	0x3100
    150. 

  150. #define ICE_LUT_KEYS_SW_ICE_SEC_IRQ_MASK	0x3104
    151. 

  151. #define ICE_LUT_KEYS_SW_ICE_SEC_IRQ_CLR		0x3108
    152. 

  152. 

  153. #define ICE_STREAM1_PARTIALLY_SET_KEY_USED	(1L << 0)
    154. 

  154. #define ICE_STREAM2_PARTIALLY_SET_KEY_USED	(1L << 1)
    155. 

  155. #define ICE_QTIC_DBG_OPEN_EVENT			(1L << 30)
    156. 

  156. #define ICE_KEYS_RAM_RESET_COMPLETED		(1L << 31)
    157. 

  157. 

  158. #define ICE_SEC_IRQ_MASK					  \
    159. 

  159. 			(ICE_STREAM1_PARTIALLY_SET_KEY_USED |\
    160. 

  160. 			 ICE_STREAM2_PARTIALLY_SET_KEY_USED |\
    161. 

  161. 			 ICE_QTIC_DBG_OPEN_EVENT |	  \
    162. 

  162. 			 ICE_KEYS_RAM_RESET_COMPLETED)
    163. 

  163. 

  164. /* Shared ICE */
    165. 

  165. #define ICE_AES_SHARE_CONTROL		0x0100
    166. 

  166. #define ICE_AES_CORE_STTS			0x0104
    167. 

  167. #define ICE_AES_CORE_DISABLE		0x1400
    168. 

  168. 

  169. #define ice_writel(ice_mmio, val, reg)	\
    170. 

  170. 	writel_relaxed((val), ice_mmio + (reg))
    171. 

  171. #define ice_readl(ice_mmio, reg)	\
    172. 

  172. 	readl_relaxed(ice_mmio + (reg))
    173. 

  173. 

  174. #endif /* _CRYPTO_INLINE_CRYPTO_ENGINE_REGS_H_ */
    175.