mtk-mmsys.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: James Liao <[email protected]>
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/device.h>
  8. #include <linux/io.h>
  9. #include <linux/of_device.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/reset-controller.h>
  12. #include <linux/soc/mediatek/mtk-mmsys.h>
  13. #include "mtk-mmsys.h"
  14. #include "mt8167-mmsys.h"
  15. #include "mt8183-mmsys.h"
  16. #include "mt8186-mmsys.h"
  17. #include "mt8192-mmsys.h"
  18. #include "mt8195-mmsys.h"
  19. #include "mt8365-mmsys.h"
  20. static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
  21. .clk_driver = "clk-mt2701-mm",
  22. .routes = mmsys_default_routing_table,
  23. .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
  24. };
  25. static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
  26. .num_drv_data = 1,
  27. .drv_data = {
  28. &mt2701_mmsys_driver_data,
  29. },
  30. };
  31. static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
  32. .clk_driver = "clk-mt2712-mm",
  33. .routes = mmsys_default_routing_table,
  34. .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
  35. };
  36. static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
  37. .num_drv_data = 1,
  38. .drv_data = {
  39. &mt2712_mmsys_driver_data,
  40. },
  41. };
  42. static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
  43. .clk_driver = "clk-mt6779-mm",
  44. };
  45. static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
  46. .num_drv_data = 1,
  47. .drv_data = {
  48. &mt6779_mmsys_driver_data,
  49. },
  50. };
  51. static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
  52. .clk_driver = "clk-mt6797-mm",
  53. };
  54. static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
  55. .num_drv_data = 1,
  56. .drv_data = {
  57. &mt6797_mmsys_driver_data,
  58. },
  59. };
  60. static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
  61. .clk_driver = "clk-mt8167-mm",
  62. .routes = mt8167_mmsys_routing_table,
  63. .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
  64. };
  65. static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
  66. .num_drv_data = 1,
  67. .drv_data = {
  68. &mt8167_mmsys_driver_data,
  69. },
  70. };
  71. static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
  72. .clk_driver = "clk-mt8173-mm",
  73. .routes = mmsys_default_routing_table,
  74. .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
  75. .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
  76. };
  77. static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
  78. .num_drv_data = 1,
  79. .drv_data = {
  80. &mt8173_mmsys_driver_data,
  81. },
  82. };
  83. static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
  84. .clk_driver = "clk-mt8183-mm",
  85. .routes = mmsys_mt8183_routing_table,
  86. .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
  87. .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
  88. };
  89. static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
  90. .num_drv_data = 1,
  91. .drv_data = {
  92. &mt8183_mmsys_driver_data,
  93. },
  94. };
  95. static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
  96. .clk_driver = "clk-mt8186-mm",
  97. .routes = mmsys_mt8186_routing_table,
  98. .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
  99. .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
  100. };
  101. static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
  102. .num_drv_data = 1,
  103. .drv_data = {
  104. &mt8186_mmsys_driver_data,
  105. },
  106. };
  107. static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
  108. .clk_driver = "clk-mt8192-mm",
  109. .routes = mmsys_mt8192_routing_table,
  110. .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
  111. .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
  112. };
  113. static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
  114. .num_drv_data = 1,
  115. .drv_data = {
  116. &mt8192_mmsys_driver_data,
  117. },
  118. };
  119. static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
  120. .io_start = 0x1c01a000,
  121. .clk_driver = "clk-mt8195-vdo0",
  122. .routes = mmsys_mt8195_routing_table,
  123. .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
  124. };
  125. static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
  126. .io_start = 0x1c100000,
  127. .clk_driver = "clk-mt8195-vdo1",
  128. };
  129. static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
  130. .num_drv_data = 2,
  131. .drv_data = {
  132. &mt8195_vdosys0_driver_data,
  133. &mt8195_vdosys1_driver_data,
  134. },
  135. };
  136. static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
  137. .clk_driver = "clk-mt8365-mm",
  138. .routes = mt8365_mmsys_routing_table,
  139. .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
  140. };
  141. static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
  142. .num_drv_data = 1,
  143. .drv_data = {
  144. &mt8365_mmsys_driver_data,
  145. },
  146. };
  147. struct mtk_mmsys {
  148. void __iomem *regs;
  149. const struct mtk_mmsys_driver_data *data;
  150. spinlock_t lock; /* protects mmsys_sw_rst_b reg */
  151. struct reset_controller_dev rcdev;
  152. phys_addr_t io_start;
  153. };
  154. static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
  155. const struct mtk_mmsys_match_data *match)
  156. {
  157. int i;
  158. for (i = 0; i < match->num_drv_data; i++)
  159. if (mmsys->io_start == match->drv_data[i]->io_start)
  160. return i;
  161. return -EINVAL;
  162. }
  163. void mtk_mmsys_ddp_connect(struct device *dev,
  164. enum mtk_ddp_comp_id cur,
  165. enum mtk_ddp_comp_id next)
  166. {
  167. struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
  168. const struct mtk_mmsys_routes *routes = mmsys->data->routes;
  169. u32 reg;
  170. int i;
  171. for (i = 0; i < mmsys->data->num_routes; i++)
  172. if (cur == routes[i].from_comp && next == routes[i].to_comp) {
  173. reg = readl_relaxed(mmsys->regs + routes[i].addr);
  174. reg &= ~routes[i].mask;
  175. reg |= routes[i].val;
  176. writel_relaxed(reg, mmsys->regs + routes[i].addr);
  177. }
  178. }
  179. EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
  180. void mtk_mmsys_ddp_disconnect(struct device *dev,
  181. enum mtk_ddp_comp_id cur,
  182. enum mtk_ddp_comp_id next)
  183. {
  184. struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
  185. const struct mtk_mmsys_routes *routes = mmsys->data->routes;
  186. u32 reg;
  187. int i;
  188. for (i = 0; i < mmsys->data->num_routes; i++)
  189. if (cur == routes[i].from_comp && next == routes[i].to_comp) {
  190. reg = readl_relaxed(mmsys->regs + routes[i].addr);
  191. reg &= ~routes[i].mask;
  192. writel_relaxed(reg, mmsys->regs + routes[i].addr);
  193. }
  194. }
  195. EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
  196. static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
  197. {
  198. u32 tmp;
  199. tmp = readl_relaxed(mmsys->regs + offset);
  200. tmp = (tmp & ~mask) | val;
  201. writel_relaxed(tmp, mmsys->regs + offset);
  202. }
  203. void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
  204. {
  205. if (val)
  206. mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8186_MMSYS_DPI_OUTPUT_FORMAT,
  207. DPI_RGB888_DDR_CON, DPI_FORMAT_MASK);
  208. else
  209. mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8186_MMSYS_DPI_OUTPUT_FORMAT,
  210. DPI_RGB565_SDR_CON, DPI_FORMAT_MASK);
  211. }
  212. EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
  213. static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
  214. bool assert)
  215. {
  216. struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
  217. unsigned long flags;
  218. u32 reg;
  219. spin_lock_irqsave(&mmsys->lock, flags);
  220. reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
  221. if (assert)
  222. reg &= ~BIT(id);
  223. else
  224. reg |= BIT(id);
  225. writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
  226. spin_unlock_irqrestore(&mmsys->lock, flags);
  227. return 0;
  228. }
  229. static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
  230. {
  231. return mtk_mmsys_reset_update(rcdev, id, true);
  232. }
  233. static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
  234. {
  235. return mtk_mmsys_reset_update(rcdev, id, false);
  236. }
  237. static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
  238. {
  239. int ret;
  240. ret = mtk_mmsys_reset_assert(rcdev, id);
  241. if (ret)
  242. return ret;
  243. usleep_range(1000, 1100);
  244. return mtk_mmsys_reset_deassert(rcdev, id);
  245. }
  246. static const struct reset_control_ops mtk_mmsys_reset_ops = {
  247. .assert = mtk_mmsys_reset_assert,
  248. .deassert = mtk_mmsys_reset_deassert,
  249. .reset = mtk_mmsys_reset,
  250. };
  251. static int mtk_mmsys_probe(struct platform_device *pdev)
  252. {
  253. struct device *dev = &pdev->dev;
  254. struct platform_device *clks;
  255. struct platform_device *drm;
  256. const struct mtk_mmsys_match_data *match_data;
  257. struct mtk_mmsys *mmsys;
  258. struct resource *res;
  259. int ret;
  260. mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
  261. if (!mmsys)
  262. return -ENOMEM;
  263. mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
  264. if (IS_ERR(mmsys->regs)) {
  265. ret = PTR_ERR(mmsys->regs);
  266. dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
  267. return ret;
  268. }
  269. spin_lock_init(&mmsys->lock);
  270. mmsys->rcdev.owner = THIS_MODULE;
  271. mmsys->rcdev.nr_resets = 32;
  272. mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
  273. mmsys->rcdev.of_node = pdev->dev.of_node;
  274. ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
  275. if (ret) {
  276. dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
  277. return ret;
  278. }
  279. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  280. if (!res) {
  281. dev_err(dev, "Couldn't get mmsys resource\n");
  282. return -EINVAL;
  283. }
  284. mmsys->io_start = res->start;
  285. match_data = of_device_get_match_data(dev);
  286. if (match_data->num_drv_data > 1) {
  287. /* This SoC has multiple mmsys channels */
  288. ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
  289. if (ret < 0) {
  290. dev_err(dev, "Couldn't get match driver data\n");
  291. return ret;
  292. }
  293. mmsys->data = match_data->drv_data[ret];
  294. } else {
  295. dev_dbg(dev, "Using single mmsys channel\n");
  296. mmsys->data = match_data->drv_data[0];
  297. }
  298. platform_set_drvdata(pdev, mmsys);
  299. clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
  300. PLATFORM_DEVID_AUTO, NULL, 0);
  301. if (IS_ERR(clks))
  302. return PTR_ERR(clks);
  303. drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
  304. PLATFORM_DEVID_AUTO, NULL, 0);
  305. if (IS_ERR(drm)) {
  306. platform_device_unregister(clks);
  307. return PTR_ERR(drm);
  308. }
  309. return 0;
  310. }
  311. static const struct of_device_id of_match_mtk_mmsys[] = {
  312. {
  313. .compatible = "mediatek,mt2701-mmsys",
  314. .data = &mt2701_mmsys_match_data,
  315. },
  316. {
  317. .compatible = "mediatek,mt2712-mmsys",
  318. .data = &mt2712_mmsys_match_data,
  319. },
  320. {
  321. .compatible = "mediatek,mt6779-mmsys",
  322. .data = &mt6779_mmsys_match_data,
  323. },
  324. {
  325. .compatible = "mediatek,mt6797-mmsys",
  326. .data = &mt6797_mmsys_match_data,
  327. },
  328. {
  329. .compatible = "mediatek,mt8167-mmsys",
  330. .data = &mt8167_mmsys_match_data,
  331. },
  332. {
  333. .compatible = "mediatek,mt8173-mmsys",
  334. .data = &mt8173_mmsys_match_data,
  335. },
  336. {
  337. .compatible = "mediatek,mt8183-mmsys",
  338. .data = &mt8183_mmsys_match_data,
  339. },
  340. {
  341. .compatible = "mediatek,mt8186-mmsys",
  342. .data = &mt8186_mmsys_match_data,
  343. },
  344. {
  345. .compatible = "mediatek,mt8192-mmsys",
  346. .data = &mt8192_mmsys_match_data,
  347. },
  348. {
  349. .compatible = "mediatek,mt8195-mmsys",
  350. .data = &mt8195_mmsys_match_data,
  351. },
  352. {
  353. .compatible = "mediatek,mt8365-mmsys",
  354. .data = &mt8365_mmsys_match_data,
  355. },
  356. { }
  357. };
  358. static struct platform_driver mtk_mmsys_drv = {
  359. .driver = {
  360. .name = "mtk-mmsys",
  361. .of_match_table = of_match_mtk_mmsys,
  362. },
  363. .probe = mtk_mmsys_probe,
  364. };
  365. builtin_platform_driver(mtk_mmsys_drv);