mt8365-mmsys.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. #ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
  3. #define __SOC_MEDIATEK_MT8365_MMSYS_H
  4. #define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c
  5. #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c
  6. #define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50
  7. #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54
  8. #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60
  9. #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64
  10. #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68
  11. #define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0
  12. #define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8
  13. #define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
  14. #define MT8365_RDMA0_SOUT_COLOR0 0x1
  15. #define MT8365_DITHER_MOUT_EN_DSI0 0x1
  16. #define MT8365_DSI0_SEL_IN_DITHER 0x1
  17. #define MT8365_RDMA0_SEL_IN_OVL0 0x0
  18. #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
  19. #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0
  20. #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0)
  21. #define MT8365_RDMA1_SOUT_DPI0 0x1
  22. #define MT8365_DPI0_SEL_IN_RDMA1 0x0
  23. #define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1
  24. #define MT8365_DPI0_SEL_IN_RDMA1 0x0
  25. static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
  26. {
  27. DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
  28. MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
  29. MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL
  30. },
  31. {
  32. DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
  33. MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
  34. MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0
  35. },
  36. {
  37. DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
  38. MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
  39. MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0
  40. },
  41. {
  42. DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
  43. MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
  44. MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
  45. },
  46. {
  47. DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
  48. MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
  49. MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
  50. },
  51. {
  52. DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
  53. MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
  54. MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
  55. },
  56. {
  57. DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
  58. MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
  59. MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
  60. },
  61. {
  62. DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
  63. MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
  64. MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
  65. },
  66. {
  67. DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
  68. MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
  69. MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1
  70. },
  71. {
  72. DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
  73. MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
  74. MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0
  75. },
  76. };
  77. #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */