ql4_nx.h 36 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * QLogic iSCSI HBA Driver
  4. * Copyright (c) 2003-2013 QLogic Corporation
  5. */
  6. #ifndef __QLA_NX_H
  7. #define __QLA_NX_H
  8. /*
  9. * Following are the states of the Phantom. Phantom will set them and
  10. * Host will read to check if the fields are correct.
  11. */
  12. #define PHAN_INITIALIZE_FAILED 0xffff
  13. #define PHAN_INITIALIZE_COMPLETE 0xff01
  14. /* Host writes the following to notify that it has done the init-handshake */
  15. #define PHAN_INITIALIZE_ACK 0xf00f
  16. #define PHAN_PEG_RCV_INITIALIZED 0xff01
  17. /*CRB_RELATED*/
  18. #define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))
  19. #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
  20. #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
  21. #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
  22. #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
  23. #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
  24. #define CRB_CMDPEG_CHECK_RETRY_COUNT 60
  25. #define CRB_CMDPEG_CHECK_DELAY 500
  26. #define qla82xx_get_temp_val(x) ((x) >> 16)
  27. #define qla82xx_get_temp_state(x) ((x) & 0xffff)
  28. #define qla82xx_encode_temp(val, state) (((val) << 16) | (state))
  29. /*
  30. * Temperature control.
  31. */
  32. enum {
  33. QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
  34. QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */
  35. QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */
  36. };
  37. #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
  38. #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
  39. #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
  40. #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
  41. #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
  42. #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
  43. #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
  44. #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
  45. #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
  46. /* Hub 0 */
  47. #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
  48. #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
  49. /* Hub 1 */
  50. #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
  51. #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
  52. #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
  53. #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
  54. #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
  55. #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
  56. #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
  57. #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
  58. #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
  59. #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
  60. #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
  61. #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
  62. #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
  63. #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
  64. #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
  65. /* Hub 2 */
  66. #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
  67. #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
  68. #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
  69. #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
  70. #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
  71. #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
  72. #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
  73. #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
  74. #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
  75. #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
  76. #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
  77. #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
  78. #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
  79. #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
  80. #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
  81. #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
  82. /* Hub 3 */
  83. #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
  84. #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
  85. #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
  86. #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
  87. /* Hub 4 */
  88. #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
  89. #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
  90. #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
  91. #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
  92. #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
  93. #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
  94. #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
  95. #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
  96. #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
  97. #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
  98. #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
  99. #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
  100. /* Hub 5 */
  101. #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
  102. #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
  103. #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
  104. #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
  105. #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
  106. #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
  107. #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
  108. /* Hub 6 */
  109. #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
  110. #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
  111. #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
  112. #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
  113. #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
  114. #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
  115. #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
  116. #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
  117. #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
  118. /* This field defines PCI/X adr [25:20] of agents on the CRB */
  119. /* */
  120. #define QLA82XX_HW_PX_MAP_CRB_PH 0
  121. #define QLA82XX_HW_PX_MAP_CRB_PS 1
  122. #define QLA82XX_HW_PX_MAP_CRB_MN 2
  123. #define QLA82XX_HW_PX_MAP_CRB_MS 3
  124. #define QLA82XX_HW_PX_MAP_CRB_SRE 5
  125. #define QLA82XX_HW_PX_MAP_CRB_NIU 6
  126. #define QLA82XX_HW_PX_MAP_CRB_QMN 7
  127. #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
  128. #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
  129. #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
  130. #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
  131. #define QLA82XX_HW_PX_MAP_CRB_QMS 12
  132. #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
  133. #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
  134. #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
  135. #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
  136. #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
  137. #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
  138. #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
  139. #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
  140. #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
  141. #define QLA82XX_HW_PX_MAP_CRB_PGND 21
  142. #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
  143. #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
  144. #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
  145. #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
  146. #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
  147. #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
  148. #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
  149. #define QLA82XX_HW_PX_MAP_CRB_SN 29
  150. #define QLA82XX_HW_PX_MAP_CRB_EG 31
  151. #define QLA82XX_HW_PX_MAP_CRB_PH2 32
  152. #define QLA82XX_HW_PX_MAP_CRB_PS2 33
  153. #define QLA82XX_HW_PX_MAP_CRB_CAM 34
  154. #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
  155. #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
  156. #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
  157. #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
  158. #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
  159. #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
  160. #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
  161. #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
  162. #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
  163. #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
  164. #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
  165. #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
  166. #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
  167. #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
  168. #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
  169. #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
  170. #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
  171. #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
  172. #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
  173. #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
  174. #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
  175. #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
  176. #define QLA82XX_HW_PX_MAP_CRB_SMB 58
  177. #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
  178. #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
  179. #define QLA82XX_HW_PX_MAP_CRB_LPC 61
  180. #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
  181. #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
  182. #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
  183. #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
  184. #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
  185. /* This field defines CRB adr [31:20] of the agents */
  186. /* */
  187. #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
  188. QLA82XX_HW_MN_CRB_AGT_ADR)
  189. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
  190. QLA82XX_HW_PH_CRB_AGT_ADR)
  191. #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
  192. QLA82XX_HW_MS_CRB_AGT_ADR)
  193. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  194. QLA82XX_HW_PS_CRB_AGT_ADR)
  195. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  196. QLA82XX_HW_SS_CRB_AGT_ADR)
  197. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  198. QLA82XX_HW_RPMX3_CRB_AGT_ADR)
  199. #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  200. QLA82XX_HW_QMS_CRB_AGT_ADR)
  201. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  202. QLA82XX_HW_SQGS0_CRB_AGT_ADR)
  203. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  204. QLA82XX_HW_SQGS1_CRB_AGT_ADR)
  205. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  206. QLA82XX_HW_SQGS2_CRB_AGT_ADR)
  207. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  208. QLA82XX_HW_SQGS3_CRB_AGT_ADR)
  209. #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  210. QLA82XX_HW_C2C0_CRB_AGT_ADR)
  211. #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  212. QLA82XX_HW_C2C1_CRB_AGT_ADR)
  213. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  214. QLA82XX_HW_RPMX2_CRB_AGT_ADR)
  215. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  216. QLA82XX_HW_RPMX4_CRB_AGT_ADR)
  217. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  218. QLA82XX_HW_RPMX7_CRB_AGT_ADR)
  219. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  220. QLA82XX_HW_RPMX9_CRB_AGT_ADR)
  221. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
  222. QLA82XX_HW_SMB_CRB_AGT_ADR)
  223. #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
  224. QLA82XX_HW_NIU_CRB_AGT_ADR)
  225. #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
  226. QLA82XX_HW_I2C0_CRB_AGT_ADR)
  227. #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
  228. QLA82XX_HW_I2C1_CRB_AGT_ADR)
  229. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  230. QLA82XX_HW_SRE_CRB_AGT_ADR)
  231. #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  232. QLA82XX_HW_EG_CRB_AGT_ADR)
  233. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  234. QLA82XX_HW_RPMX0_CRB_AGT_ADR)
  235. #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  236. QLA82XX_HW_QM_CRB_AGT_ADR)
  237. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  238. QLA82XX_HW_SQG0_CRB_AGT_ADR)
  239. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  240. QLA82XX_HW_SQG1_CRB_AGT_ADR)
  241. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  242. QLA82XX_HW_SQG2_CRB_AGT_ADR)
  243. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  244. QLA82XX_HW_SQG3_CRB_AGT_ADR)
  245. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  246. QLA82XX_HW_RPMX1_CRB_AGT_ADR)
  247. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  248. QLA82XX_HW_RPMX5_CRB_AGT_ADR)
  249. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  250. QLA82XX_HW_RPMX6_CRB_AGT_ADR)
  251. #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  252. QLA82XX_HW_RPMX8_CRB_AGT_ADR)
  253. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  254. QLA82XX_HW_CAS0_CRB_AGT_ADR)
  255. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  256. QLA82XX_HW_CAS1_CRB_AGT_ADR)
  257. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  258. QLA82XX_HW_CAS2_CRB_AGT_ADR)
  259. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
  260. QLA82XX_HW_CAS3_CRB_AGT_ADR)
  261. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  262. QLA82XX_HW_PEGNI_CRB_AGT_ADR)
  263. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  264. QLA82XX_HW_PEGND_CRB_AGT_ADR)
  265. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  266. QLA82XX_HW_PEGN0_CRB_AGT_ADR)
  267. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  268. QLA82XX_HW_PEGN1_CRB_AGT_ADR)
  269. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  270. QLA82XX_HW_PEGN2_CRB_AGT_ADR)
  271. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  272. QLA82XX_HW_PEGN3_CRB_AGT_ADR)
  273. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  274. QLA82XX_HW_PEGN4_CRB_AGT_ADR)
  275. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  276. QLA82XX_HW_PEGNC_CRB_AGT_ADR)
  277. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  278. QLA82XX_HW_PEGR0_CRB_AGT_ADR)
  279. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  280. QLA82XX_HW_PEGR1_CRB_AGT_ADR)
  281. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  282. QLA82XX_HW_PEGR2_CRB_AGT_ADR)
  283. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
  284. QLA82XX_HW_PEGR3_CRB_AGT_ADR)
  285. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  286. QLA82XX_HW_PEGSI_CRB_AGT_ADR)
  287. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  288. QLA82XX_HW_PEGSD_CRB_AGT_ADR)
  289. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  290. QLA82XX_HW_PEGS0_CRB_AGT_ADR)
  291. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  292. QLA82XX_HW_PEGS1_CRB_AGT_ADR)
  293. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  294. QLA82XX_HW_PEGS2_CRB_AGT_ADR)
  295. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  296. QLA82XX_HW_PEGS3_CRB_AGT_ADR)
  297. #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
  298. QLA82XX_HW_PEGSC_CRB_AGT_ADR)
  299. #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  300. QLA82XX_HW_NCM_CRB_AGT_ADR)
  301. #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  302. QLA82XX_HW_TMR_CRB_AGT_ADR)
  303. #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  304. QLA82XX_HW_XDMA_CRB_AGT_ADR)
  305. #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  306. QLA82XX_HW_SN_CRB_AGT_ADR)
  307. #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  308. QLA82XX_HW_I2Q_CRB_AGT_ADR)
  309. #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  310. QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
  311. #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  312. QLA82XX_HW_OCM0_CRB_AGT_ADR)
  313. #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  314. QLA82XX_HW_OCM1_CRB_AGT_ADR)
  315. #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
  316. QLA82XX_HW_LPC_CRB_AGT_ADR)
  317. #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
  318. #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
  319. #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
  320. #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
  321. #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
  322. #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
  323. #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
  324. #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
  325. #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
  326. #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
  327. #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
  328. #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
  329. /* Lock IDs for ROM lock */
  330. #define ROM_LOCK_DRIVER 0x0d417340
  331. #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
  332. #define QLA82XX_PCI_CRB_WINDOW(A) (QLA82XX_PCI_CRBSPACE + \
  333. (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
  334. #define QLA82XX_CRB_C2C_0 \
  335. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
  336. #define QLA82XX_CRB_C2C_1 \
  337. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
  338. #define QLA82XX_CRB_C2C_2 \
  339. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
  340. #define QLA82XX_CRB_CAM \
  341. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
  342. #define QLA82XX_CRB_CASPER \
  343. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
  344. #define QLA82XX_CRB_CASPER_0 \
  345. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
  346. #define QLA82XX_CRB_CASPER_1 \
  347. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
  348. #define QLA82XX_CRB_CASPER_2 \
  349. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
  350. #define QLA82XX_CRB_DDR_MD \
  351. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
  352. #define QLA82XX_CRB_DDR_NET \
  353. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
  354. #define QLA82XX_CRB_EPG \
  355. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
  356. #define QLA82XX_CRB_I2Q \
  357. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
  358. #define QLA82XX_CRB_NIU \
  359. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
  360. /* HACK upon HACK upon HACK (for PCIE builds) */
  361. #define QLA82XX_CRB_PCIX_HOST \
  362. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
  363. #define QLA82XX_CRB_PCIX_HOST2 \
  364. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
  365. #define QLA82XX_CRB_PCIX_MD \
  366. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
  367. #define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD
  368. /* window 1 pcie slot */
  369. #define QLA82XX_CRB_PCIE2 \
  370. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
  371. #define QLA82XX_CRB_PEG_MD_0 \
  372. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
  373. #define QLA82XX_CRB_PEG_MD_1 \
  374. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
  375. #define QLA82XX_CRB_PEG_MD_2 \
  376. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
  377. #define QLA82XX_CRB_PEG_MD_3 \
  378. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
  379. #define QLA82XX_CRB_PEG_MD_3 \
  380. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
  381. #define QLA82XX_CRB_PEG_MD_D \
  382. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
  383. #define QLA82XX_CRB_PEG_MD_I \
  384. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
  385. #define QLA82XX_CRB_PEG_NET_0 \
  386. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
  387. #define QLA82XX_CRB_PEG_NET_1 \
  388. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
  389. #define QLA82XX_CRB_PEG_NET_2 \
  390. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
  391. #define QLA82XX_CRB_PEG_NET_3 \
  392. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
  393. #define QLA82XX_CRB_PEG_NET_4 \
  394. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
  395. #define QLA82XX_CRB_PEG_NET_D \
  396. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
  397. #define QLA82XX_CRB_PEG_NET_I \
  398. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
  399. #define QLA82XX_CRB_PQM_MD \
  400. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
  401. #define QLA82XX_CRB_PQM_NET \
  402. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
  403. #define QLA82XX_CRB_QDR_MD \
  404. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
  405. #define QLA82XX_CRB_QDR_NET \
  406. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
  407. #define QLA82XX_CRB_ROMUSB \
  408. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
  409. #define QLA82XX_CRB_RPMX_0 \
  410. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
  411. #define QLA82XX_CRB_RPMX_1 \
  412. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
  413. #define QLA82XX_CRB_RPMX_2 \
  414. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
  415. #define QLA82XX_CRB_RPMX_3 \
  416. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
  417. #define QLA82XX_CRB_RPMX_4 \
  418. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
  419. #define QLA82XX_CRB_RPMX_5 \
  420. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
  421. #define QLA82XX_CRB_RPMX_6 \
  422. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
  423. #define QLA82XX_CRB_RPMX_7 \
  424. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
  425. #define QLA82XX_CRB_SQM_MD_0 \
  426. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
  427. #define QLA82XX_CRB_SQM_MD_1 \
  428. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
  429. #define QLA82XX_CRB_SQM_MD_2 \
  430. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
  431. #define QLA82XX_CRB_SQM_MD_3 \
  432. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
  433. #define QLA82XX_CRB_SQM_NET_0 \
  434. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
  435. #define QLA82XX_CRB_SQM_NET_1 \
  436. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
  437. #define QLA82XX_CRB_SQM_NET_2 \
  438. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
  439. #define QLA82XX_CRB_SQM_NET_3 \
  440. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
  441. #define QLA82XX_CRB_SRE \
  442. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
  443. #define QLA82XX_CRB_TIMER \
  444. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
  445. #define QLA82XX_CRB_XDMA \
  446. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
  447. #define QLA82XX_CRB_I2C0 \
  448. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
  449. #define QLA82XX_CRB_I2C1 \
  450. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
  451. #define QLA82XX_CRB_OCM0 \
  452. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
  453. #define QLA82XX_CRB_SMB \
  454. QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
  455. #define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64)
  456. /*
  457. * ====================== BASE ADDRESSES ON-CHIP ======================
  458. * Base addresses of major components on-chip.
  459. * ====================== BASE ADDRESSES ON-CHIP ======================
  460. */
  461. #define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)
  462. #define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
  463. /* Imbus address bit used to indicate a host address. This bit is
  464. * eliminated by the pcie bar and bar select before presentation
  465. * over pcie. */
  466. /* host memory via IMBUS */
  467. #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
  468. #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
  469. #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
  470. #define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)
  471. #define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)
  472. #define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)
  473. #define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)
  474. #define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)
  475. #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
  476. #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
  477. #define QLA8XXX_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
  478. #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
  479. #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
  480. #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
  481. #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
  482. #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
  483. #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
  484. #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
  485. /* PCI Windowing for DDR regions. */
  486. #define QLA8XXX_ADDR_IN_RANGE(addr, low, high) \
  487. (((addr) <= (high)) && ((addr) >= (low)))
  488. /*
  489. * Register offsets for MN
  490. */
  491. #define MIU_CONTROL (0x000)
  492. #define MIU_TAG (0x004)
  493. #define MIU_TEST_AGT_CTRL (0x090)
  494. #define MIU_TEST_AGT_ADDR_LO (0x094)
  495. #define MIU_TEST_AGT_ADDR_HI (0x098)
  496. #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
  497. #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
  498. #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
  499. #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
  500. #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
  501. #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
  502. #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
  503. #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
  504. /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
  505. #define MIU_TA_CTL_START 1
  506. #define MIU_TA_CTL_ENABLE 2
  507. #define MIU_TA_CTL_WRITE 4
  508. #define MIU_TA_CTL_BUSY 8
  509. #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
  510. #define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE |\
  511. MIU_TA_CTL_START)
  512. #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
  513. /*CAM RAM */
  514. # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
  515. # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
  516. #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
  517. #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
  518. #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
  519. #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
  520. #define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))
  521. #define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))
  522. #define HALT_STATUS_UNRECOVERABLE 0x80000000
  523. #define HALT_STATUS_RECOVERABLE 0x40000000
  524. #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
  525. #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
  526. #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
  527. #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
  528. #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
  529. #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
  530. /* Driver Coexistence Defines */
  531. #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
  532. #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
  533. #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
  534. #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
  535. #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
  536. #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
  537. enum qla_regs {
  538. QLA8XXX_PEG_HALT_STATUS1 = 0,
  539. QLA8XXX_PEG_HALT_STATUS2,
  540. QLA8XXX_PEG_ALIVE_COUNTER,
  541. QLA8XXX_CRB_DRV_ACTIVE,
  542. QLA8XXX_CRB_DEV_STATE,
  543. QLA8XXX_CRB_DRV_STATE,
  544. QLA8XXX_CRB_DRV_SCRATCH,
  545. QLA8XXX_CRB_DEV_PART_INFO,
  546. QLA8XXX_CRB_DRV_IDC_VERSION,
  547. QLA8XXX_FW_VERSION_MAJOR,
  548. QLA8XXX_FW_VERSION_MINOR,
  549. QLA8XXX_FW_VERSION_SUB,
  550. QLA8XXX_CRB_CMDPEG_STATE,
  551. QLA8XXX_CRB_TEMP_STATE,
  552. };
  553. /* Every driver should use these Device State */
  554. #define QLA8XXX_DEV_COLD 1
  555. #define QLA8XXX_DEV_INITIALIZING 2
  556. #define QLA8XXX_DEV_READY 3
  557. #define QLA8XXX_DEV_NEED_RESET 4
  558. #define QLA8XXX_DEV_NEED_QUIESCENT 5
  559. #define QLA8XXX_DEV_FAILED 6
  560. #define QLA8XXX_DEV_QUIESCENT 7
  561. #define MAX_STATES 8 /* Increment if new state added */
  562. #define QLA82XX_IDC_VERSION 0x1
  563. #define ROM_DEV_INIT_TIMEOUT 30
  564. #define ROM_DRV_RESET_ACK_TIMEOUT 10
  565. #define PCIE_SETUP_FUNCTION (0x12040)
  566. #define PCIE_SETUP_FUNCTION2 (0x12048)
  567. #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
  568. #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
  569. #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
  570. #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
  571. #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
  572. #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
  573. #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
  574. #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
  575. /*
  576. * The PCI VendorID and DeviceID for our board.
  577. */
  578. #define QLA82XX_MSIX_TBL_SPACE 8192
  579. #define QLA82XX_PCI_REG_MSIX_TBL 0x44
  580. #define QLA82XX_PCI_MSIX_CONTROL 0x40
  581. struct crb_128M_2M_sub_block_map {
  582. unsigned valid;
  583. unsigned start_128M;
  584. unsigned end_128M;
  585. unsigned start_2M;
  586. };
  587. struct crb_128M_2M_block_map {
  588. struct crb_128M_2M_sub_block_map sub_block[16];
  589. };
  590. struct crb_addr_pair {
  591. long addr;
  592. long data;
  593. };
  594. #define ADDR_ERROR ((unsigned long) 0xffffffff)
  595. #define MAX_CTL_CHECK 1000
  596. #define QLA82XX_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)
  597. /***************************************************************************
  598. * PCI related defines.
  599. **************************************************************************/
  600. /*
  601. * Interrupt related defines.
  602. */
  603. #define PCIX_TARGET_STATUS (0x10118)
  604. #define PCIX_TARGET_STATUS_F1 (0x10160)
  605. #define PCIX_TARGET_STATUS_F2 (0x10164)
  606. #define PCIX_TARGET_STATUS_F3 (0x10168)
  607. #define PCIX_TARGET_STATUS_F4 (0x10360)
  608. #define PCIX_TARGET_STATUS_F5 (0x10364)
  609. #define PCIX_TARGET_STATUS_F6 (0x10368)
  610. #define PCIX_TARGET_STATUS_F7 (0x1036c)
  611. #define PCIX_TARGET_MASK (0x10128)
  612. #define PCIX_TARGET_MASK_F1 (0x10170)
  613. #define PCIX_TARGET_MASK_F2 (0x10174)
  614. #define PCIX_TARGET_MASK_F3 (0x10178)
  615. #define PCIX_TARGET_MASK_F4 (0x10370)
  616. #define PCIX_TARGET_MASK_F5 (0x10374)
  617. #define PCIX_TARGET_MASK_F6 (0x10378)
  618. #define PCIX_TARGET_MASK_F7 (0x1037c)
  619. /*
  620. * Message Signaled Interrupts
  621. */
  622. #define PCIX_MSI_F0 (0x13000)
  623. #define PCIX_MSI_F1 (0x13004)
  624. #define PCIX_MSI_F2 (0x13008)
  625. #define PCIX_MSI_F3 (0x1300c)
  626. #define PCIX_MSI_F4 (0x13010)
  627. #define PCIX_MSI_F5 (0x13014)
  628. #define PCIX_MSI_F6 (0x13018)
  629. #define PCIX_MSI_F7 (0x1301c)
  630. #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
  631. /*
  632. *
  633. */
  634. #define PCIX_INT_VECTOR (0x10100)
  635. #define PCIX_INT_MASK (0x10104)
  636. /*
  637. * Interrupt state machine and other bits.
  638. */
  639. #define PCIE_MISCCFG_RC (0x1206c)
  640. #define ISR_INT_TARGET_STATUS \
  641. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
  642. #define ISR_INT_TARGET_STATUS_F1 \
  643. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
  644. #define ISR_INT_TARGET_STATUS_F2 \
  645. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
  646. #define ISR_INT_TARGET_STATUS_F3 \
  647. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
  648. #define ISR_INT_TARGET_STATUS_F4 \
  649. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
  650. #define ISR_INT_TARGET_STATUS_F5 \
  651. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
  652. #define ISR_INT_TARGET_STATUS_F6 \
  653. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
  654. #define ISR_INT_TARGET_STATUS_F7 \
  655. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
  656. #define ISR_INT_TARGET_MASK \
  657. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
  658. #define ISR_INT_TARGET_MASK_F1 \
  659. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
  660. #define ISR_INT_TARGET_MASK_F2 \
  661. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
  662. #define ISR_INT_TARGET_MASK_F3 \
  663. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
  664. #define ISR_INT_TARGET_MASK_F4 \
  665. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
  666. #define ISR_INT_TARGET_MASK_F5 \
  667. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
  668. #define ISR_INT_TARGET_MASK_F6 \
  669. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
  670. #define ISR_INT_TARGET_MASK_F7 \
  671. (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
  672. #define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
  673. #define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
  674. #define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
  675. #define ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
  676. #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
  677. #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
  678. /*
  679. * PCI Interrupt Vector Values.
  680. */
  681. #define PCIX_INT_VECTOR_BIT_F0 0x0080
  682. #define PCIX_INT_VECTOR_BIT_F1 0x0100
  683. #define PCIX_INT_VECTOR_BIT_F2 0x0200
  684. #define PCIX_INT_VECTOR_BIT_F3 0x0400
  685. #define PCIX_INT_VECTOR_BIT_F4 0x0800
  686. #define PCIX_INT_VECTOR_BIT_F5 0x1000
  687. #define PCIX_INT_VECTOR_BIT_F6 0x2000
  688. #define PCIX_INT_VECTOR_BIT_F7 0x4000
  689. /* struct qla4_8xxx_legacy_intr_set defined in ql4_def.h */
  690. #define QLA82XX_LEGACY_INTR_CONFIG \
  691. { \
  692. { \
  693. .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
  694. .tgt_status_reg = ISR_INT_TARGET_STATUS, \
  695. .tgt_mask_reg = ISR_INT_TARGET_MASK, \
  696. .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
  697. \
  698. { \
  699. .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
  700. .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
  701. .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
  702. .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
  703. \
  704. { \
  705. .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
  706. .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
  707. .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
  708. .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
  709. \
  710. { \
  711. .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
  712. .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
  713. .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
  714. .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
  715. \
  716. { \
  717. .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
  718. .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
  719. .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
  720. .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
  721. \
  722. { \
  723. .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
  724. .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
  725. .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
  726. .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
  727. \
  728. { \
  729. .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
  730. .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
  731. .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
  732. .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
  733. \
  734. { \
  735. .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
  736. .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
  737. .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
  738. .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
  739. }
  740. /* Magic number to let user know flash is programmed */
  741. #define QLA82XX_BDINFO_MAGIC 0x12345678
  742. #define FW_SIZE_OFFSET (0x3e840c)
  743. /* QLA82XX additions */
  744. #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
  745. #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
  746. /* Minidump related */
  747. /* Entry Type Defines */
  748. #define QLA8XXX_RDNOP 0
  749. #define QLA8XXX_RDCRB 1
  750. #define QLA8XXX_RDMUX 2
  751. #define QLA8XXX_QUEUE 3
  752. #define QLA8XXX_BOARD 4
  753. #define QLA8XXX_RDOCM 6
  754. #define QLA8XXX_PREGS 7
  755. #define QLA8XXX_L1DTG 8
  756. #define QLA8XXX_L1ITG 9
  757. #define QLA8XXX_L1DAT 11
  758. #define QLA8XXX_L1INS 12
  759. #define QLA8XXX_L2DTG 21
  760. #define QLA8XXX_L2ITG 22
  761. #define QLA8XXX_L2DAT 23
  762. #define QLA8XXX_L2INS 24
  763. #define QLA83XX_POLLRD 35
  764. #define QLA83XX_RDMUX2 36
  765. #define QLA83XX_POLLRDMWR 37
  766. #define QLA8044_RDDFE 38
  767. #define QLA8044_RDMDIO 39
  768. #define QLA8044_POLLWR 40
  769. #define QLA8XXX_RDROM 71
  770. #define QLA8XXX_RDMEM 72
  771. #define QLA8XXX_CNTRL 98
  772. #define QLA83XX_TLHDR 99
  773. #define QLA8XXX_RDEND 255
  774. /* Opcodes for Control Entries.
  775. * These Flags are bit fields.
  776. */
  777. #define QLA8XXX_DBG_OPCODE_WR 0x01
  778. #define QLA8XXX_DBG_OPCODE_RW 0x02
  779. #define QLA8XXX_DBG_OPCODE_AND 0x04
  780. #define QLA8XXX_DBG_OPCODE_OR 0x08
  781. #define QLA8XXX_DBG_OPCODE_POLL 0x10
  782. #define QLA8XXX_DBG_OPCODE_RDSTATE 0x20
  783. #define QLA8XXX_DBG_OPCODE_WRSTATE 0x40
  784. #define QLA8XXX_DBG_OPCODE_MDSTATE 0x80
  785. /* Driver Flags */
  786. #define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
  787. #define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
  788. * mismatch */
  789. /* Driver_code is for driver to write some info about the entry
  790. * currently not used.
  791. */
  792. struct qla8xxx_minidump_entry_hdr {
  793. uint32_t entry_type;
  794. uint32_t entry_size;
  795. uint32_t entry_capture_size;
  796. struct {
  797. uint8_t entry_capture_mask;
  798. uint8_t entry_code;
  799. uint8_t driver_code;
  800. uint8_t driver_flags;
  801. } d_ctrl;
  802. };
  803. /* Read CRB entry header */
  804. struct qla8xxx_minidump_entry_crb {
  805. struct qla8xxx_minidump_entry_hdr h;
  806. uint32_t addr;
  807. struct {
  808. uint8_t addr_stride;
  809. uint8_t state_index_a;
  810. uint16_t poll_timeout;
  811. } crb_strd;
  812. uint32_t data_size;
  813. uint32_t op_count;
  814. struct {
  815. uint8_t opcode;
  816. uint8_t state_index_v;
  817. uint8_t shl;
  818. uint8_t shr;
  819. } crb_ctrl;
  820. uint32_t value_1;
  821. uint32_t value_2;
  822. uint32_t value_3;
  823. };
  824. struct qla8xxx_minidump_entry_cache {
  825. struct qla8xxx_minidump_entry_hdr h;
  826. uint32_t tag_reg_addr;
  827. struct {
  828. uint16_t tag_value_stride;
  829. uint16_t init_tag_value;
  830. } addr_ctrl;
  831. uint32_t data_size;
  832. uint32_t op_count;
  833. uint32_t control_addr;
  834. struct {
  835. uint16_t write_value;
  836. uint8_t poll_mask;
  837. uint8_t poll_wait;
  838. } cache_ctrl;
  839. uint32_t read_addr;
  840. struct {
  841. uint8_t read_addr_stride;
  842. uint8_t read_addr_cnt;
  843. uint16_t rsvd_1;
  844. } read_ctrl;
  845. };
  846. /* Read OCM */
  847. struct qla8xxx_minidump_entry_rdocm {
  848. struct qla8xxx_minidump_entry_hdr h;
  849. uint32_t rsvd_0;
  850. uint32_t rsvd_1;
  851. uint32_t data_size;
  852. uint32_t op_count;
  853. uint32_t rsvd_2;
  854. uint32_t rsvd_3;
  855. uint32_t read_addr;
  856. uint32_t read_addr_stride;
  857. };
  858. /* Read Memory */
  859. struct qla8xxx_minidump_entry_rdmem {
  860. struct qla8xxx_minidump_entry_hdr h;
  861. uint32_t rsvd[6];
  862. uint32_t read_addr;
  863. uint32_t read_data_size;
  864. };
  865. /* Read ROM */
  866. struct qla8xxx_minidump_entry_rdrom {
  867. struct qla8xxx_minidump_entry_hdr h;
  868. uint32_t rsvd[6];
  869. uint32_t read_addr;
  870. uint32_t read_data_size;
  871. };
  872. /* Mux entry */
  873. struct qla8xxx_minidump_entry_mux {
  874. struct qla8xxx_minidump_entry_hdr h;
  875. uint32_t select_addr;
  876. uint32_t rsvd_0;
  877. uint32_t data_size;
  878. uint32_t op_count;
  879. uint32_t select_value;
  880. uint32_t select_value_stride;
  881. uint32_t read_addr;
  882. uint32_t rsvd_1;
  883. };
  884. /* Queue entry */
  885. struct qla8xxx_minidump_entry_queue {
  886. struct qla8xxx_minidump_entry_hdr h;
  887. uint32_t select_addr;
  888. struct {
  889. uint16_t queue_id_stride;
  890. uint16_t rsvd_0;
  891. } q_strd;
  892. uint32_t data_size;
  893. uint32_t op_count;
  894. uint32_t rsvd_1;
  895. uint32_t rsvd_2;
  896. uint32_t read_addr;
  897. struct {
  898. uint8_t read_addr_stride;
  899. uint8_t read_addr_cnt;
  900. uint16_t rsvd_3;
  901. } rd_strd;
  902. };
  903. #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
  904. #define RQST_TMPLT_SIZE 0x0
  905. #define RQST_TMPLT 0x1
  906. #define MD_DIRECT_ROM_WINDOW 0x42110030
  907. #define MD_DIRECT_ROM_READ_BASE 0x42150000
  908. #define MD_MIU_TEST_AGT_CTRL 0x41000090
  909. #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
  910. #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
  911. #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
  912. #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
  913. #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
  914. #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
  915. #endif