arcmsr_hba.c 146 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Nick Cheng, C.L. Huang
  6. ** Description: SCSI RAID Device Driver for Areca RAID Controller
  7. *******************************************************************************
  8. ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
  9. **
  10. ** Web site: www.areca.com.tw
  11. ** E-mail: [email protected]
  12. **
  13. ** This program is free software; you can redistribute it and/or modify
  14. ** it under the terms of the GNU General Public License version 2 as
  15. ** published by the Free Software Foundation.
  16. ** This program is distributed in the hope that it will be useful,
  17. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. ** GNU General Public License for more details.
  20. *******************************************************************************
  21. ** Redistribution and use in source and binary forms, with or without
  22. ** modification, are permitted provided that the following conditions
  23. ** are met:
  24. ** 1. Redistributions of source code must retain the above copyright
  25. ** notice, this list of conditions and the following disclaimer.
  26. ** 2. Redistributions in binary form must reproduce the above copyright
  27. ** notice, this list of conditions and the following disclaimer in the
  28. ** documentation and/or other materials provided with the distribution.
  29. ** 3. The name of the author may not be used to endorse or promote products
  30. ** derived from this software without specific prior written permission.
  31. **
  32. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  33. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  34. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  35. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  36. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  37. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  39. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  41. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *******************************************************************************
  43. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  44. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.rst
  45. *******************************************************************************
  46. */
  47. #include <linux/module.h>
  48. #include <linux/reboot.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/pci_ids.h>
  51. #include <linux/interrupt.h>
  52. #include <linux/moduleparam.h>
  53. #include <linux/errno.h>
  54. #include <linux/types.h>
  55. #include <linux/delay.h>
  56. #include <linux/dma-mapping.h>
  57. #include <linux/timer.h>
  58. #include <linux/slab.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <linux/circ_buf.h>
  62. #include <asm/dma.h>
  63. #include <asm/io.h>
  64. #include <linux/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Nick Cheng, C.L. Huang <[email protected]>");
  74. MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. static int msix_enable = 1;
  78. module_param(msix_enable, int, S_IRUGO);
  79. MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)");
  80. static int msi_enable = 1;
  81. module_param(msi_enable, int, S_IRUGO);
  82. MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)");
  83. static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
  84. module_param(host_can_queue, int, S_IRUGO);
  85. MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128");
  86. static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
  87. module_param(cmd_per_lun, int, S_IRUGO);
  88. MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32");
  89. static int dma_mask_64 = 0;
  90. module_param(dma_mask_64, int, S_IRUGO);
  91. MODULE_PARM_DESC(dma_mask_64, " set DMA mask to 64 bits(0 ~ 1), dma_mask_64=1(64 bits), =0(32 bits)");
  92. static int set_date_time = 0;
  93. module_param(set_date_time, int, S_IRUGO);
  94. MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable");
  95. static int cmd_timeout = ARCMSR_DEFAULT_TIMEOUT;
  96. module_param(cmd_timeout, int, S_IRUGO);
  97. MODULE_PARM_DESC(cmd_timeout, " scsi cmd timeout(0 ~ 120 sec.), default is 90");
  98. #define ARCMSR_SLEEPTIME 10
  99. #define ARCMSR_RETRYCOUNT 12
  100. static wait_queue_head_t wait_q;
  101. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  102. struct scsi_cmnd *cmd);
  103. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  104. static int arcmsr_abort(struct scsi_cmnd *);
  105. static int arcmsr_bus_reset(struct scsi_cmnd *);
  106. static int arcmsr_bios_param(struct scsi_device *sdev,
  107. struct block_device *bdev, sector_t capacity, int *info);
  108. static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  109. static int arcmsr_probe(struct pci_dev *pdev,
  110. const struct pci_device_id *id);
  111. static int __maybe_unused arcmsr_suspend(struct device *dev);
  112. static int __maybe_unused arcmsr_resume(struct device *dev);
  113. static void arcmsr_remove(struct pci_dev *pdev);
  114. static void arcmsr_shutdown(struct pci_dev *pdev);
  115. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  116. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  117. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  118. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  119. u32 intmask_org);
  120. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  121. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
  122. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
  123. static void arcmsr_request_device_map(struct timer_list *t);
  124. static void arcmsr_message_isr_bh_fn(struct work_struct *work);
  125. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
  126. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
  127. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
  128. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
  129. static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb);
  130. static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb);
  131. static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb);
  132. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
  133. static const char *arcmsr_info(struct Scsi_Host *);
  134. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  135. static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
  136. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
  137. static void arcmsr_set_iop_datetime(struct timer_list *);
  138. static int arcmsr_slave_config(struct scsi_device *sdev);
  139. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
  140. {
  141. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  142. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  143. return scsi_change_queue_depth(sdev, queue_depth);
  144. }
  145. static struct scsi_host_template arcmsr_scsi_host_template = {
  146. .module = THIS_MODULE,
  147. .name = "Areca SAS/SATA RAID driver",
  148. .info = arcmsr_info,
  149. .queuecommand = arcmsr_queue_command,
  150. .eh_abort_handler = arcmsr_abort,
  151. .eh_bus_reset_handler = arcmsr_bus_reset,
  152. .bios_param = arcmsr_bios_param,
  153. .slave_configure = arcmsr_slave_config,
  154. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  155. .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
  156. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  157. .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
  158. .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
  159. .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
  160. .shost_groups = arcmsr_host_groups,
  161. .no_write_same = 1,
  162. };
  163. static struct pci_device_id arcmsr_device_id_table[] = {
  164. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
  165. .driver_data = ACB_ADAPTER_TYPE_A},
  166. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
  167. .driver_data = ACB_ADAPTER_TYPE_A},
  168. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
  169. .driver_data = ACB_ADAPTER_TYPE_A},
  170. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
  171. .driver_data = ACB_ADAPTER_TYPE_A},
  172. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
  173. .driver_data = ACB_ADAPTER_TYPE_A},
  174. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
  175. .driver_data = ACB_ADAPTER_TYPE_B},
  176. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
  177. .driver_data = ACB_ADAPTER_TYPE_B},
  178. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
  179. .driver_data = ACB_ADAPTER_TYPE_B},
  180. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
  181. .driver_data = ACB_ADAPTER_TYPE_B},
  182. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
  183. .driver_data = ACB_ADAPTER_TYPE_A},
  184. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
  185. .driver_data = ACB_ADAPTER_TYPE_D},
  186. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
  187. .driver_data = ACB_ADAPTER_TYPE_A},
  188. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
  189. .driver_data = ACB_ADAPTER_TYPE_A},
  190. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
  191. .driver_data = ACB_ADAPTER_TYPE_A},
  192. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
  193. .driver_data = ACB_ADAPTER_TYPE_A},
  194. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
  195. .driver_data = ACB_ADAPTER_TYPE_A},
  196. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
  197. .driver_data = ACB_ADAPTER_TYPE_A},
  198. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
  199. .driver_data = ACB_ADAPTER_TYPE_A},
  200. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
  201. .driver_data = ACB_ADAPTER_TYPE_A},
  202. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
  203. .driver_data = ACB_ADAPTER_TYPE_A},
  204. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
  205. .driver_data = ACB_ADAPTER_TYPE_C},
  206. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884),
  207. .driver_data = ACB_ADAPTER_TYPE_E},
  208. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1886),
  209. .driver_data = ACB_ADAPTER_TYPE_F},
  210. {0, 0}, /* Terminating entry */
  211. };
  212. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  213. static SIMPLE_DEV_PM_OPS(arcmsr_pm_ops, arcmsr_suspend, arcmsr_resume);
  214. static struct pci_driver arcmsr_pci_driver = {
  215. .name = "arcmsr",
  216. .id_table = arcmsr_device_id_table,
  217. .probe = arcmsr_probe,
  218. .remove = arcmsr_remove,
  219. .driver.pm = &arcmsr_pm_ops,
  220. .shutdown = arcmsr_shutdown,
  221. };
  222. /*
  223. ****************************************************************************
  224. ****************************************************************************
  225. */
  226. static void arcmsr_free_io_queue(struct AdapterControlBlock *acb)
  227. {
  228. switch (acb->adapter_type) {
  229. case ACB_ADAPTER_TYPE_B:
  230. case ACB_ADAPTER_TYPE_D:
  231. case ACB_ADAPTER_TYPE_E:
  232. case ACB_ADAPTER_TYPE_F:
  233. dma_free_coherent(&acb->pdev->dev, acb->ioqueue_size,
  234. acb->dma_coherent2, acb->dma_coherent_handle2);
  235. break;
  236. }
  237. }
  238. static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
  239. {
  240. struct pci_dev *pdev = acb->pdev;
  241. switch (acb->adapter_type){
  242. case ACB_ADAPTER_TYPE_A:{
  243. acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
  244. if (!acb->pmuA) {
  245. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  246. return false;
  247. }
  248. break;
  249. }
  250. case ACB_ADAPTER_TYPE_B:{
  251. void __iomem *mem_base0, *mem_base1;
  252. mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  253. if (!mem_base0) {
  254. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  255. return false;
  256. }
  257. mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
  258. if (!mem_base1) {
  259. iounmap(mem_base0);
  260. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  261. return false;
  262. }
  263. acb->mem_base0 = mem_base0;
  264. acb->mem_base1 = mem_base1;
  265. break;
  266. }
  267. case ACB_ADAPTER_TYPE_C:{
  268. acb->pmuC = ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
  269. if (!acb->pmuC) {
  270. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  271. return false;
  272. }
  273. if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  274. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
  275. return true;
  276. }
  277. break;
  278. }
  279. case ACB_ADAPTER_TYPE_D: {
  280. void __iomem *mem_base0;
  281. unsigned long addr, range;
  282. addr = (unsigned long)pci_resource_start(pdev, 0);
  283. range = pci_resource_len(pdev, 0);
  284. mem_base0 = ioremap(addr, range);
  285. if (!mem_base0) {
  286. pr_notice("arcmsr%d: memory mapping region fail\n",
  287. acb->host->host_no);
  288. return false;
  289. }
  290. acb->mem_base0 = mem_base0;
  291. break;
  292. }
  293. case ACB_ADAPTER_TYPE_E: {
  294. acb->pmuE = ioremap(pci_resource_start(pdev, 1),
  295. pci_resource_len(pdev, 1));
  296. if (!acb->pmuE) {
  297. pr_notice("arcmsr%d: memory mapping region fail \n",
  298. acb->host->host_no);
  299. return false;
  300. }
  301. writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/
  302. writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */
  303. acb->in_doorbell = 0;
  304. acb->out_doorbell = 0;
  305. break;
  306. }
  307. case ACB_ADAPTER_TYPE_F: {
  308. acb->pmuF = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  309. if (!acb->pmuF) {
  310. pr_notice("arcmsr%d: memory mapping region fail\n",
  311. acb->host->host_no);
  312. return false;
  313. }
  314. writel(0, &acb->pmuF->host_int_status); /* clear interrupt */
  315. writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
  316. acb->in_doorbell = 0;
  317. acb->out_doorbell = 0;
  318. break;
  319. }
  320. }
  321. return true;
  322. }
  323. static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
  324. {
  325. switch (acb->adapter_type) {
  326. case ACB_ADAPTER_TYPE_A:
  327. iounmap(acb->pmuA);
  328. break;
  329. case ACB_ADAPTER_TYPE_B:
  330. iounmap(acb->mem_base0);
  331. iounmap(acb->mem_base1);
  332. break;
  333. case ACB_ADAPTER_TYPE_C:
  334. iounmap(acb->pmuC);
  335. break;
  336. case ACB_ADAPTER_TYPE_D:
  337. iounmap(acb->mem_base0);
  338. break;
  339. case ACB_ADAPTER_TYPE_E:
  340. iounmap(acb->pmuE);
  341. break;
  342. case ACB_ADAPTER_TYPE_F:
  343. iounmap(acb->pmuF);
  344. break;
  345. }
  346. }
  347. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  348. {
  349. irqreturn_t handle_state;
  350. struct AdapterControlBlock *acb = dev_id;
  351. handle_state = arcmsr_interrupt(acb);
  352. return handle_state;
  353. }
  354. static int arcmsr_bios_param(struct scsi_device *sdev,
  355. struct block_device *bdev, sector_t capacity, int *geom)
  356. {
  357. int heads, sectors, cylinders, total_capacity;
  358. if (scsi_partsize(bdev, capacity, geom))
  359. return 0;
  360. total_capacity = capacity;
  361. heads = 64;
  362. sectors = 32;
  363. cylinders = total_capacity / (heads * sectors);
  364. if (cylinders > 1024) {
  365. heads = 255;
  366. sectors = 63;
  367. cylinders = total_capacity / (heads * sectors);
  368. }
  369. geom[0] = heads;
  370. geom[1] = sectors;
  371. geom[2] = cylinders;
  372. return 0;
  373. }
  374. static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
  375. {
  376. struct MessageUnit_A __iomem *reg = acb->pmuA;
  377. int i;
  378. for (i = 0; i < 2000; i++) {
  379. if (readl(&reg->outbound_intstatus) &
  380. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  381. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  382. &reg->outbound_intstatus);
  383. return true;
  384. }
  385. msleep(10);
  386. } /* max 20 seconds */
  387. return false;
  388. }
  389. static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
  390. {
  391. struct MessageUnit_B *reg = acb->pmuB;
  392. int i;
  393. for (i = 0; i < 2000; i++) {
  394. if (readl(reg->iop2drv_doorbell)
  395. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  396. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
  397. reg->iop2drv_doorbell);
  398. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
  399. reg->drv2iop_doorbell);
  400. return true;
  401. }
  402. msleep(10);
  403. } /* max 20 seconds */
  404. return false;
  405. }
  406. static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
  407. {
  408. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  409. int i;
  410. for (i = 0; i < 2000; i++) {
  411. if (readl(&phbcmu->outbound_doorbell)
  412. & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  413. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
  414. &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
  415. return true;
  416. }
  417. msleep(10);
  418. } /* max 20 seconds */
  419. return false;
  420. }
  421. static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
  422. {
  423. struct MessageUnit_D *reg = pACB->pmuD;
  424. int i;
  425. for (i = 0; i < 2000; i++) {
  426. if (readl(reg->outbound_doorbell)
  427. & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  428. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  429. reg->outbound_doorbell);
  430. return true;
  431. }
  432. msleep(10);
  433. } /* max 20 seconds */
  434. return false;
  435. }
  436. static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB)
  437. {
  438. int i;
  439. uint32_t read_doorbell;
  440. struct MessageUnit_E __iomem *phbcmu = pACB->pmuE;
  441. for (i = 0; i < 2000; i++) {
  442. read_doorbell = readl(&phbcmu->iobound_doorbell);
  443. if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
  444. writel(0, &phbcmu->host_int_status); /*clear interrupt*/
  445. pACB->in_doorbell = read_doorbell;
  446. return true;
  447. }
  448. msleep(10);
  449. } /* max 20 seconds */
  450. return false;
  451. }
  452. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
  453. {
  454. struct MessageUnit_A __iomem *reg = acb->pmuA;
  455. int retry_count = 30;
  456. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  457. do {
  458. if (arcmsr_hbaA_wait_msgint_ready(acb))
  459. break;
  460. else {
  461. retry_count--;
  462. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  463. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  464. }
  465. } while (retry_count != 0);
  466. }
  467. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
  468. {
  469. struct MessageUnit_B *reg = acb->pmuB;
  470. int retry_count = 30;
  471. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
  472. do {
  473. if (arcmsr_hbaB_wait_msgint_ready(acb))
  474. break;
  475. else {
  476. retry_count--;
  477. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  478. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  479. }
  480. } while (retry_count != 0);
  481. }
  482. static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
  483. {
  484. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  485. int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
  486. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  487. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  488. do {
  489. if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
  490. break;
  491. } else {
  492. retry_count--;
  493. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  494. timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
  495. }
  496. } while (retry_count != 0);
  497. return;
  498. }
  499. static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
  500. {
  501. int retry_count = 15;
  502. struct MessageUnit_D *reg = pACB->pmuD;
  503. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
  504. do {
  505. if (arcmsr_hbaD_wait_msgint_ready(pACB))
  506. break;
  507. retry_count--;
  508. pr_notice("arcmsr%d: wait 'flush adapter "
  509. "cache' timeout, retry count down = %d\n",
  510. pACB->host->host_no, retry_count);
  511. } while (retry_count != 0);
  512. }
  513. static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB)
  514. {
  515. int retry_count = 30;
  516. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  517. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  518. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  519. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  520. do {
  521. if (arcmsr_hbaE_wait_msgint_ready(pACB))
  522. break;
  523. retry_count--;
  524. pr_notice("arcmsr%d: wait 'flush adapter "
  525. "cache' timeout, retry count down = %d\n",
  526. pACB->host->host_no, retry_count);
  527. } while (retry_count != 0);
  528. }
  529. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  530. {
  531. switch (acb->adapter_type) {
  532. case ACB_ADAPTER_TYPE_A:
  533. arcmsr_hbaA_flush_cache(acb);
  534. break;
  535. case ACB_ADAPTER_TYPE_B:
  536. arcmsr_hbaB_flush_cache(acb);
  537. break;
  538. case ACB_ADAPTER_TYPE_C:
  539. arcmsr_hbaC_flush_cache(acb);
  540. break;
  541. case ACB_ADAPTER_TYPE_D:
  542. arcmsr_hbaD_flush_cache(acb);
  543. break;
  544. case ACB_ADAPTER_TYPE_E:
  545. case ACB_ADAPTER_TYPE_F:
  546. arcmsr_hbaE_flush_cache(acb);
  547. break;
  548. }
  549. }
  550. static void arcmsr_hbaB_assign_regAddr(struct AdapterControlBlock *acb)
  551. {
  552. struct MessageUnit_B *reg = acb->pmuB;
  553. if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
  554. reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
  555. reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
  556. reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
  557. reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
  558. } else {
  559. reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
  560. reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
  561. reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
  562. reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
  563. }
  564. reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
  565. reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
  566. reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
  567. }
  568. static void arcmsr_hbaD_assign_regAddr(struct AdapterControlBlock *acb)
  569. {
  570. struct MessageUnit_D *reg = acb->pmuD;
  571. reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
  572. reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
  573. reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
  574. reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
  575. reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
  576. reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
  577. reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
  578. reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
  579. reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
  580. reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
  581. reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
  582. reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
  583. reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
  584. reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
  585. reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
  586. reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
  587. reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
  588. reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
  589. reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
  590. reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
  591. reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
  592. reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
  593. reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
  594. reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
  595. reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
  596. reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
  597. }
  598. static void arcmsr_hbaF_assign_regAddr(struct AdapterControlBlock *acb)
  599. {
  600. dma_addr_t host_buffer_dma;
  601. struct MessageUnit_F __iomem *pmuF;
  602. memset(acb->dma_coherent2, 0xff, acb->completeQ_size);
  603. acb->message_wbuffer = (uint32_t *)round_up((unsigned long)acb->dma_coherent2 +
  604. acb->completeQ_size, 4);
  605. acb->message_rbuffer = ((void *)acb->message_wbuffer) + 0x100;
  606. acb->msgcode_rwbuffer = ((void *)acb->message_wbuffer) + 0x200;
  607. memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
  608. host_buffer_dma = round_up(acb->dma_coherent_handle2 + acb->completeQ_size, 4);
  609. pmuF = acb->pmuF;
  610. /* host buffer low address, bit0:1 all buffer active */
  611. writel(lower_32_bits(host_buffer_dma | 1), &pmuF->inbound_msgaddr0);
  612. /* host buffer high address */
  613. writel(upper_32_bits(host_buffer_dma), &pmuF->inbound_msgaddr1);
  614. /* set host buffer physical address */
  615. writel(ARCMSR_HBFMU_DOORBELL_SYNC1, &pmuF->iobound_doorbell);
  616. }
  617. static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
  618. {
  619. bool rtn = true;
  620. void *dma_coherent;
  621. dma_addr_t dma_coherent_handle;
  622. struct pci_dev *pdev = acb->pdev;
  623. switch (acb->adapter_type) {
  624. case ACB_ADAPTER_TYPE_B: {
  625. acb->ioqueue_size = roundup(sizeof(struct MessageUnit_B), 32);
  626. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
  627. &dma_coherent_handle, GFP_KERNEL);
  628. if (!dma_coherent) {
  629. pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
  630. return false;
  631. }
  632. acb->dma_coherent_handle2 = dma_coherent_handle;
  633. acb->dma_coherent2 = dma_coherent;
  634. acb->pmuB = (struct MessageUnit_B *)dma_coherent;
  635. arcmsr_hbaB_assign_regAddr(acb);
  636. }
  637. break;
  638. case ACB_ADAPTER_TYPE_D: {
  639. acb->ioqueue_size = roundup(sizeof(struct MessageUnit_D), 32);
  640. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
  641. &dma_coherent_handle, GFP_KERNEL);
  642. if (!dma_coherent) {
  643. pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
  644. return false;
  645. }
  646. acb->dma_coherent_handle2 = dma_coherent_handle;
  647. acb->dma_coherent2 = dma_coherent;
  648. acb->pmuD = (struct MessageUnit_D *)dma_coherent;
  649. arcmsr_hbaD_assign_regAddr(acb);
  650. }
  651. break;
  652. case ACB_ADAPTER_TYPE_E: {
  653. uint32_t completeQ_size;
  654. completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128;
  655. acb->ioqueue_size = roundup(completeQ_size, 32);
  656. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
  657. &dma_coherent_handle, GFP_KERNEL);
  658. if (!dma_coherent){
  659. pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
  660. return false;
  661. }
  662. acb->dma_coherent_handle2 = dma_coherent_handle;
  663. acb->dma_coherent2 = dma_coherent;
  664. acb->pCompletionQ = dma_coherent;
  665. acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
  666. acb->doneq_index = 0;
  667. }
  668. break;
  669. case ACB_ADAPTER_TYPE_F: {
  670. uint32_t QueueDepth;
  671. uint32_t depthTbl[] = {256, 512, 1024, 128, 64, 32};
  672. arcmsr_wait_firmware_ready(acb);
  673. QueueDepth = depthTbl[readl(&acb->pmuF->outbound_msgaddr1) & 7];
  674. acb->completeQ_size = sizeof(struct deliver_completeQ) * QueueDepth + 128;
  675. acb->ioqueue_size = roundup(acb->completeQ_size + MESG_RW_BUFFER_SIZE, 32);
  676. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
  677. &dma_coherent_handle, GFP_KERNEL);
  678. if (!dma_coherent) {
  679. pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
  680. return false;
  681. }
  682. acb->dma_coherent_handle2 = dma_coherent_handle;
  683. acb->dma_coherent2 = dma_coherent;
  684. acb->pCompletionQ = dma_coherent;
  685. acb->completionQ_entry = acb->completeQ_size / sizeof(struct deliver_completeQ);
  686. acb->doneq_index = 0;
  687. arcmsr_hbaF_assign_regAddr(acb);
  688. }
  689. break;
  690. default:
  691. break;
  692. }
  693. return rtn;
  694. }
  695. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  696. {
  697. struct pci_dev *pdev = acb->pdev;
  698. void *dma_coherent;
  699. dma_addr_t dma_coherent_handle;
  700. struct CommandControlBlock *ccb_tmp;
  701. int i = 0, j = 0;
  702. unsigned long cdb_phyaddr, next_ccb_phy;
  703. unsigned long roundup_ccbsize;
  704. unsigned long max_xfer_len;
  705. unsigned long max_sg_entrys;
  706. uint32_t firm_config_version, curr_phy_upper32;
  707. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  708. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  709. acb->devstate[i][j] = ARECA_RAID_GONE;
  710. max_xfer_len = ARCMSR_MAX_XFER_LEN;
  711. max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
  712. firm_config_version = acb->firm_cfg_version;
  713. if((firm_config_version & 0xFF) >= 3){
  714. max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
  715. max_sg_entrys = (max_xfer_len/4096);
  716. }
  717. acb->host->max_sectors = max_xfer_len/512;
  718. acb->host->sg_tablesize = max_sg_entrys;
  719. roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
  720. acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB;
  721. if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
  722. acb->uncache_size += acb->ioqueue_size;
  723. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
  724. if(!dma_coherent){
  725. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
  726. return -ENOMEM;
  727. }
  728. acb->dma_coherent = dma_coherent;
  729. acb->dma_coherent_handle = dma_coherent_handle;
  730. memset(dma_coherent, 0, acb->uncache_size);
  731. acb->ccbsize = roundup_ccbsize;
  732. ccb_tmp = dma_coherent;
  733. curr_phy_upper32 = upper_32_bits(dma_coherent_handle);
  734. acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
  735. for(i = 0; i < acb->maxFreeCCB; i++){
  736. cdb_phyaddr = (unsigned long)dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
  737. switch (acb->adapter_type) {
  738. case ACB_ADAPTER_TYPE_A:
  739. case ACB_ADAPTER_TYPE_B:
  740. ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
  741. break;
  742. case ACB_ADAPTER_TYPE_C:
  743. case ACB_ADAPTER_TYPE_D:
  744. case ACB_ADAPTER_TYPE_E:
  745. case ACB_ADAPTER_TYPE_F:
  746. ccb_tmp->cdb_phyaddr = cdb_phyaddr;
  747. break;
  748. }
  749. acb->pccb_pool[i] = ccb_tmp;
  750. ccb_tmp->acb = acb;
  751. ccb_tmp->smid = (u32)i << 16;
  752. INIT_LIST_HEAD(&ccb_tmp->list);
  753. next_ccb_phy = dma_coherent_handle + roundup_ccbsize;
  754. if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) {
  755. acb->maxFreeCCB = i;
  756. acb->host->can_queue = i;
  757. break;
  758. }
  759. else
  760. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  761. ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
  762. dma_coherent_handle = next_ccb_phy;
  763. }
  764. if (acb->adapter_type != ACB_ADAPTER_TYPE_F) {
  765. acb->dma_coherent_handle2 = dma_coherent_handle;
  766. acb->dma_coherent2 = ccb_tmp;
  767. }
  768. switch (acb->adapter_type) {
  769. case ACB_ADAPTER_TYPE_B:
  770. acb->pmuB = (struct MessageUnit_B *)acb->dma_coherent2;
  771. arcmsr_hbaB_assign_regAddr(acb);
  772. break;
  773. case ACB_ADAPTER_TYPE_D:
  774. acb->pmuD = (struct MessageUnit_D *)acb->dma_coherent2;
  775. arcmsr_hbaD_assign_regAddr(acb);
  776. break;
  777. case ACB_ADAPTER_TYPE_E:
  778. acb->pCompletionQ = acb->dma_coherent2;
  779. acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
  780. acb->doneq_index = 0;
  781. break;
  782. }
  783. return 0;
  784. }
  785. static void arcmsr_message_isr_bh_fn(struct work_struct *work)
  786. {
  787. struct AdapterControlBlock *acb = container_of(work,
  788. struct AdapterControlBlock, arcmsr_do_message_isr_bh);
  789. char *acb_dev_map = (char *)acb->device_map;
  790. uint32_t __iomem *signature = NULL;
  791. char __iomem *devicemap = NULL;
  792. int target, lun;
  793. struct scsi_device *psdev;
  794. char diff, temp;
  795. switch (acb->adapter_type) {
  796. case ACB_ADAPTER_TYPE_A: {
  797. struct MessageUnit_A __iomem *reg = acb->pmuA;
  798. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  799. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  800. break;
  801. }
  802. case ACB_ADAPTER_TYPE_B: {
  803. struct MessageUnit_B *reg = acb->pmuB;
  804. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  805. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  806. break;
  807. }
  808. case ACB_ADAPTER_TYPE_C: {
  809. struct MessageUnit_C __iomem *reg = acb->pmuC;
  810. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  811. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  812. break;
  813. }
  814. case ACB_ADAPTER_TYPE_D: {
  815. struct MessageUnit_D *reg = acb->pmuD;
  816. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  817. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  818. break;
  819. }
  820. case ACB_ADAPTER_TYPE_E: {
  821. struct MessageUnit_E __iomem *reg = acb->pmuE;
  822. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  823. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  824. break;
  825. }
  826. case ACB_ADAPTER_TYPE_F: {
  827. signature = (uint32_t __iomem *)(&acb->msgcode_rwbuffer[0]);
  828. devicemap = (char __iomem *)(&acb->msgcode_rwbuffer[21]);
  829. break;
  830. }
  831. }
  832. if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
  833. return;
  834. for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
  835. target++) {
  836. temp = readb(devicemap);
  837. diff = (*acb_dev_map) ^ temp;
  838. if (diff != 0) {
  839. *acb_dev_map = temp;
  840. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
  841. lun++) {
  842. if ((diff & 0x01) == 1 &&
  843. (temp & 0x01) == 1) {
  844. scsi_add_device(acb->host,
  845. 0, target, lun);
  846. } else if ((diff & 0x01) == 1
  847. && (temp & 0x01) == 0) {
  848. psdev = scsi_device_lookup(acb->host,
  849. 0, target, lun);
  850. if (psdev != NULL) {
  851. scsi_remove_device(psdev);
  852. scsi_device_put(psdev);
  853. }
  854. }
  855. temp >>= 1;
  856. diff >>= 1;
  857. }
  858. }
  859. devicemap++;
  860. acb_dev_map++;
  861. }
  862. acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG;
  863. }
  864. static int
  865. arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
  866. {
  867. unsigned long flags;
  868. int nvec, i;
  869. if (msix_enable == 0)
  870. goto msi_int0;
  871. nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
  872. PCI_IRQ_MSIX);
  873. if (nvec > 0) {
  874. pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
  875. flags = 0;
  876. } else {
  877. msi_int0:
  878. if (msi_enable == 1) {
  879. nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
  880. if (nvec == 1) {
  881. dev_info(&pdev->dev, "msi enabled\n");
  882. goto msi_int1;
  883. }
  884. }
  885. nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
  886. if (nvec < 1)
  887. return FAILED;
  888. msi_int1:
  889. flags = IRQF_SHARED;
  890. }
  891. acb->vector_count = nvec;
  892. for (i = 0; i < nvec; i++) {
  893. if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
  894. flags, "arcmsr", acb)) {
  895. pr_warn("arcmsr%d: request_irq =%d failed!\n",
  896. acb->host->host_no, pci_irq_vector(pdev, i));
  897. goto out_free_irq;
  898. }
  899. }
  900. return SUCCESS;
  901. out_free_irq:
  902. while (--i >= 0)
  903. free_irq(pci_irq_vector(pdev, i), acb);
  904. pci_free_irq_vectors(pdev);
  905. return FAILED;
  906. }
  907. static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb)
  908. {
  909. INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  910. pacb->fw_flag = FW_NORMAL;
  911. timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0);
  912. pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  913. add_timer(&pacb->eternal_timer);
  914. }
  915. static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb)
  916. {
  917. timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0);
  918. pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000);
  919. add_timer(&pacb->refresh_timer);
  920. }
  921. static int arcmsr_set_dma_mask(struct AdapterControlBlock *acb)
  922. {
  923. struct pci_dev *pcidev = acb->pdev;
  924. if (IS_DMA64) {
  925. if (((acb->adapter_type == ACB_ADAPTER_TYPE_A) && !dma_mask_64) ||
  926. dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64)))
  927. goto dma32;
  928. if (dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)) ||
  929. dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64))) {
  930. printk("arcmsr: set DMA 64 mask failed\n");
  931. return -ENXIO;
  932. }
  933. } else {
  934. dma32:
  935. if (dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
  936. dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
  937. dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32))) {
  938. printk("arcmsr: set DMA 32-bit mask failed\n");
  939. return -ENXIO;
  940. }
  941. }
  942. return 0;
  943. }
  944. static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  945. {
  946. struct Scsi_Host *host;
  947. struct AdapterControlBlock *acb;
  948. uint8_t bus,dev_fun;
  949. int error;
  950. error = pci_enable_device(pdev);
  951. if(error){
  952. return -ENODEV;
  953. }
  954. host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
  955. if(!host){
  956. goto pci_disable_dev;
  957. }
  958. init_waitqueue_head(&wait_q);
  959. bus = pdev->bus->number;
  960. dev_fun = pdev->devfn;
  961. acb = (struct AdapterControlBlock *) host->hostdata;
  962. memset(acb,0,sizeof(struct AdapterControlBlock));
  963. acb->pdev = pdev;
  964. acb->adapter_type = id->driver_data;
  965. if (arcmsr_set_dma_mask(acb))
  966. goto scsi_host_release;
  967. acb->host = host;
  968. host->max_lun = ARCMSR_MAX_TARGETLUN;
  969. host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
  970. host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
  971. if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD))
  972. host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
  973. host->can_queue = host_can_queue; /* max simultaneous cmds */
  974. if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN))
  975. cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
  976. host->cmd_per_lun = cmd_per_lun;
  977. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  978. host->unique_id = (bus << 8) | dev_fun;
  979. pci_set_drvdata(pdev, host);
  980. pci_set_master(pdev);
  981. error = pci_request_regions(pdev, "arcmsr");
  982. if(error){
  983. goto scsi_host_release;
  984. }
  985. spin_lock_init(&acb->eh_lock);
  986. spin_lock_init(&acb->ccblist_lock);
  987. spin_lock_init(&acb->postq_lock);
  988. spin_lock_init(&acb->doneq_lock);
  989. spin_lock_init(&acb->rqbuffer_lock);
  990. spin_lock_init(&acb->wqbuffer_lock);
  991. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  992. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  993. ACB_F_MESSAGE_WQBUFFER_READED);
  994. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  995. INIT_LIST_HEAD(&acb->ccb_free_list);
  996. error = arcmsr_remap_pciregion(acb);
  997. if(!error){
  998. goto pci_release_regs;
  999. }
  1000. error = arcmsr_alloc_io_queue(acb);
  1001. if (!error)
  1002. goto unmap_pci_region;
  1003. error = arcmsr_get_firmware_spec(acb);
  1004. if(!error){
  1005. goto free_hbb_mu;
  1006. }
  1007. if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
  1008. arcmsr_free_io_queue(acb);
  1009. error = arcmsr_alloc_ccb_pool(acb);
  1010. if(error){
  1011. goto unmap_pci_region;
  1012. }
  1013. error = scsi_add_host(host, &pdev->dev);
  1014. if(error){
  1015. goto free_ccb_pool;
  1016. }
  1017. if (arcmsr_request_irq(pdev, acb) == FAILED)
  1018. goto scsi_host_remove;
  1019. arcmsr_iop_init(acb);
  1020. arcmsr_init_get_devmap_timer(acb);
  1021. if (set_date_time)
  1022. arcmsr_init_set_datetime_timer(acb);
  1023. if(arcmsr_alloc_sysfs_attr(acb))
  1024. goto out_free_sysfs;
  1025. scsi_scan_host(host);
  1026. return 0;
  1027. out_free_sysfs:
  1028. if (set_date_time)
  1029. del_timer_sync(&acb->refresh_timer);
  1030. del_timer_sync(&acb->eternal_timer);
  1031. flush_work(&acb->arcmsr_do_message_isr_bh);
  1032. arcmsr_stop_adapter_bgrb(acb);
  1033. arcmsr_flush_adapter_cache(acb);
  1034. arcmsr_free_irq(pdev, acb);
  1035. scsi_host_remove:
  1036. scsi_remove_host(host);
  1037. free_ccb_pool:
  1038. arcmsr_free_ccb_pool(acb);
  1039. goto unmap_pci_region;
  1040. free_hbb_mu:
  1041. arcmsr_free_io_queue(acb);
  1042. unmap_pci_region:
  1043. arcmsr_unmap_pciregion(acb);
  1044. pci_release_regs:
  1045. pci_release_regions(pdev);
  1046. scsi_host_release:
  1047. scsi_host_put(host);
  1048. pci_disable_dev:
  1049. pci_disable_device(pdev);
  1050. return -ENODEV;
  1051. }
  1052. static void arcmsr_free_irq(struct pci_dev *pdev,
  1053. struct AdapterControlBlock *acb)
  1054. {
  1055. int i;
  1056. for (i = 0; i < acb->vector_count; i++)
  1057. free_irq(pci_irq_vector(pdev, i), acb);
  1058. pci_free_irq_vectors(pdev);
  1059. }
  1060. static int __maybe_unused arcmsr_suspend(struct device *dev)
  1061. {
  1062. struct pci_dev *pdev = to_pci_dev(dev);
  1063. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1064. struct AdapterControlBlock *acb =
  1065. (struct AdapterControlBlock *)host->hostdata;
  1066. arcmsr_disable_outbound_ints(acb);
  1067. arcmsr_free_irq(pdev, acb);
  1068. del_timer_sync(&acb->eternal_timer);
  1069. if (set_date_time)
  1070. del_timer_sync(&acb->refresh_timer);
  1071. flush_work(&acb->arcmsr_do_message_isr_bh);
  1072. arcmsr_stop_adapter_bgrb(acb);
  1073. arcmsr_flush_adapter_cache(acb);
  1074. return 0;
  1075. }
  1076. static int __maybe_unused arcmsr_resume(struct device *dev)
  1077. {
  1078. struct pci_dev *pdev = to_pci_dev(dev);
  1079. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1080. struct AdapterControlBlock *acb =
  1081. (struct AdapterControlBlock *)host->hostdata;
  1082. if (arcmsr_set_dma_mask(acb))
  1083. goto controller_unregister;
  1084. if (arcmsr_request_irq(pdev, acb) == FAILED)
  1085. goto controller_stop;
  1086. switch (acb->adapter_type) {
  1087. case ACB_ADAPTER_TYPE_B: {
  1088. struct MessageUnit_B *reg = acb->pmuB;
  1089. uint32_t i;
  1090. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  1091. reg->post_qbuffer[i] = 0;
  1092. reg->done_qbuffer[i] = 0;
  1093. }
  1094. reg->postq_index = 0;
  1095. reg->doneq_index = 0;
  1096. break;
  1097. }
  1098. case ACB_ADAPTER_TYPE_E:
  1099. writel(0, &acb->pmuE->host_int_status);
  1100. writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
  1101. acb->in_doorbell = 0;
  1102. acb->out_doorbell = 0;
  1103. acb->doneq_index = 0;
  1104. break;
  1105. case ACB_ADAPTER_TYPE_F:
  1106. writel(0, &acb->pmuF->host_int_status);
  1107. writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
  1108. acb->in_doorbell = 0;
  1109. acb->out_doorbell = 0;
  1110. acb->doneq_index = 0;
  1111. arcmsr_hbaF_assign_regAddr(acb);
  1112. break;
  1113. }
  1114. arcmsr_iop_init(acb);
  1115. arcmsr_init_get_devmap_timer(acb);
  1116. if (set_date_time)
  1117. arcmsr_init_set_datetime_timer(acb);
  1118. return 0;
  1119. controller_stop:
  1120. arcmsr_stop_adapter_bgrb(acb);
  1121. arcmsr_flush_adapter_cache(acb);
  1122. controller_unregister:
  1123. scsi_remove_host(host);
  1124. arcmsr_free_ccb_pool(acb);
  1125. if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
  1126. arcmsr_free_io_queue(acb);
  1127. arcmsr_unmap_pciregion(acb);
  1128. scsi_host_put(host);
  1129. return -ENODEV;
  1130. }
  1131. static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
  1132. {
  1133. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1134. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  1135. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  1136. printk(KERN_NOTICE
  1137. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  1138. , acb->host->host_no);
  1139. return false;
  1140. }
  1141. return true;
  1142. }
  1143. static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
  1144. {
  1145. struct MessageUnit_B *reg = acb->pmuB;
  1146. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
  1147. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  1148. printk(KERN_NOTICE
  1149. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  1150. , acb->host->host_no);
  1151. return false;
  1152. }
  1153. return true;
  1154. }
  1155. static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
  1156. {
  1157. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1158. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  1159. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1160. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  1161. printk(KERN_NOTICE
  1162. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  1163. , pACB->host->host_no);
  1164. return false;
  1165. }
  1166. return true;
  1167. }
  1168. static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
  1169. {
  1170. struct MessageUnit_D *reg = pACB->pmuD;
  1171. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
  1172. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  1173. pr_notice("arcmsr%d: wait 'abort all outstanding "
  1174. "command' timeout\n", pACB->host->host_no);
  1175. return false;
  1176. }
  1177. return true;
  1178. }
  1179. static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)
  1180. {
  1181. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  1182. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  1183. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  1184. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  1185. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  1186. pr_notice("arcmsr%d: wait 'abort all outstanding "
  1187. "command' timeout\n", pACB->host->host_no);
  1188. return false;
  1189. }
  1190. return true;
  1191. }
  1192. static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  1193. {
  1194. uint8_t rtnval = 0;
  1195. switch (acb->adapter_type) {
  1196. case ACB_ADAPTER_TYPE_A:
  1197. rtnval = arcmsr_hbaA_abort_allcmd(acb);
  1198. break;
  1199. case ACB_ADAPTER_TYPE_B:
  1200. rtnval = arcmsr_hbaB_abort_allcmd(acb);
  1201. break;
  1202. case ACB_ADAPTER_TYPE_C:
  1203. rtnval = arcmsr_hbaC_abort_allcmd(acb);
  1204. break;
  1205. case ACB_ADAPTER_TYPE_D:
  1206. rtnval = arcmsr_hbaD_abort_allcmd(acb);
  1207. break;
  1208. case ACB_ADAPTER_TYPE_E:
  1209. case ACB_ADAPTER_TYPE_F:
  1210. rtnval = arcmsr_hbaE_abort_allcmd(acb);
  1211. break;
  1212. }
  1213. return rtnval;
  1214. }
  1215. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  1216. {
  1217. struct scsi_cmnd *pcmd = ccb->pcmd;
  1218. scsi_dma_unmap(pcmd);
  1219. }
  1220. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
  1221. {
  1222. struct AdapterControlBlock *acb = ccb->acb;
  1223. struct scsi_cmnd *pcmd = ccb->pcmd;
  1224. unsigned long flags;
  1225. atomic_dec(&acb->ccboutstandingcount);
  1226. arcmsr_pci_unmap_dma(ccb);
  1227. ccb->startdone = ARCMSR_CCB_DONE;
  1228. spin_lock_irqsave(&acb->ccblist_lock, flags);
  1229. list_add_tail(&ccb->list, &acb->ccb_free_list);
  1230. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  1231. scsi_done(pcmd);
  1232. }
  1233. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  1234. {
  1235. struct scsi_cmnd *pcmd = ccb->pcmd;
  1236. pcmd->result = (DID_OK << 16) | SAM_STAT_CHECK_CONDITION;
  1237. if (pcmd->sense_buffer) {
  1238. struct SENSE_DATA *sensebuffer;
  1239. memcpy_and_pad(pcmd->sense_buffer,
  1240. SCSI_SENSE_BUFFERSIZE,
  1241. ccb->arcmsr_cdb.SenseData,
  1242. sizeof(ccb->arcmsr_cdb.SenseData),
  1243. 0);
  1244. sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  1245. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  1246. sensebuffer->Valid = 1;
  1247. }
  1248. }
  1249. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  1250. {
  1251. u32 orig_mask = 0;
  1252. switch (acb->adapter_type) {
  1253. case ACB_ADAPTER_TYPE_A : {
  1254. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1255. orig_mask = readl(&reg->outbound_intmask);
  1256. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  1257. &reg->outbound_intmask);
  1258. }
  1259. break;
  1260. case ACB_ADAPTER_TYPE_B : {
  1261. struct MessageUnit_B *reg = acb->pmuB;
  1262. orig_mask = readl(reg->iop2drv_doorbell_mask);
  1263. writel(0, reg->iop2drv_doorbell_mask);
  1264. }
  1265. break;
  1266. case ACB_ADAPTER_TYPE_C:{
  1267. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1268. /* disable all outbound interrupt */
  1269. orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
  1270. writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  1271. }
  1272. break;
  1273. case ACB_ADAPTER_TYPE_D: {
  1274. struct MessageUnit_D *reg = acb->pmuD;
  1275. /* disable all outbound interrupt */
  1276. writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
  1277. }
  1278. break;
  1279. case ACB_ADAPTER_TYPE_E:
  1280. case ACB_ADAPTER_TYPE_F: {
  1281. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1282. orig_mask = readl(&reg->host_int_mask);
  1283. writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, &reg->host_int_mask);
  1284. readl(&reg->host_int_mask); /* Dummy readl to force pci flush */
  1285. }
  1286. break;
  1287. }
  1288. return orig_mask;
  1289. }
  1290. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
  1291. struct CommandControlBlock *ccb, bool error)
  1292. {
  1293. uint8_t id, lun;
  1294. id = ccb->pcmd->device->id;
  1295. lun = ccb->pcmd->device->lun;
  1296. if (!error) {
  1297. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  1298. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  1299. ccb->pcmd->result = DID_OK << 16;
  1300. arcmsr_ccb_complete(ccb);
  1301. }else{
  1302. switch (ccb->arcmsr_cdb.DeviceStatus) {
  1303. case ARCMSR_DEV_SELECT_TIMEOUT: {
  1304. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1305. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1306. arcmsr_ccb_complete(ccb);
  1307. }
  1308. break;
  1309. case ARCMSR_DEV_ABORTED:
  1310. case ARCMSR_DEV_INIT_FAIL: {
  1311. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1312. ccb->pcmd->result = DID_BAD_TARGET << 16;
  1313. arcmsr_ccb_complete(ccb);
  1314. }
  1315. break;
  1316. case ARCMSR_DEV_CHECK_CONDITION: {
  1317. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  1318. arcmsr_report_sense_info(ccb);
  1319. arcmsr_ccb_complete(ccb);
  1320. }
  1321. break;
  1322. default:
  1323. printk(KERN_NOTICE
  1324. "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
  1325. but got unknown DeviceStatus = 0x%x \n"
  1326. , acb->host->host_no
  1327. , id
  1328. , lun
  1329. , ccb->arcmsr_cdb.DeviceStatus);
  1330. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1331. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1332. arcmsr_ccb_complete(ccb);
  1333. break;
  1334. }
  1335. }
  1336. }
  1337. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
  1338. {
  1339. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  1340. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  1341. struct scsi_cmnd *abortcmd = pCCB->pcmd;
  1342. if (abortcmd) {
  1343. abortcmd->result |= DID_ABORT << 16;
  1344. arcmsr_ccb_complete(pCCB);
  1345. printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
  1346. acb->host->host_no, pCCB);
  1347. }
  1348. return;
  1349. }
  1350. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  1351. done acb = '0x%p'"
  1352. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  1353. " ccboutstandingcount = %d \n"
  1354. , acb->host->host_no
  1355. , acb
  1356. , pCCB
  1357. , pCCB->acb
  1358. , pCCB->startdone
  1359. , atomic_read(&acb->ccboutstandingcount));
  1360. return;
  1361. }
  1362. arcmsr_report_ccb_state(acb, pCCB, error);
  1363. }
  1364. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  1365. {
  1366. int i = 0;
  1367. uint32_t flag_ccb;
  1368. struct ARCMSR_CDB *pARCMSR_CDB;
  1369. bool error;
  1370. struct CommandControlBlock *pCCB;
  1371. unsigned long ccb_cdb_phy;
  1372. switch (acb->adapter_type) {
  1373. case ACB_ADAPTER_TYPE_A: {
  1374. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1375. uint32_t outbound_intstatus;
  1376. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1377. acb->outbound_int_enable;
  1378. /*clear and abort all outbound posted Q*/
  1379. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1380. while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  1381. && (i++ < acb->maxOutstanding)) {
  1382. ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
  1383. if (acb->cdb_phyadd_hipart)
  1384. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  1385. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  1386. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1387. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1388. arcmsr_drain_donequeue(acb, pCCB, error);
  1389. }
  1390. }
  1391. break;
  1392. case ACB_ADAPTER_TYPE_B: {
  1393. struct MessageUnit_B *reg = acb->pmuB;
  1394. /*clear all outbound posted Q*/
  1395. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
  1396. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  1397. flag_ccb = reg->done_qbuffer[i];
  1398. if (flag_ccb != 0) {
  1399. reg->done_qbuffer[i] = 0;
  1400. ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
  1401. if (acb->cdb_phyadd_hipart)
  1402. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  1403. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  1404. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1405. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1406. arcmsr_drain_donequeue(acb, pCCB, error);
  1407. }
  1408. reg->post_qbuffer[i] = 0;
  1409. }
  1410. reg->doneq_index = 0;
  1411. reg->postq_index = 0;
  1412. }
  1413. break;
  1414. case ACB_ADAPTER_TYPE_C: {
  1415. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1416. while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) {
  1417. /*need to do*/
  1418. flag_ccb = readl(&reg->outbound_queueport_low);
  1419. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  1420. if (acb->cdb_phyadd_hipart)
  1421. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  1422. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  1423. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1424. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  1425. arcmsr_drain_donequeue(acb, pCCB, error);
  1426. }
  1427. }
  1428. break;
  1429. case ACB_ADAPTER_TYPE_D: {
  1430. struct MessageUnit_D *pmu = acb->pmuD;
  1431. uint32_t outbound_write_pointer;
  1432. uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
  1433. unsigned long flags;
  1434. residual = atomic_read(&acb->ccboutstandingcount);
  1435. for (i = 0; i < residual; i++) {
  1436. spin_lock_irqsave(&acb->doneq_lock, flags);
  1437. outbound_write_pointer =
  1438. pmu->done_qbuffer[0].addressLow + 1;
  1439. doneq_index = pmu->doneq_index;
  1440. if ((doneq_index & 0xFFF) !=
  1441. (outbound_write_pointer & 0xFFF)) {
  1442. toggle = doneq_index & 0x4000;
  1443. index_stripped = (doneq_index & 0xFFF) + 1;
  1444. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  1445. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  1446. ((toggle ^ 0x4000) + 1);
  1447. doneq_index = pmu->doneq_index;
  1448. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1449. addressLow = pmu->done_qbuffer[doneq_index &
  1450. 0xFFF].addressLow;
  1451. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  1452. if (acb->cdb_phyadd_hipart)
  1453. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  1454. pARCMSR_CDB = (struct ARCMSR_CDB *)
  1455. (acb->vir2phy_offset + ccb_cdb_phy);
  1456. pCCB = container_of(pARCMSR_CDB,
  1457. struct CommandControlBlock, arcmsr_cdb);
  1458. error = (addressLow &
  1459. ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
  1460. true : false;
  1461. arcmsr_drain_donequeue(acb, pCCB, error);
  1462. writel(doneq_index,
  1463. pmu->outboundlist_read_pointer);
  1464. } else {
  1465. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1466. mdelay(10);
  1467. }
  1468. }
  1469. pmu->postq_index = 0;
  1470. pmu->doneq_index = 0x40FF;
  1471. }
  1472. break;
  1473. case ACB_ADAPTER_TYPE_E:
  1474. arcmsr_hbaE_postqueue_isr(acb);
  1475. break;
  1476. case ACB_ADAPTER_TYPE_F:
  1477. arcmsr_hbaF_postqueue_isr(acb);
  1478. break;
  1479. }
  1480. }
  1481. static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb)
  1482. {
  1483. char *acb_dev_map = (char *)acb->device_map;
  1484. int target, lun, i;
  1485. struct scsi_device *psdev;
  1486. struct CommandControlBlock *ccb;
  1487. char temp;
  1488. for (i = 0; i < acb->maxFreeCCB; i++) {
  1489. ccb = acb->pccb_pool[i];
  1490. if (ccb->startdone == ARCMSR_CCB_START) {
  1491. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1492. arcmsr_pci_unmap_dma(ccb);
  1493. scsi_done(ccb->pcmd);
  1494. }
  1495. }
  1496. for (target = 0; target < ARCMSR_MAX_TARGETID; target++) {
  1497. temp = *acb_dev_map;
  1498. if (temp) {
  1499. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  1500. if (temp & 1) {
  1501. psdev = scsi_device_lookup(acb->host,
  1502. 0, target, lun);
  1503. if (psdev != NULL) {
  1504. scsi_remove_device(psdev);
  1505. scsi_device_put(psdev);
  1506. }
  1507. }
  1508. temp >>= 1;
  1509. }
  1510. *acb_dev_map = 0;
  1511. }
  1512. acb_dev_map++;
  1513. }
  1514. }
  1515. static void arcmsr_free_pcidev(struct AdapterControlBlock *acb)
  1516. {
  1517. struct pci_dev *pdev;
  1518. struct Scsi_Host *host;
  1519. host = acb->host;
  1520. arcmsr_free_sysfs_attr(acb);
  1521. scsi_remove_host(host);
  1522. flush_work(&acb->arcmsr_do_message_isr_bh);
  1523. del_timer_sync(&acb->eternal_timer);
  1524. if (set_date_time)
  1525. del_timer_sync(&acb->refresh_timer);
  1526. pdev = acb->pdev;
  1527. arcmsr_free_irq(pdev, acb);
  1528. arcmsr_free_ccb_pool(acb);
  1529. if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
  1530. arcmsr_free_io_queue(acb);
  1531. arcmsr_unmap_pciregion(acb);
  1532. pci_release_regions(pdev);
  1533. scsi_host_put(host);
  1534. pci_disable_device(pdev);
  1535. }
  1536. static void arcmsr_remove(struct pci_dev *pdev)
  1537. {
  1538. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1539. struct AdapterControlBlock *acb =
  1540. (struct AdapterControlBlock *) host->hostdata;
  1541. int poll_count = 0;
  1542. uint16_t dev_id;
  1543. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  1544. if (dev_id == 0xffff) {
  1545. acb->acb_flags &= ~ACB_F_IOP_INITED;
  1546. acb->acb_flags |= ACB_F_ADAPTER_REMOVED;
  1547. arcmsr_remove_scsi_devices(acb);
  1548. arcmsr_free_pcidev(acb);
  1549. return;
  1550. }
  1551. arcmsr_free_sysfs_attr(acb);
  1552. scsi_remove_host(host);
  1553. flush_work(&acb->arcmsr_do_message_isr_bh);
  1554. del_timer_sync(&acb->eternal_timer);
  1555. if (set_date_time)
  1556. del_timer_sync(&acb->refresh_timer);
  1557. arcmsr_disable_outbound_ints(acb);
  1558. arcmsr_stop_adapter_bgrb(acb);
  1559. arcmsr_flush_adapter_cache(acb);
  1560. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  1561. acb->acb_flags &= ~ACB_F_IOP_INITED;
  1562. for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){
  1563. if (!atomic_read(&acb->ccboutstandingcount))
  1564. break;
  1565. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1566. msleep(25);
  1567. }
  1568. if (atomic_read(&acb->ccboutstandingcount)) {
  1569. int i;
  1570. arcmsr_abort_allcmd(acb);
  1571. arcmsr_done4abort_postqueue(acb);
  1572. for (i = 0; i < acb->maxFreeCCB; i++) {
  1573. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1574. if (ccb->startdone == ARCMSR_CCB_START) {
  1575. ccb->startdone = ARCMSR_CCB_ABORTED;
  1576. ccb->pcmd->result = DID_ABORT << 16;
  1577. arcmsr_ccb_complete(ccb);
  1578. }
  1579. }
  1580. }
  1581. arcmsr_free_irq(pdev, acb);
  1582. arcmsr_free_ccb_pool(acb);
  1583. if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
  1584. arcmsr_free_io_queue(acb);
  1585. arcmsr_unmap_pciregion(acb);
  1586. pci_release_regions(pdev);
  1587. scsi_host_put(host);
  1588. pci_disable_device(pdev);
  1589. }
  1590. static void arcmsr_shutdown(struct pci_dev *pdev)
  1591. {
  1592. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1593. struct AdapterControlBlock *acb =
  1594. (struct AdapterControlBlock *)host->hostdata;
  1595. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
  1596. return;
  1597. del_timer_sync(&acb->eternal_timer);
  1598. if (set_date_time)
  1599. del_timer_sync(&acb->refresh_timer);
  1600. arcmsr_disable_outbound_ints(acb);
  1601. arcmsr_free_irq(pdev, acb);
  1602. flush_work(&acb->arcmsr_do_message_isr_bh);
  1603. arcmsr_stop_adapter_bgrb(acb);
  1604. arcmsr_flush_adapter_cache(acb);
  1605. }
  1606. static int arcmsr_module_init(void)
  1607. {
  1608. int error = 0;
  1609. error = pci_register_driver(&arcmsr_pci_driver);
  1610. return error;
  1611. }
  1612. static void arcmsr_module_exit(void)
  1613. {
  1614. pci_unregister_driver(&arcmsr_pci_driver);
  1615. }
  1616. module_init(arcmsr_module_init);
  1617. module_exit(arcmsr_module_exit);
  1618. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  1619. u32 intmask_org)
  1620. {
  1621. u32 mask;
  1622. switch (acb->adapter_type) {
  1623. case ACB_ADAPTER_TYPE_A: {
  1624. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1625. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  1626. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
  1627. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
  1628. writel(mask, &reg->outbound_intmask);
  1629. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  1630. }
  1631. break;
  1632. case ACB_ADAPTER_TYPE_B: {
  1633. struct MessageUnit_B *reg = acb->pmuB;
  1634. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
  1635. ARCMSR_IOP2DRV_DATA_READ_OK |
  1636. ARCMSR_IOP2DRV_CDB_DONE |
  1637. ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  1638. writel(mask, reg->iop2drv_doorbell_mask);
  1639. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  1640. }
  1641. break;
  1642. case ACB_ADAPTER_TYPE_C: {
  1643. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1644. mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
  1645. writel(intmask_org & mask, &reg->host_int_mask);
  1646. acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
  1647. }
  1648. break;
  1649. case ACB_ADAPTER_TYPE_D: {
  1650. struct MessageUnit_D *reg = acb->pmuD;
  1651. mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
  1652. writel(intmask_org | mask, reg->pcief0_int_enable);
  1653. break;
  1654. }
  1655. case ACB_ADAPTER_TYPE_E:
  1656. case ACB_ADAPTER_TYPE_F: {
  1657. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1658. mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
  1659. writel(intmask_org & mask, &reg->host_int_mask);
  1660. break;
  1661. }
  1662. }
  1663. }
  1664. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  1665. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  1666. {
  1667. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1668. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  1669. __le32 address_lo, address_hi;
  1670. int arccdbsize = 0x30;
  1671. __le32 length = 0;
  1672. int i;
  1673. struct scatterlist *sg;
  1674. int nseg;
  1675. ccb->pcmd = pcmd;
  1676. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  1677. arcmsr_cdb->TargetID = pcmd->device->id;
  1678. arcmsr_cdb->LUN = pcmd->device->lun;
  1679. arcmsr_cdb->Function = 1;
  1680. arcmsr_cdb->msgContext = 0;
  1681. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  1682. nseg = scsi_dma_map(pcmd);
  1683. if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
  1684. return FAILED;
  1685. scsi_for_each_sg(pcmd, sg, nseg, i) {
  1686. /* Get the physical address of the current data pointer */
  1687. length = cpu_to_le32(sg_dma_len(sg));
  1688. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  1689. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  1690. if (address_hi == 0) {
  1691. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  1692. pdma_sg->address = address_lo;
  1693. pdma_sg->length = length;
  1694. psge += sizeof (struct SG32ENTRY);
  1695. arccdbsize += sizeof (struct SG32ENTRY);
  1696. } else {
  1697. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  1698. pdma_sg->addresshigh = address_hi;
  1699. pdma_sg->address = address_lo;
  1700. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  1701. psge += sizeof (struct SG64ENTRY);
  1702. arccdbsize += sizeof (struct SG64ENTRY);
  1703. }
  1704. }
  1705. arcmsr_cdb->sgcount = (uint8_t)nseg;
  1706. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  1707. arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
  1708. if ( arccdbsize > 256)
  1709. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  1710. if (pcmd->sc_data_direction == DMA_TO_DEVICE)
  1711. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  1712. ccb->arc_cdb_size = arccdbsize;
  1713. return SUCCESS;
  1714. }
  1715. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  1716. {
  1717. uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
  1718. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1719. atomic_inc(&acb->ccboutstandingcount);
  1720. ccb->startdone = ARCMSR_CCB_START;
  1721. switch (acb->adapter_type) {
  1722. case ACB_ADAPTER_TYPE_A: {
  1723. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1724. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  1725. writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  1726. &reg->inbound_queueport);
  1727. else
  1728. writel(cdb_phyaddr, &reg->inbound_queueport);
  1729. break;
  1730. }
  1731. case ACB_ADAPTER_TYPE_B: {
  1732. struct MessageUnit_B *reg = acb->pmuB;
  1733. uint32_t ending_index, index = reg->postq_index;
  1734. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  1735. reg->post_qbuffer[ending_index] = 0;
  1736. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  1737. reg->post_qbuffer[index] =
  1738. cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
  1739. } else {
  1740. reg->post_qbuffer[index] = cdb_phyaddr;
  1741. }
  1742. index++;
  1743. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  1744. reg->postq_index = index;
  1745. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
  1746. }
  1747. break;
  1748. case ACB_ADAPTER_TYPE_C: {
  1749. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1750. uint32_t ccb_post_stamp, arc_cdb_size;
  1751. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1752. ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
  1753. writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high);
  1754. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1755. }
  1756. break;
  1757. case ACB_ADAPTER_TYPE_D: {
  1758. struct MessageUnit_D *pmu = acb->pmuD;
  1759. u16 index_stripped;
  1760. u16 postq_index, toggle;
  1761. unsigned long flags;
  1762. struct InBound_SRB *pinbound_srb;
  1763. spin_lock_irqsave(&acb->postq_lock, flags);
  1764. postq_index = pmu->postq_index;
  1765. pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
  1766. pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr);
  1767. pinbound_srb->addressLow = cdb_phyaddr;
  1768. pinbound_srb->length = ccb->arc_cdb_size >> 2;
  1769. arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
  1770. toggle = postq_index & 0x4000;
  1771. index_stripped = postq_index + 1;
  1772. index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
  1773. pmu->postq_index = index_stripped ? (index_stripped | toggle) :
  1774. (toggle ^ 0x4000);
  1775. writel(postq_index, pmu->inboundlist_write_pointer);
  1776. spin_unlock_irqrestore(&acb->postq_lock, flags);
  1777. break;
  1778. }
  1779. case ACB_ADAPTER_TYPE_E: {
  1780. struct MessageUnit_E __iomem *pmu = acb->pmuE;
  1781. u32 ccb_post_stamp, arc_cdb_size;
  1782. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1783. ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6));
  1784. writel(0, &pmu->inbound_queueport_high);
  1785. writel(ccb_post_stamp, &pmu->inbound_queueport_low);
  1786. break;
  1787. }
  1788. case ACB_ADAPTER_TYPE_F: {
  1789. struct MessageUnit_F __iomem *pmu = acb->pmuF;
  1790. u32 ccb_post_stamp, arc_cdb_size;
  1791. if (ccb->arc_cdb_size <= 0x300)
  1792. arc_cdb_size = (ccb->arc_cdb_size - 1) >> 6 | 1;
  1793. else {
  1794. arc_cdb_size = ((ccb->arc_cdb_size + 0xff) >> 8) + 2;
  1795. if (arc_cdb_size > 0xF)
  1796. arc_cdb_size = 0xF;
  1797. arc_cdb_size = (arc_cdb_size << 1) | 1;
  1798. }
  1799. ccb_post_stamp = (ccb->smid | arc_cdb_size);
  1800. writel(0, &pmu->inbound_queueport_high);
  1801. writel(ccb_post_stamp, &pmu->inbound_queueport_low);
  1802. break;
  1803. }
  1804. }
  1805. }
  1806. static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
  1807. {
  1808. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1809. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1810. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1811. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  1812. printk(KERN_NOTICE
  1813. "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
  1814. , acb->host->host_no);
  1815. }
  1816. }
  1817. static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
  1818. {
  1819. struct MessageUnit_B *reg = acb->pmuB;
  1820. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1821. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
  1822. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  1823. printk(KERN_NOTICE
  1824. "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
  1825. , acb->host->host_no);
  1826. }
  1827. }
  1828. static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
  1829. {
  1830. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1831. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1832. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1833. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1834. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  1835. printk(KERN_NOTICE
  1836. "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
  1837. , pACB->host->host_no);
  1838. }
  1839. return;
  1840. }
  1841. static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
  1842. {
  1843. struct MessageUnit_D *reg = pACB->pmuD;
  1844. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1845. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
  1846. if (!arcmsr_hbaD_wait_msgint_ready(pACB))
  1847. pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
  1848. "timeout\n", pACB->host->host_no);
  1849. }
  1850. static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB)
  1851. {
  1852. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  1853. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1854. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1855. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  1856. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  1857. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  1858. pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
  1859. "timeout\n", pACB->host->host_no);
  1860. }
  1861. }
  1862. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  1863. {
  1864. switch (acb->adapter_type) {
  1865. case ACB_ADAPTER_TYPE_A:
  1866. arcmsr_hbaA_stop_bgrb(acb);
  1867. break;
  1868. case ACB_ADAPTER_TYPE_B:
  1869. arcmsr_hbaB_stop_bgrb(acb);
  1870. break;
  1871. case ACB_ADAPTER_TYPE_C:
  1872. arcmsr_hbaC_stop_bgrb(acb);
  1873. break;
  1874. case ACB_ADAPTER_TYPE_D:
  1875. arcmsr_hbaD_stop_bgrb(acb);
  1876. break;
  1877. case ACB_ADAPTER_TYPE_E:
  1878. case ACB_ADAPTER_TYPE_F:
  1879. arcmsr_hbaE_stop_bgrb(acb);
  1880. break;
  1881. }
  1882. }
  1883. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  1884. {
  1885. dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
  1886. }
  1887. static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  1888. {
  1889. switch (acb->adapter_type) {
  1890. case ACB_ADAPTER_TYPE_A: {
  1891. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1892. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1893. }
  1894. break;
  1895. case ACB_ADAPTER_TYPE_B: {
  1896. struct MessageUnit_B *reg = acb->pmuB;
  1897. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  1898. }
  1899. break;
  1900. case ACB_ADAPTER_TYPE_C: {
  1901. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1902. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  1903. }
  1904. break;
  1905. case ACB_ADAPTER_TYPE_D: {
  1906. struct MessageUnit_D *reg = acb->pmuD;
  1907. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  1908. reg->inbound_doorbell);
  1909. }
  1910. break;
  1911. case ACB_ADAPTER_TYPE_E:
  1912. case ACB_ADAPTER_TYPE_F: {
  1913. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1914. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
  1915. writel(acb->out_doorbell, &reg->iobound_doorbell);
  1916. }
  1917. break;
  1918. }
  1919. }
  1920. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  1921. {
  1922. switch (acb->adapter_type) {
  1923. case ACB_ADAPTER_TYPE_A: {
  1924. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1925. /*
  1926. ** push inbound doorbell tell iop, driver data write ok
  1927. ** and wait reply on next hwinterrupt for next Qbuffer post
  1928. */
  1929. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  1930. }
  1931. break;
  1932. case ACB_ADAPTER_TYPE_B: {
  1933. struct MessageUnit_B *reg = acb->pmuB;
  1934. /*
  1935. ** push inbound doorbell tell iop, driver data write ok
  1936. ** and wait reply on next hwinterrupt for next Qbuffer post
  1937. */
  1938. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
  1939. }
  1940. break;
  1941. case ACB_ADAPTER_TYPE_C: {
  1942. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1943. /*
  1944. ** push inbound doorbell tell iop, driver data write ok
  1945. ** and wait reply on next hwinterrupt for next Qbuffer post
  1946. */
  1947. writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
  1948. }
  1949. break;
  1950. case ACB_ADAPTER_TYPE_D: {
  1951. struct MessageUnit_D *reg = acb->pmuD;
  1952. writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
  1953. reg->inbound_doorbell);
  1954. }
  1955. break;
  1956. case ACB_ADAPTER_TYPE_E:
  1957. case ACB_ADAPTER_TYPE_F: {
  1958. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1959. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
  1960. writel(acb->out_doorbell, &reg->iobound_doorbell);
  1961. }
  1962. break;
  1963. }
  1964. }
  1965. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  1966. {
  1967. struct QBUFFER __iomem *qbuffer = NULL;
  1968. switch (acb->adapter_type) {
  1969. case ACB_ADAPTER_TYPE_A: {
  1970. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1971. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1972. }
  1973. break;
  1974. case ACB_ADAPTER_TYPE_B: {
  1975. struct MessageUnit_B *reg = acb->pmuB;
  1976. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1977. }
  1978. break;
  1979. case ACB_ADAPTER_TYPE_C: {
  1980. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1981. qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
  1982. }
  1983. break;
  1984. case ACB_ADAPTER_TYPE_D: {
  1985. struct MessageUnit_D *reg = acb->pmuD;
  1986. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1987. }
  1988. break;
  1989. case ACB_ADAPTER_TYPE_E: {
  1990. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1991. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1992. }
  1993. break;
  1994. case ACB_ADAPTER_TYPE_F: {
  1995. qbuffer = (struct QBUFFER __iomem *)acb->message_rbuffer;
  1996. }
  1997. break;
  1998. }
  1999. return qbuffer;
  2000. }
  2001. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  2002. {
  2003. struct QBUFFER __iomem *pqbuffer = NULL;
  2004. switch (acb->adapter_type) {
  2005. case ACB_ADAPTER_TYPE_A: {
  2006. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2007. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  2008. }
  2009. break;
  2010. case ACB_ADAPTER_TYPE_B: {
  2011. struct MessageUnit_B *reg = acb->pmuB;
  2012. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  2013. }
  2014. break;
  2015. case ACB_ADAPTER_TYPE_C: {
  2016. struct MessageUnit_C __iomem *reg = acb->pmuC;
  2017. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  2018. }
  2019. break;
  2020. case ACB_ADAPTER_TYPE_D: {
  2021. struct MessageUnit_D *reg = acb->pmuD;
  2022. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  2023. }
  2024. break;
  2025. case ACB_ADAPTER_TYPE_E: {
  2026. struct MessageUnit_E __iomem *reg = acb->pmuE;
  2027. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  2028. }
  2029. break;
  2030. case ACB_ADAPTER_TYPE_F:
  2031. pqbuffer = (struct QBUFFER __iomem *)acb->message_wbuffer;
  2032. break;
  2033. }
  2034. return pqbuffer;
  2035. }
  2036. static uint32_t
  2037. arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
  2038. struct QBUFFER __iomem *prbuffer)
  2039. {
  2040. uint8_t *pQbuffer;
  2041. uint8_t *buf1 = NULL;
  2042. uint32_t __iomem *iop_data;
  2043. uint32_t iop_len, data_len, *buf2 = NULL;
  2044. iop_data = (uint32_t __iomem *)prbuffer->data;
  2045. iop_len = readl(&prbuffer->data_len);
  2046. if (iop_len > 0) {
  2047. buf1 = kmalloc(128, GFP_ATOMIC);
  2048. buf2 = (uint32_t *)buf1;
  2049. if (buf1 == NULL)
  2050. return 0;
  2051. data_len = iop_len;
  2052. while (data_len >= 4) {
  2053. *buf2++ = readl(iop_data);
  2054. iop_data++;
  2055. data_len -= 4;
  2056. }
  2057. if (data_len)
  2058. *buf2 = readl(iop_data);
  2059. buf2 = (uint32_t *)buf1;
  2060. }
  2061. while (iop_len > 0) {
  2062. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  2063. *pQbuffer = *buf1;
  2064. acb->rqbuf_putIndex++;
  2065. /* if last, index number set it to 0 */
  2066. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  2067. buf1++;
  2068. iop_len--;
  2069. }
  2070. kfree(buf2);
  2071. /* let IOP know data has been read */
  2072. arcmsr_iop_message_read(acb);
  2073. return 1;
  2074. }
  2075. uint32_t
  2076. arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
  2077. struct QBUFFER __iomem *prbuffer) {
  2078. uint8_t *pQbuffer;
  2079. uint8_t __iomem *iop_data;
  2080. uint32_t iop_len;
  2081. if (acb->adapter_type > ACB_ADAPTER_TYPE_B)
  2082. return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
  2083. iop_data = (uint8_t __iomem *)prbuffer->data;
  2084. iop_len = readl(&prbuffer->data_len);
  2085. while (iop_len > 0) {
  2086. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  2087. *pQbuffer = readb(iop_data);
  2088. acb->rqbuf_putIndex++;
  2089. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  2090. iop_data++;
  2091. iop_len--;
  2092. }
  2093. arcmsr_iop_message_read(acb);
  2094. return 1;
  2095. }
  2096. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  2097. {
  2098. unsigned long flags;
  2099. struct QBUFFER __iomem *prbuffer;
  2100. int32_t buf_empty_len;
  2101. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2102. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  2103. buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
  2104. (ARCMSR_MAX_QBUFFER - 1);
  2105. if (buf_empty_len >= readl(&prbuffer->data_len)) {
  2106. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  2107. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  2108. } else
  2109. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  2110. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2111. }
  2112. static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
  2113. {
  2114. uint8_t *pQbuffer;
  2115. struct QBUFFER __iomem *pwbuffer;
  2116. uint8_t *buf1 = NULL;
  2117. uint32_t __iomem *iop_data;
  2118. uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
  2119. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  2120. buf1 = kmalloc(128, GFP_ATOMIC);
  2121. buf2 = (uint32_t *)buf1;
  2122. if (buf1 == NULL)
  2123. return;
  2124. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  2125. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  2126. iop_data = (uint32_t __iomem *)pwbuffer->data;
  2127. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  2128. && (allxfer_len < 124)) {
  2129. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  2130. *buf1 = *pQbuffer;
  2131. acb->wqbuf_getIndex++;
  2132. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  2133. buf1++;
  2134. allxfer_len++;
  2135. }
  2136. data_len = allxfer_len;
  2137. buf1 = (uint8_t *)buf2;
  2138. while (data_len >= 4) {
  2139. data = *buf2++;
  2140. writel(data, iop_data);
  2141. iop_data++;
  2142. data_len -= 4;
  2143. }
  2144. if (data_len) {
  2145. data = *buf2;
  2146. writel(data, iop_data);
  2147. }
  2148. writel(allxfer_len, &pwbuffer->data_len);
  2149. kfree(buf1);
  2150. arcmsr_iop_message_wrote(acb);
  2151. }
  2152. }
  2153. void
  2154. arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
  2155. {
  2156. uint8_t *pQbuffer;
  2157. struct QBUFFER __iomem *pwbuffer;
  2158. uint8_t __iomem *iop_data;
  2159. int32_t allxfer_len = 0;
  2160. if (acb->adapter_type > ACB_ADAPTER_TYPE_B) {
  2161. arcmsr_write_ioctldata2iop_in_DWORD(acb);
  2162. return;
  2163. }
  2164. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  2165. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  2166. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  2167. iop_data = (uint8_t __iomem *)pwbuffer->data;
  2168. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  2169. && (allxfer_len < 124)) {
  2170. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  2171. writeb(*pQbuffer, iop_data);
  2172. acb->wqbuf_getIndex++;
  2173. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  2174. iop_data++;
  2175. allxfer_len++;
  2176. }
  2177. writel(allxfer_len, &pwbuffer->data_len);
  2178. arcmsr_iop_message_wrote(acb);
  2179. }
  2180. }
  2181. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  2182. {
  2183. unsigned long flags;
  2184. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2185. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  2186. if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  2187. arcmsr_write_ioctldata2iop(acb);
  2188. if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
  2189. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  2190. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2191. }
  2192. static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
  2193. {
  2194. uint32_t outbound_doorbell;
  2195. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2196. outbound_doorbell = readl(&reg->outbound_doorbell);
  2197. do {
  2198. writel(outbound_doorbell, &reg->outbound_doorbell);
  2199. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
  2200. arcmsr_iop2drv_data_wrote_handle(acb);
  2201. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
  2202. arcmsr_iop2drv_data_read_handle(acb);
  2203. outbound_doorbell = readl(&reg->outbound_doorbell);
  2204. } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
  2205. | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
  2206. }
  2207. static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
  2208. {
  2209. uint32_t outbound_doorbell;
  2210. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  2211. /*
  2212. *******************************************************************
  2213. ** Maybe here we need to check wrqbuffer_lock is lock or not
  2214. ** DOORBELL: din! don!
  2215. ** check if there are any mail need to pack from firmware
  2216. *******************************************************************
  2217. */
  2218. outbound_doorbell = readl(&reg->outbound_doorbell);
  2219. do {
  2220. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  2221. readl(&reg->outbound_doorbell_clear);
  2222. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
  2223. arcmsr_iop2drv_data_wrote_handle(pACB);
  2224. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
  2225. arcmsr_iop2drv_data_read_handle(pACB);
  2226. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
  2227. arcmsr_hbaC_message_isr(pACB);
  2228. outbound_doorbell = readl(&reg->outbound_doorbell);
  2229. } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
  2230. | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
  2231. | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
  2232. }
  2233. static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
  2234. {
  2235. uint32_t outbound_doorbell;
  2236. struct MessageUnit_D *pmu = pACB->pmuD;
  2237. outbound_doorbell = readl(pmu->outbound_doorbell);
  2238. do {
  2239. writel(outbound_doorbell, pmu->outbound_doorbell);
  2240. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
  2241. arcmsr_hbaD_message_isr(pACB);
  2242. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
  2243. arcmsr_iop2drv_data_wrote_handle(pACB);
  2244. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
  2245. arcmsr_iop2drv_data_read_handle(pACB);
  2246. outbound_doorbell = readl(pmu->outbound_doorbell);
  2247. } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
  2248. | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
  2249. | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
  2250. }
  2251. static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB)
  2252. {
  2253. uint32_t outbound_doorbell, in_doorbell, tmp, i;
  2254. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  2255. if (pACB->adapter_type == ACB_ADAPTER_TYPE_F) {
  2256. for (i = 0; i < 5; i++) {
  2257. in_doorbell = readl(&reg->iobound_doorbell);
  2258. if (in_doorbell != 0)
  2259. break;
  2260. }
  2261. } else
  2262. in_doorbell = readl(&reg->iobound_doorbell);
  2263. outbound_doorbell = in_doorbell ^ pACB->in_doorbell;
  2264. do {
  2265. writel(0, &reg->host_int_status); /* clear interrupt */
  2266. if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
  2267. arcmsr_iop2drv_data_wrote_handle(pACB);
  2268. }
  2269. if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
  2270. arcmsr_iop2drv_data_read_handle(pACB);
  2271. }
  2272. if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
  2273. arcmsr_hbaE_message_isr(pACB);
  2274. }
  2275. tmp = in_doorbell;
  2276. in_doorbell = readl(&reg->iobound_doorbell);
  2277. outbound_doorbell = tmp ^ in_doorbell;
  2278. } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
  2279. | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
  2280. | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE));
  2281. pACB->in_doorbell = in_doorbell;
  2282. }
  2283. static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
  2284. {
  2285. uint32_t flag_ccb;
  2286. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2287. struct ARCMSR_CDB *pARCMSR_CDB;
  2288. struct CommandControlBlock *pCCB;
  2289. bool error;
  2290. unsigned long cdb_phy_addr;
  2291. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  2292. cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
  2293. if (acb->cdb_phyadd_hipart)
  2294. cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
  2295. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
  2296. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  2297. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2298. arcmsr_drain_donequeue(acb, pCCB, error);
  2299. }
  2300. }
  2301. static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
  2302. {
  2303. uint32_t index;
  2304. uint32_t flag_ccb;
  2305. struct MessageUnit_B *reg = acb->pmuB;
  2306. struct ARCMSR_CDB *pARCMSR_CDB;
  2307. struct CommandControlBlock *pCCB;
  2308. bool error;
  2309. unsigned long cdb_phy_addr;
  2310. index = reg->doneq_index;
  2311. while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
  2312. cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
  2313. if (acb->cdb_phyadd_hipart)
  2314. cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
  2315. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
  2316. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  2317. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2318. arcmsr_drain_donequeue(acb, pCCB, error);
  2319. reg->done_qbuffer[index] = 0;
  2320. index++;
  2321. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  2322. reg->doneq_index = index;
  2323. }
  2324. }
  2325. static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
  2326. {
  2327. struct MessageUnit_C __iomem *phbcmu;
  2328. struct ARCMSR_CDB *arcmsr_cdb;
  2329. struct CommandControlBlock *ccb;
  2330. uint32_t flag_ccb, throttling = 0;
  2331. unsigned long ccb_cdb_phy;
  2332. int error;
  2333. phbcmu = acb->pmuC;
  2334. /* areca cdb command done */
  2335. /* Use correct offset and size for syncing */
  2336. while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
  2337. 0xFFFFFFFF) {
  2338. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2339. if (acb->cdb_phyadd_hipart)
  2340. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  2341. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  2342. + ccb_cdb_phy);
  2343. ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
  2344. arcmsr_cdb);
  2345. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  2346. ? true : false;
  2347. /* check if command done with no error */
  2348. arcmsr_drain_donequeue(acb, ccb, error);
  2349. throttling++;
  2350. if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
  2351. writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
  2352. &phbcmu->inbound_doorbell);
  2353. throttling = 0;
  2354. }
  2355. }
  2356. }
  2357. static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
  2358. {
  2359. u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
  2360. uint32_t addressLow;
  2361. int error;
  2362. struct MessageUnit_D *pmu;
  2363. struct ARCMSR_CDB *arcmsr_cdb;
  2364. struct CommandControlBlock *ccb;
  2365. unsigned long flags, ccb_cdb_phy;
  2366. spin_lock_irqsave(&acb->doneq_lock, flags);
  2367. pmu = acb->pmuD;
  2368. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  2369. doneq_index = pmu->doneq_index;
  2370. if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
  2371. do {
  2372. toggle = doneq_index & 0x4000;
  2373. index_stripped = (doneq_index & 0xFFF) + 1;
  2374. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  2375. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  2376. ((toggle ^ 0x4000) + 1);
  2377. doneq_index = pmu->doneq_index;
  2378. addressLow = pmu->done_qbuffer[doneq_index &
  2379. 0xFFF].addressLow;
  2380. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  2381. if (acb->cdb_phyadd_hipart)
  2382. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  2383. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  2384. + ccb_cdb_phy);
  2385. ccb = container_of(arcmsr_cdb,
  2386. struct CommandControlBlock, arcmsr_cdb);
  2387. error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  2388. ? true : false;
  2389. arcmsr_drain_donequeue(acb, ccb, error);
  2390. writel(doneq_index, pmu->outboundlist_read_pointer);
  2391. } while ((doneq_index & 0xFFF) !=
  2392. (outbound_write_pointer & 0xFFF));
  2393. }
  2394. writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
  2395. pmu->outboundlist_interrupt_cause);
  2396. readl(pmu->outboundlist_interrupt_cause);
  2397. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2398. }
  2399. static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb)
  2400. {
  2401. uint32_t doneq_index;
  2402. uint16_t cmdSMID;
  2403. int error;
  2404. struct MessageUnit_E __iomem *pmu;
  2405. struct CommandControlBlock *ccb;
  2406. unsigned long flags;
  2407. spin_lock_irqsave(&acb->doneq_lock, flags);
  2408. doneq_index = acb->doneq_index;
  2409. pmu = acb->pmuE;
  2410. while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) {
  2411. cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
  2412. ccb = acb->pccb_pool[cmdSMID];
  2413. error = (acb->pCompletionQ[doneq_index].cmdFlag
  2414. & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  2415. arcmsr_drain_donequeue(acb, ccb, error);
  2416. doneq_index++;
  2417. if (doneq_index >= acb->completionQ_entry)
  2418. doneq_index = 0;
  2419. }
  2420. acb->doneq_index = doneq_index;
  2421. writel(doneq_index, &pmu->reply_post_consumer_index);
  2422. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2423. }
  2424. static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb)
  2425. {
  2426. uint32_t doneq_index;
  2427. uint16_t cmdSMID;
  2428. int error;
  2429. struct MessageUnit_F __iomem *phbcmu;
  2430. struct CommandControlBlock *ccb;
  2431. unsigned long flags;
  2432. spin_lock_irqsave(&acb->doneq_lock, flags);
  2433. doneq_index = acb->doneq_index;
  2434. phbcmu = acb->pmuF;
  2435. while (1) {
  2436. cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
  2437. if (cmdSMID == 0xffff)
  2438. break;
  2439. ccb = acb->pccb_pool[cmdSMID];
  2440. error = (acb->pCompletionQ[doneq_index].cmdFlag &
  2441. ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  2442. arcmsr_drain_donequeue(acb, ccb, error);
  2443. acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
  2444. doneq_index++;
  2445. if (doneq_index >= acb->completionQ_entry)
  2446. doneq_index = 0;
  2447. }
  2448. acb->doneq_index = doneq_index;
  2449. writel(doneq_index, &phbcmu->reply_post_consumer_index);
  2450. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2451. }
  2452. /*
  2453. **********************************************************************************
  2454. ** Handle a message interrupt
  2455. **
  2456. ** The only message interrupt we expect is in response to a query for the current adapter config.
  2457. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  2458. **********************************************************************************
  2459. */
  2460. static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
  2461. {
  2462. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2463. /*clear interrupt and message state*/
  2464. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
  2465. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2466. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2467. }
  2468. static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
  2469. {
  2470. struct MessageUnit_B *reg = acb->pmuB;
  2471. /*clear interrupt and message state*/
  2472. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2473. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2474. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2475. }
  2476. /*
  2477. **********************************************************************************
  2478. ** Handle a message interrupt
  2479. **
  2480. ** The only message interrupt we expect is in response to a query for the
  2481. ** current adapter config.
  2482. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  2483. **********************************************************************************
  2484. */
  2485. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
  2486. {
  2487. struct MessageUnit_C __iomem *reg = acb->pmuC;
  2488. /*clear interrupt and message state*/
  2489. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
  2490. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2491. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2492. }
  2493. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
  2494. {
  2495. struct MessageUnit_D *reg = acb->pmuD;
  2496. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
  2497. readl(reg->outbound_doorbell);
  2498. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2499. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2500. }
  2501. static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb)
  2502. {
  2503. struct MessageUnit_E __iomem *reg = acb->pmuE;
  2504. writel(0, &reg->host_int_status);
  2505. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2506. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2507. }
  2508. static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
  2509. {
  2510. uint32_t outbound_intstatus;
  2511. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2512. outbound_intstatus = readl(&reg->outbound_intstatus) &
  2513. acb->outbound_int_enable;
  2514. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
  2515. return IRQ_NONE;
  2516. do {
  2517. writel(outbound_intstatus, &reg->outbound_intstatus);
  2518. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
  2519. arcmsr_hbaA_doorbell_isr(acb);
  2520. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
  2521. arcmsr_hbaA_postqueue_isr(acb);
  2522. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
  2523. arcmsr_hbaA_message_isr(acb);
  2524. outbound_intstatus = readl(&reg->outbound_intstatus) &
  2525. acb->outbound_int_enable;
  2526. } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
  2527. | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
  2528. | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
  2529. return IRQ_HANDLED;
  2530. }
  2531. static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
  2532. {
  2533. uint32_t outbound_doorbell;
  2534. struct MessageUnit_B *reg = acb->pmuB;
  2535. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  2536. acb->outbound_int_enable;
  2537. if (!outbound_doorbell)
  2538. return IRQ_NONE;
  2539. do {
  2540. writel(~outbound_doorbell, reg->iop2drv_doorbell);
  2541. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  2542. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
  2543. arcmsr_iop2drv_data_wrote_handle(acb);
  2544. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
  2545. arcmsr_iop2drv_data_read_handle(acb);
  2546. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
  2547. arcmsr_hbaB_postqueue_isr(acb);
  2548. if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
  2549. arcmsr_hbaB_message_isr(acb);
  2550. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  2551. acb->outbound_int_enable;
  2552. } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
  2553. | ARCMSR_IOP2DRV_DATA_READ_OK
  2554. | ARCMSR_IOP2DRV_CDB_DONE
  2555. | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
  2556. return IRQ_HANDLED;
  2557. }
  2558. static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
  2559. {
  2560. uint32_t host_interrupt_status;
  2561. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  2562. /*
  2563. *********************************************
  2564. ** check outbound intstatus
  2565. *********************************************
  2566. */
  2567. host_interrupt_status = readl(&phbcmu->host_int_status) &
  2568. (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  2569. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
  2570. if (!host_interrupt_status)
  2571. return IRQ_NONE;
  2572. do {
  2573. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
  2574. arcmsr_hbaC_doorbell_isr(pACB);
  2575. /* MU post queue interrupts*/
  2576. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
  2577. arcmsr_hbaC_postqueue_isr(pACB);
  2578. host_interrupt_status = readl(&phbcmu->host_int_status);
  2579. } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  2580. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
  2581. return IRQ_HANDLED;
  2582. }
  2583. static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
  2584. {
  2585. u32 host_interrupt_status;
  2586. struct MessageUnit_D *pmu = pACB->pmuD;
  2587. host_interrupt_status = readl(pmu->host_int_status) &
  2588. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  2589. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
  2590. if (!host_interrupt_status)
  2591. return IRQ_NONE;
  2592. do {
  2593. /* MU post queue interrupts*/
  2594. if (host_interrupt_status &
  2595. ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
  2596. arcmsr_hbaD_postqueue_isr(pACB);
  2597. if (host_interrupt_status &
  2598. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
  2599. arcmsr_hbaD_doorbell_isr(pACB);
  2600. host_interrupt_status = readl(pmu->host_int_status);
  2601. } while (host_interrupt_status &
  2602. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  2603. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
  2604. return IRQ_HANDLED;
  2605. }
  2606. static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB)
  2607. {
  2608. uint32_t host_interrupt_status;
  2609. struct MessageUnit_E __iomem *pmu = pACB->pmuE;
  2610. host_interrupt_status = readl(&pmu->host_int_status) &
  2611. (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
  2612. ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
  2613. if (!host_interrupt_status)
  2614. return IRQ_NONE;
  2615. do {
  2616. /* MU ioctl transfer doorbell interrupts*/
  2617. if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
  2618. arcmsr_hbaE_doorbell_isr(pACB);
  2619. }
  2620. /* MU post queue interrupts*/
  2621. if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
  2622. arcmsr_hbaE_postqueue_isr(pACB);
  2623. }
  2624. host_interrupt_status = readl(&pmu->host_int_status);
  2625. } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
  2626. ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
  2627. return IRQ_HANDLED;
  2628. }
  2629. static irqreturn_t arcmsr_hbaF_handle_isr(struct AdapterControlBlock *pACB)
  2630. {
  2631. uint32_t host_interrupt_status;
  2632. struct MessageUnit_F __iomem *phbcmu = pACB->pmuF;
  2633. host_interrupt_status = readl(&phbcmu->host_int_status) &
  2634. (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
  2635. ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
  2636. if (!host_interrupt_status)
  2637. return IRQ_NONE;
  2638. do {
  2639. /* MU post queue interrupts*/
  2640. if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR)
  2641. arcmsr_hbaF_postqueue_isr(pACB);
  2642. /* MU ioctl transfer doorbell interrupts*/
  2643. if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)
  2644. arcmsr_hbaE_doorbell_isr(pACB);
  2645. host_interrupt_status = readl(&phbcmu->host_int_status);
  2646. } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
  2647. ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
  2648. return IRQ_HANDLED;
  2649. }
  2650. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  2651. {
  2652. switch (acb->adapter_type) {
  2653. case ACB_ADAPTER_TYPE_A:
  2654. return arcmsr_hbaA_handle_isr(acb);
  2655. case ACB_ADAPTER_TYPE_B:
  2656. return arcmsr_hbaB_handle_isr(acb);
  2657. case ACB_ADAPTER_TYPE_C:
  2658. return arcmsr_hbaC_handle_isr(acb);
  2659. case ACB_ADAPTER_TYPE_D:
  2660. return arcmsr_hbaD_handle_isr(acb);
  2661. case ACB_ADAPTER_TYPE_E:
  2662. return arcmsr_hbaE_handle_isr(acb);
  2663. case ACB_ADAPTER_TYPE_F:
  2664. return arcmsr_hbaF_handle_isr(acb);
  2665. default:
  2666. return IRQ_NONE;
  2667. }
  2668. }
  2669. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  2670. {
  2671. if (acb) {
  2672. /* stop adapter background rebuild */
  2673. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  2674. uint32_t intmask_org;
  2675. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  2676. intmask_org = arcmsr_disable_outbound_ints(acb);
  2677. arcmsr_stop_adapter_bgrb(acb);
  2678. arcmsr_flush_adapter_cache(acb);
  2679. arcmsr_enable_outbound_ints(acb, intmask_org);
  2680. }
  2681. }
  2682. }
  2683. void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
  2684. {
  2685. uint32_t i;
  2686. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2687. for (i = 0; i < 15; i++) {
  2688. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2689. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2690. acb->rqbuf_getIndex = 0;
  2691. acb->rqbuf_putIndex = 0;
  2692. arcmsr_iop_message_read(acb);
  2693. mdelay(30);
  2694. } else if (acb->rqbuf_getIndex !=
  2695. acb->rqbuf_putIndex) {
  2696. acb->rqbuf_getIndex = 0;
  2697. acb->rqbuf_putIndex = 0;
  2698. mdelay(30);
  2699. } else
  2700. break;
  2701. }
  2702. }
  2703. }
  2704. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  2705. struct scsi_cmnd *cmd)
  2706. {
  2707. char *buffer;
  2708. unsigned short use_sg;
  2709. int retvalue = 0, transfer_len = 0;
  2710. unsigned long flags;
  2711. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  2712. uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
  2713. (uint32_t)cmd->cmnd[6] << 16 |
  2714. (uint32_t)cmd->cmnd[7] << 8 |
  2715. (uint32_t)cmd->cmnd[8];
  2716. struct scatterlist *sg;
  2717. use_sg = scsi_sg_count(cmd);
  2718. sg = scsi_sglist(cmd);
  2719. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2720. if (use_sg > 1) {
  2721. retvalue = ARCMSR_MESSAGE_FAIL;
  2722. goto message_out;
  2723. }
  2724. transfer_len += sg->length;
  2725. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  2726. retvalue = ARCMSR_MESSAGE_FAIL;
  2727. pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
  2728. goto message_out;
  2729. }
  2730. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
  2731. switch (controlcode) {
  2732. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  2733. unsigned char *ver_addr;
  2734. uint8_t *ptmpQbuffer;
  2735. uint32_t allxfer_len = 0;
  2736. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2737. if (!ver_addr) {
  2738. retvalue = ARCMSR_MESSAGE_FAIL;
  2739. pr_info("%s: memory not enough!\n", __func__);
  2740. goto message_out;
  2741. }
  2742. ptmpQbuffer = ver_addr;
  2743. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2744. if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
  2745. unsigned int tail = acb->rqbuf_getIndex;
  2746. unsigned int head = acb->rqbuf_putIndex;
  2747. unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
  2748. allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
  2749. if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
  2750. allxfer_len = ARCMSR_API_DATA_BUFLEN;
  2751. if (allxfer_len <= cnt_to_end)
  2752. memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
  2753. else {
  2754. memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
  2755. memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
  2756. }
  2757. acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
  2758. }
  2759. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
  2760. allxfer_len);
  2761. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2762. struct QBUFFER __iomem *prbuffer;
  2763. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2764. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  2765. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  2766. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  2767. }
  2768. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2769. kfree(ver_addr);
  2770. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  2771. if (acb->fw_flag == FW_DEADLOCK)
  2772. pcmdmessagefld->cmdmessage.ReturnCode =
  2773. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2774. else
  2775. pcmdmessagefld->cmdmessage.ReturnCode =
  2776. ARCMSR_MESSAGE_RETURNCODE_OK;
  2777. break;
  2778. }
  2779. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  2780. unsigned char *ver_addr;
  2781. uint32_t user_len;
  2782. int32_t cnt2end;
  2783. uint8_t *pQbuffer, *ptmpuserbuffer;
  2784. user_len = pcmdmessagefld->cmdmessage.Length;
  2785. if (user_len > ARCMSR_API_DATA_BUFLEN) {
  2786. retvalue = ARCMSR_MESSAGE_FAIL;
  2787. goto message_out;
  2788. }
  2789. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2790. if (!ver_addr) {
  2791. retvalue = ARCMSR_MESSAGE_FAIL;
  2792. goto message_out;
  2793. }
  2794. ptmpuserbuffer = ver_addr;
  2795. memcpy(ptmpuserbuffer,
  2796. pcmdmessagefld->messagedatabuffer, user_len);
  2797. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2798. if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
  2799. struct SENSE_DATA *sensebuffer =
  2800. (struct SENSE_DATA *)cmd->sense_buffer;
  2801. arcmsr_write_ioctldata2iop(acb);
  2802. /* has error report sensedata */
  2803. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  2804. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  2805. sensebuffer->AdditionalSenseLength = 0x0A;
  2806. sensebuffer->AdditionalSenseCode = 0x20;
  2807. sensebuffer->Valid = 1;
  2808. retvalue = ARCMSR_MESSAGE_FAIL;
  2809. } else {
  2810. pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
  2811. cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
  2812. if (user_len > cnt2end) {
  2813. memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
  2814. ptmpuserbuffer += cnt2end;
  2815. user_len -= cnt2end;
  2816. acb->wqbuf_putIndex = 0;
  2817. pQbuffer = acb->wqbuffer;
  2818. }
  2819. memcpy(pQbuffer, ptmpuserbuffer, user_len);
  2820. acb->wqbuf_putIndex += user_len;
  2821. acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  2822. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  2823. acb->acb_flags &=
  2824. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  2825. arcmsr_write_ioctldata2iop(acb);
  2826. }
  2827. }
  2828. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2829. kfree(ver_addr);
  2830. if (acb->fw_flag == FW_DEADLOCK)
  2831. pcmdmessagefld->cmdmessage.ReturnCode =
  2832. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2833. else
  2834. pcmdmessagefld->cmdmessage.ReturnCode =
  2835. ARCMSR_MESSAGE_RETURNCODE_OK;
  2836. break;
  2837. }
  2838. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  2839. uint8_t *pQbuffer = acb->rqbuffer;
  2840. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2841. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2842. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2843. acb->rqbuf_getIndex = 0;
  2844. acb->rqbuf_putIndex = 0;
  2845. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2846. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2847. if (acb->fw_flag == FW_DEADLOCK)
  2848. pcmdmessagefld->cmdmessage.ReturnCode =
  2849. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2850. else
  2851. pcmdmessagefld->cmdmessage.ReturnCode =
  2852. ARCMSR_MESSAGE_RETURNCODE_OK;
  2853. break;
  2854. }
  2855. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  2856. uint8_t *pQbuffer = acb->wqbuffer;
  2857. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2858. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2859. ACB_F_MESSAGE_WQBUFFER_READED);
  2860. acb->wqbuf_getIndex = 0;
  2861. acb->wqbuf_putIndex = 0;
  2862. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2863. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2864. if (acb->fw_flag == FW_DEADLOCK)
  2865. pcmdmessagefld->cmdmessage.ReturnCode =
  2866. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2867. else
  2868. pcmdmessagefld->cmdmessage.ReturnCode =
  2869. ARCMSR_MESSAGE_RETURNCODE_OK;
  2870. break;
  2871. }
  2872. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  2873. uint8_t *pQbuffer;
  2874. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2875. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2876. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2877. acb->rqbuf_getIndex = 0;
  2878. acb->rqbuf_putIndex = 0;
  2879. pQbuffer = acb->rqbuffer;
  2880. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2881. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2882. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2883. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2884. ACB_F_MESSAGE_WQBUFFER_READED);
  2885. acb->wqbuf_getIndex = 0;
  2886. acb->wqbuf_putIndex = 0;
  2887. pQbuffer = acb->wqbuffer;
  2888. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2889. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2890. if (acb->fw_flag == FW_DEADLOCK)
  2891. pcmdmessagefld->cmdmessage.ReturnCode =
  2892. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2893. else
  2894. pcmdmessagefld->cmdmessage.ReturnCode =
  2895. ARCMSR_MESSAGE_RETURNCODE_OK;
  2896. break;
  2897. }
  2898. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  2899. if (acb->fw_flag == FW_DEADLOCK)
  2900. pcmdmessagefld->cmdmessage.ReturnCode =
  2901. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2902. else
  2903. pcmdmessagefld->cmdmessage.ReturnCode =
  2904. ARCMSR_MESSAGE_RETURNCODE_3F;
  2905. break;
  2906. }
  2907. case ARCMSR_MESSAGE_SAY_HELLO: {
  2908. int8_t *hello_string = "Hello! I am ARCMSR";
  2909. if (acb->fw_flag == FW_DEADLOCK)
  2910. pcmdmessagefld->cmdmessage.ReturnCode =
  2911. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2912. else
  2913. pcmdmessagefld->cmdmessage.ReturnCode =
  2914. ARCMSR_MESSAGE_RETURNCODE_OK;
  2915. memcpy(pcmdmessagefld->messagedatabuffer,
  2916. hello_string, (int16_t)strlen(hello_string));
  2917. break;
  2918. }
  2919. case ARCMSR_MESSAGE_SAY_GOODBYE: {
  2920. if (acb->fw_flag == FW_DEADLOCK)
  2921. pcmdmessagefld->cmdmessage.ReturnCode =
  2922. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2923. else
  2924. pcmdmessagefld->cmdmessage.ReturnCode =
  2925. ARCMSR_MESSAGE_RETURNCODE_OK;
  2926. arcmsr_iop_parking(acb);
  2927. break;
  2928. }
  2929. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
  2930. if (acb->fw_flag == FW_DEADLOCK)
  2931. pcmdmessagefld->cmdmessage.ReturnCode =
  2932. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2933. else
  2934. pcmdmessagefld->cmdmessage.ReturnCode =
  2935. ARCMSR_MESSAGE_RETURNCODE_OK;
  2936. arcmsr_flush_adapter_cache(acb);
  2937. break;
  2938. }
  2939. default:
  2940. retvalue = ARCMSR_MESSAGE_FAIL;
  2941. pr_info("%s: unknown controlcode!\n", __func__);
  2942. }
  2943. message_out:
  2944. if (use_sg) {
  2945. struct scatterlist *sg = scsi_sglist(cmd);
  2946. kunmap_atomic(buffer - sg->offset);
  2947. }
  2948. return retvalue;
  2949. }
  2950. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  2951. {
  2952. struct list_head *head;
  2953. struct CommandControlBlock *ccb = NULL;
  2954. unsigned long flags;
  2955. spin_lock_irqsave(&acb->ccblist_lock, flags);
  2956. head = &acb->ccb_free_list;
  2957. if (!list_empty(head)) {
  2958. ccb = list_entry(head->next, struct CommandControlBlock, list);
  2959. list_del_init(&ccb->list);
  2960. }else{
  2961. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2962. return NULL;
  2963. }
  2964. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2965. return ccb;
  2966. }
  2967. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  2968. struct scsi_cmnd *cmd)
  2969. {
  2970. switch (cmd->cmnd[0]) {
  2971. case INQUIRY: {
  2972. unsigned char inqdata[36];
  2973. char *buffer;
  2974. struct scatterlist *sg;
  2975. if (cmd->device->lun) {
  2976. cmd->result = (DID_TIME_OUT << 16);
  2977. scsi_done(cmd);
  2978. return;
  2979. }
  2980. inqdata[0] = TYPE_PROCESSOR;
  2981. /* Periph Qualifier & Periph Dev Type */
  2982. inqdata[1] = 0;
  2983. /* rem media bit & Dev Type Modifier */
  2984. inqdata[2] = 0;
  2985. /* ISO, ECMA, & ANSI versions */
  2986. inqdata[4] = 31;
  2987. /* length of additional data */
  2988. memcpy(&inqdata[8], "Areca ", 8);
  2989. /* Vendor Identification */
  2990. memcpy(&inqdata[16], "RAID controller ", 16);
  2991. /* Product Identification */
  2992. memcpy(&inqdata[32], "R001", 4); /* Product Revision */
  2993. sg = scsi_sglist(cmd);
  2994. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2995. memcpy(buffer, inqdata, sizeof(inqdata));
  2996. sg = scsi_sglist(cmd);
  2997. kunmap_atomic(buffer - sg->offset);
  2998. scsi_done(cmd);
  2999. }
  3000. break;
  3001. case WRITE_BUFFER:
  3002. case READ_BUFFER: {
  3003. if (arcmsr_iop_message_xfer(acb, cmd))
  3004. cmd->result = (DID_ERROR << 16);
  3005. scsi_done(cmd);
  3006. }
  3007. break;
  3008. default:
  3009. scsi_done(cmd);
  3010. }
  3011. }
  3012. static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd)
  3013. {
  3014. struct Scsi_Host *host = cmd->device->host;
  3015. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  3016. struct CommandControlBlock *ccb;
  3017. int target = cmd->device->id;
  3018. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) {
  3019. cmd->result = (DID_NO_CONNECT << 16);
  3020. scsi_done(cmd);
  3021. return 0;
  3022. }
  3023. cmd->host_scribble = NULL;
  3024. cmd->result = 0;
  3025. if (target == 16) {
  3026. /* virtual device for iop message transfer */
  3027. arcmsr_handle_virtual_command(acb, cmd);
  3028. return 0;
  3029. }
  3030. ccb = arcmsr_get_freeccb(acb);
  3031. if (!ccb)
  3032. return SCSI_MLQUEUE_HOST_BUSY;
  3033. if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
  3034. cmd->result = (DID_ERROR << 16) | SAM_STAT_RESERVATION_CONFLICT;
  3035. scsi_done(cmd);
  3036. return 0;
  3037. }
  3038. arcmsr_post_ccb(acb, ccb);
  3039. return 0;
  3040. }
  3041. static DEF_SCSI_QCMD(arcmsr_queue_command)
  3042. static int arcmsr_slave_config(struct scsi_device *sdev)
  3043. {
  3044. unsigned int dev_timeout;
  3045. dev_timeout = sdev->request_queue->rq_timeout;
  3046. if ((cmd_timeout > 0) && ((cmd_timeout * HZ) > dev_timeout))
  3047. blk_queue_rq_timeout(sdev->request_queue, cmd_timeout * HZ);
  3048. return 0;
  3049. }
  3050. static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer)
  3051. {
  3052. int count;
  3053. uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model;
  3054. uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version;
  3055. uint32_t *acb_device_map = (uint32_t *)pACB->device_map;
  3056. uint32_t *firm_model = &rwbuffer[15];
  3057. uint32_t *firm_version = &rwbuffer[17];
  3058. uint32_t *device_map = &rwbuffer[21];
  3059. count = 2;
  3060. while (count) {
  3061. *acb_firm_model = readl(firm_model);
  3062. acb_firm_model++;
  3063. firm_model++;
  3064. count--;
  3065. }
  3066. count = 4;
  3067. while (count) {
  3068. *acb_firm_version = readl(firm_version);
  3069. acb_firm_version++;
  3070. firm_version++;
  3071. count--;
  3072. }
  3073. count = 4;
  3074. while (count) {
  3075. *acb_device_map = readl(device_map);
  3076. acb_device_map++;
  3077. device_map++;
  3078. count--;
  3079. }
  3080. pACB->signature = readl(&rwbuffer[0]);
  3081. pACB->firm_request_len = readl(&rwbuffer[1]);
  3082. pACB->firm_numbers_queue = readl(&rwbuffer[2]);
  3083. pACB->firm_sdram_size = readl(&rwbuffer[3]);
  3084. pACB->firm_hd_channels = readl(&rwbuffer[4]);
  3085. pACB->firm_cfg_version = readl(&rwbuffer[25]);
  3086. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  3087. pACB->host->host_no,
  3088. pACB->firm_model,
  3089. pACB->firm_version);
  3090. }
  3091. static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
  3092. {
  3093. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3094. arcmsr_wait_firmware_ready(acb);
  3095. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3096. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3097. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  3098. miscellaneous data' timeout \n", acb->host->host_no);
  3099. return false;
  3100. }
  3101. arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
  3102. return true;
  3103. }
  3104. static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
  3105. {
  3106. struct MessageUnit_B *reg = acb->pmuB;
  3107. arcmsr_wait_firmware_ready(acb);
  3108. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  3109. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3110. printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
  3111. return false;
  3112. }
  3113. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  3114. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3115. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  3116. miscellaneous data' timeout \n", acb->host->host_no);
  3117. return false;
  3118. }
  3119. arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
  3120. return true;
  3121. }
  3122. static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
  3123. {
  3124. uint32_t intmask_org;
  3125. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  3126. /* disable all outbound interrupt */
  3127. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  3128. writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  3129. /* wait firmware ready */
  3130. arcmsr_wait_firmware_ready(pACB);
  3131. /* post "get config" instruction */
  3132. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3133. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3134. /* wait message ready */
  3135. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  3136. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  3137. miscellaneous data' timeout \n", pACB->host->host_no);
  3138. return false;
  3139. }
  3140. arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
  3141. return true;
  3142. }
  3143. static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
  3144. {
  3145. struct MessageUnit_D *reg = acb->pmuD;
  3146. if (readl(acb->pmuD->outbound_doorbell) &
  3147. ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  3148. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  3149. acb->pmuD->outbound_doorbell);/*clear interrupt*/
  3150. }
  3151. arcmsr_wait_firmware_ready(acb);
  3152. /* post "get config" instruction */
  3153. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
  3154. /* wait message ready */
  3155. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  3156. pr_notice("arcmsr%d: wait get adapter firmware "
  3157. "miscellaneous data timeout\n", acb->host->host_no);
  3158. return false;
  3159. }
  3160. arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer);
  3161. return true;
  3162. }
  3163. static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB)
  3164. {
  3165. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  3166. uint32_t intmask_org;
  3167. /* disable all outbound interrupt */
  3168. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  3169. writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  3170. /* wait firmware ready */
  3171. arcmsr_wait_firmware_ready(pACB);
  3172. mdelay(20);
  3173. /* post "get config" instruction */
  3174. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3175. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3176. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  3177. /* wait message ready */
  3178. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  3179. pr_notice("arcmsr%d: wait get adapter firmware "
  3180. "miscellaneous data timeout\n", pACB->host->host_no);
  3181. return false;
  3182. }
  3183. arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
  3184. return true;
  3185. }
  3186. static bool arcmsr_hbaF_get_config(struct AdapterControlBlock *pACB)
  3187. {
  3188. struct MessageUnit_F __iomem *reg = pACB->pmuF;
  3189. uint32_t intmask_org;
  3190. /* disable all outbound interrupt */
  3191. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  3192. writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  3193. /* wait firmware ready */
  3194. arcmsr_wait_firmware_ready(pACB);
  3195. /* post "get config" instruction */
  3196. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3197. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3198. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  3199. /* wait message ready */
  3200. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  3201. pr_notice("arcmsr%d: wait get adapter firmware miscellaneous data timeout\n",
  3202. pACB->host->host_no);
  3203. return false;
  3204. }
  3205. arcmsr_get_adapter_config(pACB, pACB->msgcode_rwbuffer);
  3206. return true;
  3207. }
  3208. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  3209. {
  3210. bool rtn = false;
  3211. switch (acb->adapter_type) {
  3212. case ACB_ADAPTER_TYPE_A:
  3213. rtn = arcmsr_hbaA_get_config(acb);
  3214. break;
  3215. case ACB_ADAPTER_TYPE_B:
  3216. rtn = arcmsr_hbaB_get_config(acb);
  3217. break;
  3218. case ACB_ADAPTER_TYPE_C:
  3219. rtn = arcmsr_hbaC_get_config(acb);
  3220. break;
  3221. case ACB_ADAPTER_TYPE_D:
  3222. rtn = arcmsr_hbaD_get_config(acb);
  3223. break;
  3224. case ACB_ADAPTER_TYPE_E:
  3225. rtn = arcmsr_hbaE_get_config(acb);
  3226. break;
  3227. case ACB_ADAPTER_TYPE_F:
  3228. rtn = arcmsr_hbaF_get_config(acb);
  3229. break;
  3230. default:
  3231. break;
  3232. }
  3233. acb->maxOutstanding = acb->firm_numbers_queue - 1;
  3234. if (acb->host->can_queue >= acb->firm_numbers_queue)
  3235. acb->host->can_queue = acb->maxOutstanding;
  3236. else
  3237. acb->maxOutstanding = acb->host->can_queue;
  3238. acb->maxFreeCCB = acb->host->can_queue;
  3239. if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM)
  3240. acb->maxFreeCCB += 64;
  3241. return rtn;
  3242. }
  3243. static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
  3244. struct CommandControlBlock *poll_ccb)
  3245. {
  3246. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3247. struct CommandControlBlock *ccb;
  3248. struct ARCMSR_CDB *arcmsr_cdb;
  3249. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  3250. int rtn;
  3251. bool error;
  3252. unsigned long ccb_cdb_phy;
  3253. polling_hba_ccb_retry:
  3254. poll_count++;
  3255. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  3256. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  3257. while (1) {
  3258. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  3259. if (poll_ccb_done){
  3260. rtn = SUCCESS;
  3261. break;
  3262. }else {
  3263. msleep(25);
  3264. if (poll_count > 100){
  3265. rtn = FAILED;
  3266. break;
  3267. }
  3268. goto polling_hba_ccb_retry;
  3269. }
  3270. }
  3271. ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
  3272. if (acb->cdb_phyadd_hipart)
  3273. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  3274. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  3275. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  3276. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  3277. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  3278. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  3279. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  3280. " poll command abort successfully \n"
  3281. , acb->host->host_no
  3282. , ccb->pcmd->device->id
  3283. , (u32)ccb->pcmd->device->lun
  3284. , ccb);
  3285. ccb->pcmd->result = DID_ABORT << 16;
  3286. arcmsr_ccb_complete(ccb);
  3287. continue;
  3288. }
  3289. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  3290. " command done ccb = '0x%p'"
  3291. "ccboutstandingcount = %d \n"
  3292. , acb->host->host_no
  3293. , ccb
  3294. , atomic_read(&acb->ccboutstandingcount));
  3295. continue;
  3296. }
  3297. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  3298. arcmsr_report_ccb_state(acb, ccb, error);
  3299. }
  3300. return rtn;
  3301. }
  3302. static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
  3303. struct CommandControlBlock *poll_ccb)
  3304. {
  3305. struct MessageUnit_B *reg = acb->pmuB;
  3306. struct ARCMSR_CDB *arcmsr_cdb;
  3307. struct CommandControlBlock *ccb;
  3308. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  3309. int index, rtn;
  3310. bool error;
  3311. unsigned long ccb_cdb_phy;
  3312. polling_hbb_ccb_retry:
  3313. poll_count++;
  3314. /* clear doorbell interrupt */
  3315. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  3316. while(1){
  3317. index = reg->doneq_index;
  3318. flag_ccb = reg->done_qbuffer[index];
  3319. if (flag_ccb == 0) {
  3320. if (poll_ccb_done){
  3321. rtn = SUCCESS;
  3322. break;
  3323. }else {
  3324. msleep(25);
  3325. if (poll_count > 100){
  3326. rtn = FAILED;
  3327. break;
  3328. }
  3329. goto polling_hbb_ccb_retry;
  3330. }
  3331. }
  3332. reg->done_qbuffer[index] = 0;
  3333. index++;
  3334. /*if last index number set it to 0 */
  3335. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  3336. reg->doneq_index = index;
  3337. /* check if command done with no error*/
  3338. ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
  3339. if (acb->cdb_phyadd_hipart)
  3340. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  3341. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  3342. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  3343. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  3344. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  3345. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  3346. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  3347. " poll command abort successfully \n"
  3348. ,acb->host->host_no
  3349. ,ccb->pcmd->device->id
  3350. ,(u32)ccb->pcmd->device->lun
  3351. ,ccb);
  3352. ccb->pcmd->result = DID_ABORT << 16;
  3353. arcmsr_ccb_complete(ccb);
  3354. continue;
  3355. }
  3356. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  3357. " command done ccb = '0x%p'"
  3358. "ccboutstandingcount = %d \n"
  3359. , acb->host->host_no
  3360. , ccb
  3361. , atomic_read(&acb->ccboutstandingcount));
  3362. continue;
  3363. }
  3364. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  3365. arcmsr_report_ccb_state(acb, ccb, error);
  3366. }
  3367. return rtn;
  3368. }
  3369. static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
  3370. struct CommandControlBlock *poll_ccb)
  3371. {
  3372. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3373. uint32_t flag_ccb;
  3374. struct ARCMSR_CDB *arcmsr_cdb;
  3375. bool error;
  3376. struct CommandControlBlock *pCCB;
  3377. uint32_t poll_ccb_done = 0, poll_count = 0;
  3378. int rtn;
  3379. unsigned long ccb_cdb_phy;
  3380. polling_hbc_ccb_retry:
  3381. poll_count++;
  3382. while (1) {
  3383. if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
  3384. if (poll_ccb_done) {
  3385. rtn = SUCCESS;
  3386. break;
  3387. } else {
  3388. msleep(25);
  3389. if (poll_count > 100) {
  3390. rtn = FAILED;
  3391. break;
  3392. }
  3393. goto polling_hbc_ccb_retry;
  3394. }
  3395. }
  3396. flag_ccb = readl(&reg->outbound_queueport_low);
  3397. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  3398. if (acb->cdb_phyadd_hipart)
  3399. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  3400. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
  3401. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  3402. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  3403. /* check ifcommand done with no error*/
  3404. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  3405. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  3406. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  3407. " poll command abort successfully \n"
  3408. , acb->host->host_no
  3409. , pCCB->pcmd->device->id
  3410. , (u32)pCCB->pcmd->device->lun
  3411. , pCCB);
  3412. pCCB->pcmd->result = DID_ABORT << 16;
  3413. arcmsr_ccb_complete(pCCB);
  3414. continue;
  3415. }
  3416. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  3417. " command done ccb = '0x%p'"
  3418. "ccboutstandingcount = %d \n"
  3419. , acb->host->host_no
  3420. , pCCB
  3421. , atomic_read(&acb->ccboutstandingcount));
  3422. continue;
  3423. }
  3424. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  3425. arcmsr_report_ccb_state(acb, pCCB, error);
  3426. }
  3427. return rtn;
  3428. }
  3429. static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
  3430. struct CommandControlBlock *poll_ccb)
  3431. {
  3432. bool error;
  3433. uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb;
  3434. int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
  3435. unsigned long flags, ccb_cdb_phy;
  3436. struct ARCMSR_CDB *arcmsr_cdb;
  3437. struct CommandControlBlock *pCCB;
  3438. struct MessageUnit_D *pmu = acb->pmuD;
  3439. polling_hbaD_ccb_retry:
  3440. poll_count++;
  3441. while (1) {
  3442. spin_lock_irqsave(&acb->doneq_lock, flags);
  3443. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  3444. doneq_index = pmu->doneq_index;
  3445. if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
  3446. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3447. if (poll_ccb_done) {
  3448. rtn = SUCCESS;
  3449. break;
  3450. } else {
  3451. msleep(25);
  3452. if (poll_count > 40) {
  3453. rtn = FAILED;
  3454. break;
  3455. }
  3456. goto polling_hbaD_ccb_retry;
  3457. }
  3458. }
  3459. toggle = doneq_index & 0x4000;
  3460. index_stripped = (doneq_index & 0xFFF) + 1;
  3461. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  3462. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  3463. ((toggle ^ 0x4000) + 1);
  3464. doneq_index = pmu->doneq_index;
  3465. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3466. flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
  3467. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  3468. if (acb->cdb_phyadd_hipart)
  3469. ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
  3470. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
  3471. ccb_cdb_phy);
  3472. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
  3473. arcmsr_cdb);
  3474. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  3475. if ((pCCB->acb != acb) ||
  3476. (pCCB->startdone != ARCMSR_CCB_START)) {
  3477. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  3478. pr_notice("arcmsr%d: scsi id = %d "
  3479. "lun = %d ccb = '0x%p' poll command "
  3480. "abort successfully\n"
  3481. , acb->host->host_no
  3482. , pCCB->pcmd->device->id
  3483. , (u32)pCCB->pcmd->device->lun
  3484. , pCCB);
  3485. pCCB->pcmd->result = DID_ABORT << 16;
  3486. arcmsr_ccb_complete(pCCB);
  3487. continue;
  3488. }
  3489. pr_notice("arcmsr%d: polling an illegal "
  3490. "ccb command done ccb = '0x%p' "
  3491. "ccboutstandingcount = %d\n"
  3492. , acb->host->host_no
  3493. , pCCB
  3494. , atomic_read(&acb->ccboutstandingcount));
  3495. continue;
  3496. }
  3497. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  3498. ? true : false;
  3499. arcmsr_report_ccb_state(acb, pCCB, error);
  3500. }
  3501. return rtn;
  3502. }
  3503. static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb,
  3504. struct CommandControlBlock *poll_ccb)
  3505. {
  3506. bool error;
  3507. uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index;
  3508. uint16_t cmdSMID;
  3509. unsigned long flags;
  3510. int rtn;
  3511. struct CommandControlBlock *pCCB;
  3512. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3513. polling_hbaC_ccb_retry:
  3514. poll_count++;
  3515. while (1) {
  3516. spin_lock_irqsave(&acb->doneq_lock, flags);
  3517. doneq_index = acb->doneq_index;
  3518. if ((readl(&reg->reply_post_producer_index) & 0xFFFF) ==
  3519. doneq_index) {
  3520. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3521. if (poll_ccb_done) {
  3522. rtn = SUCCESS;
  3523. break;
  3524. } else {
  3525. msleep(25);
  3526. if (poll_count > 40) {
  3527. rtn = FAILED;
  3528. break;
  3529. }
  3530. goto polling_hbaC_ccb_retry;
  3531. }
  3532. }
  3533. cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
  3534. doneq_index++;
  3535. if (doneq_index >= acb->completionQ_entry)
  3536. doneq_index = 0;
  3537. acb->doneq_index = doneq_index;
  3538. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3539. pCCB = acb->pccb_pool[cmdSMID];
  3540. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  3541. /* check if command done with no error*/
  3542. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  3543. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  3544. pr_notice("arcmsr%d: scsi id = %d "
  3545. "lun = %d ccb = '0x%p' poll command "
  3546. "abort successfully\n"
  3547. , acb->host->host_no
  3548. , pCCB->pcmd->device->id
  3549. , (u32)pCCB->pcmd->device->lun
  3550. , pCCB);
  3551. pCCB->pcmd->result = DID_ABORT << 16;
  3552. arcmsr_ccb_complete(pCCB);
  3553. continue;
  3554. }
  3555. pr_notice("arcmsr%d: polling an illegal "
  3556. "ccb command done ccb = '0x%p' "
  3557. "ccboutstandingcount = %d\n"
  3558. , acb->host->host_no
  3559. , pCCB
  3560. , atomic_read(&acb->ccboutstandingcount));
  3561. continue;
  3562. }
  3563. error = (acb->pCompletionQ[doneq_index].cmdFlag &
  3564. ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  3565. arcmsr_report_ccb_state(acb, pCCB, error);
  3566. }
  3567. writel(doneq_index, &reg->reply_post_consumer_index);
  3568. return rtn;
  3569. }
  3570. static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  3571. struct CommandControlBlock *poll_ccb)
  3572. {
  3573. int rtn = 0;
  3574. switch (acb->adapter_type) {
  3575. case ACB_ADAPTER_TYPE_A:
  3576. rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
  3577. break;
  3578. case ACB_ADAPTER_TYPE_B:
  3579. rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
  3580. break;
  3581. case ACB_ADAPTER_TYPE_C:
  3582. rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
  3583. break;
  3584. case ACB_ADAPTER_TYPE_D:
  3585. rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
  3586. break;
  3587. case ACB_ADAPTER_TYPE_E:
  3588. case ACB_ADAPTER_TYPE_F:
  3589. rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb);
  3590. break;
  3591. }
  3592. return rtn;
  3593. }
  3594. static void arcmsr_set_iop_datetime(struct timer_list *t)
  3595. {
  3596. struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer);
  3597. unsigned int next_time;
  3598. struct tm tm;
  3599. union {
  3600. struct {
  3601. uint16_t signature;
  3602. uint8_t year;
  3603. uint8_t month;
  3604. uint8_t date;
  3605. uint8_t hour;
  3606. uint8_t minute;
  3607. uint8_t second;
  3608. } a;
  3609. struct {
  3610. uint32_t msg_time[2];
  3611. } b;
  3612. } datetime;
  3613. time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm);
  3614. datetime.a.signature = 0x55AA;
  3615. datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */
  3616. datetime.a.month = tm.tm_mon;
  3617. datetime.a.date = tm.tm_mday;
  3618. datetime.a.hour = tm.tm_hour;
  3619. datetime.a.minute = tm.tm_min;
  3620. datetime.a.second = tm.tm_sec;
  3621. switch (pacb->adapter_type) {
  3622. case ACB_ADAPTER_TYPE_A: {
  3623. struct MessageUnit_A __iomem *reg = pacb->pmuA;
  3624. writel(datetime.b.msg_time[0], &reg->message_rwbuffer[0]);
  3625. writel(datetime.b.msg_time[1], &reg->message_rwbuffer[1]);
  3626. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
  3627. break;
  3628. }
  3629. case ACB_ADAPTER_TYPE_B: {
  3630. uint32_t __iomem *rwbuffer;
  3631. struct MessageUnit_B *reg = pacb->pmuB;
  3632. rwbuffer = reg->message_rwbuffer;
  3633. writel(datetime.b.msg_time[0], rwbuffer++);
  3634. writel(datetime.b.msg_time[1], rwbuffer++);
  3635. writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
  3636. break;
  3637. }
  3638. case ACB_ADAPTER_TYPE_C: {
  3639. struct MessageUnit_C __iomem *reg = pacb->pmuC;
  3640. writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
  3641. writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
  3642. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
  3643. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3644. break;
  3645. }
  3646. case ACB_ADAPTER_TYPE_D: {
  3647. uint32_t __iomem *rwbuffer;
  3648. struct MessageUnit_D *reg = pacb->pmuD;
  3649. rwbuffer = reg->msgcode_rwbuffer;
  3650. writel(datetime.b.msg_time[0], rwbuffer++);
  3651. writel(datetime.b.msg_time[1], rwbuffer++);
  3652. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
  3653. break;
  3654. }
  3655. case ACB_ADAPTER_TYPE_E: {
  3656. struct MessageUnit_E __iomem *reg = pacb->pmuE;
  3657. writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
  3658. writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
  3659. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
  3660. pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3661. writel(pacb->out_doorbell, &reg->iobound_doorbell);
  3662. break;
  3663. }
  3664. case ACB_ADAPTER_TYPE_F: {
  3665. struct MessageUnit_F __iomem *reg = pacb->pmuF;
  3666. pacb->msgcode_rwbuffer[0] = datetime.b.msg_time[0];
  3667. pacb->msgcode_rwbuffer[1] = datetime.b.msg_time[1];
  3668. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
  3669. pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3670. writel(pacb->out_doorbell, &reg->iobound_doorbell);
  3671. break;
  3672. }
  3673. }
  3674. if (sys_tz.tz_minuteswest)
  3675. next_time = ARCMSR_HOURS;
  3676. else
  3677. next_time = ARCMSR_MINUTES;
  3678. mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time));
  3679. }
  3680. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  3681. {
  3682. uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
  3683. dma_addr_t dma_coherent_handle;
  3684. /*
  3685. ********************************************************************
  3686. ** here we need to tell iop 331 our freeccb.HighPart
  3687. ** if freeccb.HighPart is not zero
  3688. ********************************************************************
  3689. */
  3690. switch (acb->adapter_type) {
  3691. case ACB_ADAPTER_TYPE_B:
  3692. case ACB_ADAPTER_TYPE_D:
  3693. dma_coherent_handle = acb->dma_coherent_handle2;
  3694. break;
  3695. case ACB_ADAPTER_TYPE_E:
  3696. case ACB_ADAPTER_TYPE_F:
  3697. dma_coherent_handle = acb->dma_coherent_handle +
  3698. offsetof(struct CommandControlBlock, arcmsr_cdb);
  3699. break;
  3700. default:
  3701. dma_coherent_handle = acb->dma_coherent_handle;
  3702. break;
  3703. }
  3704. cdb_phyaddr = lower_32_bits(dma_coherent_handle);
  3705. cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
  3706. acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
  3707. acb->cdb_phyadd_hipart = ((uint64_t)cdb_phyaddr_hi32) << 32;
  3708. /*
  3709. ***********************************************************************
  3710. ** if adapter type B, set window of "post command Q"
  3711. ***********************************************************************
  3712. */
  3713. switch (acb->adapter_type) {
  3714. case ACB_ADAPTER_TYPE_A: {
  3715. if (cdb_phyaddr_hi32 != 0) {
  3716. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3717. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  3718. &reg->message_rwbuffer[0]);
  3719. writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  3720. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  3721. &reg->inbound_msgaddr0);
  3722. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3723. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  3724. part physical address timeout\n",
  3725. acb->host->host_no);
  3726. return 1;
  3727. }
  3728. }
  3729. }
  3730. break;
  3731. case ACB_ADAPTER_TYPE_B: {
  3732. uint32_t __iomem *rwbuffer;
  3733. struct MessageUnit_B *reg = acb->pmuB;
  3734. reg->postq_index = 0;
  3735. reg->doneq_index = 0;
  3736. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
  3737. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3738. printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
  3739. acb->host->host_no);
  3740. return 1;
  3741. }
  3742. rwbuffer = reg->message_rwbuffer;
  3743. /* driver "set config" signature */
  3744. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3745. /* normal should be zero */
  3746. writel(cdb_phyaddr_hi32, rwbuffer++);
  3747. /* postQ size (256 + 8)*4 */
  3748. writel(cdb_phyaddr, rwbuffer++);
  3749. /* doneQ size (256 + 8)*4 */
  3750. writel(cdb_phyaddr + 1056, rwbuffer++);
  3751. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  3752. writel(1056, rwbuffer);
  3753. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
  3754. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3755. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3756. timeout \n",acb->host->host_no);
  3757. return 1;
  3758. }
  3759. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  3760. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3761. pr_err("arcmsr%d: can't set driver mode.\n",
  3762. acb->host->host_no);
  3763. return 1;
  3764. }
  3765. }
  3766. break;
  3767. case ACB_ADAPTER_TYPE_C: {
  3768. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3769. printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
  3770. acb->adapter_index, cdb_phyaddr_hi32);
  3771. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  3772. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
  3773. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  3774. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3775. if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
  3776. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3777. timeout \n", acb->host->host_no);
  3778. return 1;
  3779. }
  3780. }
  3781. break;
  3782. case ACB_ADAPTER_TYPE_D: {
  3783. uint32_t __iomem *rwbuffer;
  3784. struct MessageUnit_D *reg = acb->pmuD;
  3785. reg->postq_index = 0;
  3786. reg->doneq_index = 0;
  3787. rwbuffer = reg->msgcode_rwbuffer;
  3788. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3789. writel(cdb_phyaddr_hi32, rwbuffer++);
  3790. writel(cdb_phyaddr, rwbuffer++);
  3791. writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
  3792. sizeof(struct InBound_SRB)), rwbuffer++);
  3793. writel(0x100, rwbuffer);
  3794. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
  3795. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  3796. pr_notice("arcmsr%d: 'set command Q window' timeout\n",
  3797. acb->host->host_no);
  3798. return 1;
  3799. }
  3800. }
  3801. break;
  3802. case ACB_ADAPTER_TYPE_E: {
  3803. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3804. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  3805. writel(ARCMSR_SIGNATURE_1884, &reg->msgcode_rwbuffer[1]);
  3806. writel(cdb_phyaddr, &reg->msgcode_rwbuffer[2]);
  3807. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[3]);
  3808. writel(acb->ccbsize, &reg->msgcode_rwbuffer[4]);
  3809. writel(lower_32_bits(acb->dma_coherent_handle2), &reg->msgcode_rwbuffer[5]);
  3810. writel(upper_32_bits(acb->dma_coherent_handle2), &reg->msgcode_rwbuffer[6]);
  3811. writel(acb->ioqueue_size, &reg->msgcode_rwbuffer[7]);
  3812. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  3813. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3814. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3815. if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
  3816. pr_notice("arcmsr%d: 'set command Q window' timeout \n",
  3817. acb->host->host_no);
  3818. return 1;
  3819. }
  3820. }
  3821. break;
  3822. case ACB_ADAPTER_TYPE_F: {
  3823. struct MessageUnit_F __iomem *reg = acb->pmuF;
  3824. acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
  3825. acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
  3826. acb->msgcode_rwbuffer[2] = cdb_phyaddr;
  3827. acb->msgcode_rwbuffer[3] = cdb_phyaddr_hi32;
  3828. acb->msgcode_rwbuffer[4] = acb->ccbsize;
  3829. acb->msgcode_rwbuffer[5] = lower_32_bits(acb->dma_coherent_handle2);
  3830. acb->msgcode_rwbuffer[6] = upper_32_bits(acb->dma_coherent_handle2);
  3831. acb->msgcode_rwbuffer[7] = acb->completeQ_size;
  3832. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  3833. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3834. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3835. if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
  3836. pr_notice("arcmsr%d: 'set command Q window' timeout\n",
  3837. acb->host->host_no);
  3838. return 1;
  3839. }
  3840. }
  3841. break;
  3842. }
  3843. return 0;
  3844. }
  3845. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  3846. {
  3847. uint32_t firmware_state = 0;
  3848. switch (acb->adapter_type) {
  3849. case ACB_ADAPTER_TYPE_A: {
  3850. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3851. do {
  3852. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3853. msleep(20);
  3854. firmware_state = readl(&reg->outbound_msgaddr1);
  3855. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  3856. }
  3857. break;
  3858. case ACB_ADAPTER_TYPE_B: {
  3859. struct MessageUnit_B *reg = acb->pmuB;
  3860. do {
  3861. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3862. msleep(20);
  3863. firmware_state = readl(reg->iop2drv_doorbell);
  3864. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  3865. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  3866. }
  3867. break;
  3868. case ACB_ADAPTER_TYPE_C: {
  3869. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3870. do {
  3871. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3872. msleep(20);
  3873. firmware_state = readl(&reg->outbound_msgaddr1);
  3874. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  3875. }
  3876. break;
  3877. case ACB_ADAPTER_TYPE_D: {
  3878. struct MessageUnit_D *reg = acb->pmuD;
  3879. do {
  3880. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3881. msleep(20);
  3882. firmware_state = readl(reg->outbound_msgaddr1);
  3883. } while ((firmware_state &
  3884. ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
  3885. }
  3886. break;
  3887. case ACB_ADAPTER_TYPE_E:
  3888. case ACB_ADAPTER_TYPE_F: {
  3889. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3890. do {
  3891. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3892. msleep(20);
  3893. firmware_state = readl(&reg->outbound_msgaddr1);
  3894. } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0);
  3895. }
  3896. break;
  3897. }
  3898. }
  3899. static void arcmsr_request_device_map(struct timer_list *t)
  3900. {
  3901. struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer);
  3902. if (acb->acb_flags & (ACB_F_MSG_GET_CONFIG | ACB_F_BUS_RESET | ACB_F_ABORT)) {
  3903. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3904. } else {
  3905. acb->fw_flag = FW_NORMAL;
  3906. switch (acb->adapter_type) {
  3907. case ACB_ADAPTER_TYPE_A: {
  3908. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3909. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3910. break;
  3911. }
  3912. case ACB_ADAPTER_TYPE_B: {
  3913. struct MessageUnit_B *reg = acb->pmuB;
  3914. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  3915. break;
  3916. }
  3917. case ACB_ADAPTER_TYPE_C: {
  3918. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3919. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3920. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3921. break;
  3922. }
  3923. case ACB_ADAPTER_TYPE_D: {
  3924. struct MessageUnit_D *reg = acb->pmuD;
  3925. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
  3926. break;
  3927. }
  3928. case ACB_ADAPTER_TYPE_E: {
  3929. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3930. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3931. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3932. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3933. break;
  3934. }
  3935. case ACB_ADAPTER_TYPE_F: {
  3936. struct MessageUnit_F __iomem *reg = acb->pmuF;
  3937. uint32_t outMsg1 = readl(&reg->outbound_msgaddr1);
  3938. if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
  3939. (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
  3940. goto nxt6s;
  3941. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3942. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3943. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3944. break;
  3945. }
  3946. default:
  3947. return;
  3948. }
  3949. acb->acb_flags |= ACB_F_MSG_GET_CONFIG;
  3950. nxt6s:
  3951. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3952. }
  3953. }
  3954. static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
  3955. {
  3956. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3957. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3958. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  3959. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3960. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3961. rebuild' timeout \n", acb->host->host_no);
  3962. }
  3963. }
  3964. static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
  3965. {
  3966. struct MessageUnit_B *reg = acb->pmuB;
  3967. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3968. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
  3969. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3970. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3971. rebuild' timeout \n",acb->host->host_no);
  3972. }
  3973. }
  3974. static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
  3975. {
  3976. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  3977. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3978. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
  3979. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
  3980. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  3981. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3982. rebuild' timeout \n", pACB->host->host_no);
  3983. }
  3984. return;
  3985. }
  3986. static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
  3987. {
  3988. struct MessageUnit_D *pmu = pACB->pmuD;
  3989. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3990. writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
  3991. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  3992. pr_notice("arcmsr%d: wait 'start adapter "
  3993. "background rebuild' timeout\n", pACB->host->host_no);
  3994. }
  3995. }
  3996. static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB)
  3997. {
  3998. struct MessageUnit_E __iomem *pmu = pACB->pmuE;
  3999. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  4000. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
  4001. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  4002. writel(pACB->out_doorbell, &pmu->iobound_doorbell);
  4003. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  4004. pr_notice("arcmsr%d: wait 'start adapter "
  4005. "background rebuild' timeout \n", pACB->host->host_no);
  4006. }
  4007. }
  4008. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  4009. {
  4010. switch (acb->adapter_type) {
  4011. case ACB_ADAPTER_TYPE_A:
  4012. arcmsr_hbaA_start_bgrb(acb);
  4013. break;
  4014. case ACB_ADAPTER_TYPE_B:
  4015. arcmsr_hbaB_start_bgrb(acb);
  4016. break;
  4017. case ACB_ADAPTER_TYPE_C:
  4018. arcmsr_hbaC_start_bgrb(acb);
  4019. break;
  4020. case ACB_ADAPTER_TYPE_D:
  4021. arcmsr_hbaD_start_bgrb(acb);
  4022. break;
  4023. case ACB_ADAPTER_TYPE_E:
  4024. case ACB_ADAPTER_TYPE_F:
  4025. arcmsr_hbaE_start_bgrb(acb);
  4026. break;
  4027. }
  4028. }
  4029. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  4030. {
  4031. switch (acb->adapter_type) {
  4032. case ACB_ADAPTER_TYPE_A: {
  4033. struct MessageUnit_A __iomem *reg = acb->pmuA;
  4034. uint32_t outbound_doorbell;
  4035. /* empty doorbell Qbuffer if door bell ringed */
  4036. outbound_doorbell = readl(&reg->outbound_doorbell);
  4037. /*clear doorbell interrupt */
  4038. writel(outbound_doorbell, &reg->outbound_doorbell);
  4039. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  4040. }
  4041. break;
  4042. case ACB_ADAPTER_TYPE_B: {
  4043. struct MessageUnit_B *reg = acb->pmuB;
  4044. uint32_t outbound_doorbell, i;
  4045. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  4046. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  4047. /* let IOP know data has been read */
  4048. for(i=0; i < 200; i++) {
  4049. msleep(20);
  4050. outbound_doorbell = readl(reg->iop2drv_doorbell);
  4051. if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  4052. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  4053. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  4054. } else
  4055. break;
  4056. }
  4057. }
  4058. break;
  4059. case ACB_ADAPTER_TYPE_C: {
  4060. struct MessageUnit_C __iomem *reg = acb->pmuC;
  4061. uint32_t outbound_doorbell, i;
  4062. /* empty doorbell Qbuffer if door bell ringed */
  4063. outbound_doorbell = readl(&reg->outbound_doorbell);
  4064. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  4065. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  4066. for (i = 0; i < 200; i++) {
  4067. msleep(20);
  4068. outbound_doorbell = readl(&reg->outbound_doorbell);
  4069. if (outbound_doorbell &
  4070. ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
  4071. writel(outbound_doorbell,
  4072. &reg->outbound_doorbell_clear);
  4073. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
  4074. &reg->inbound_doorbell);
  4075. } else
  4076. break;
  4077. }
  4078. }
  4079. break;
  4080. case ACB_ADAPTER_TYPE_D: {
  4081. struct MessageUnit_D *reg = acb->pmuD;
  4082. uint32_t outbound_doorbell, i;
  4083. /* empty doorbell Qbuffer if door bell ringed */
  4084. outbound_doorbell = readl(reg->outbound_doorbell);
  4085. writel(outbound_doorbell, reg->outbound_doorbell);
  4086. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  4087. reg->inbound_doorbell);
  4088. for (i = 0; i < 200; i++) {
  4089. msleep(20);
  4090. outbound_doorbell = readl(reg->outbound_doorbell);
  4091. if (outbound_doorbell &
  4092. ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
  4093. writel(outbound_doorbell,
  4094. reg->outbound_doorbell);
  4095. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  4096. reg->inbound_doorbell);
  4097. } else
  4098. break;
  4099. }
  4100. }
  4101. break;
  4102. case ACB_ADAPTER_TYPE_E:
  4103. case ACB_ADAPTER_TYPE_F: {
  4104. struct MessageUnit_E __iomem *reg = acb->pmuE;
  4105. uint32_t i, tmp;
  4106. acb->in_doorbell = readl(&reg->iobound_doorbell);
  4107. writel(0, &reg->host_int_status); /*clear interrupt*/
  4108. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
  4109. writel(acb->out_doorbell, &reg->iobound_doorbell);
  4110. for(i=0; i < 200; i++) {
  4111. msleep(20);
  4112. tmp = acb->in_doorbell;
  4113. acb->in_doorbell = readl(&reg->iobound_doorbell);
  4114. if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
  4115. writel(0, &reg->host_int_status); /*clear interrupt*/
  4116. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
  4117. writel(acb->out_doorbell, &reg->iobound_doorbell);
  4118. } else
  4119. break;
  4120. }
  4121. }
  4122. break;
  4123. }
  4124. }
  4125. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  4126. {
  4127. switch (acb->adapter_type) {
  4128. case ACB_ADAPTER_TYPE_A:
  4129. return;
  4130. case ACB_ADAPTER_TYPE_B:
  4131. {
  4132. struct MessageUnit_B *reg = acb->pmuB;
  4133. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
  4134. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  4135. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  4136. return;
  4137. }
  4138. }
  4139. break;
  4140. case ACB_ADAPTER_TYPE_C:
  4141. return;
  4142. }
  4143. return;
  4144. }
  4145. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
  4146. {
  4147. uint8_t value[64];
  4148. int i, count = 0;
  4149. struct MessageUnit_A __iomem *pmuA = acb->pmuA;
  4150. struct MessageUnit_C __iomem *pmuC = acb->pmuC;
  4151. struct MessageUnit_D *pmuD = acb->pmuD;
  4152. /* backup pci config data */
  4153. printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
  4154. for (i = 0; i < 64; i++) {
  4155. pci_read_config_byte(acb->pdev, i, &value[i]);
  4156. }
  4157. /* hardware reset signal */
  4158. if (acb->dev_id == 0x1680) {
  4159. writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
  4160. } else if (acb->dev_id == 0x1880) {
  4161. do {
  4162. count++;
  4163. writel(0xF, &pmuC->write_sequence);
  4164. writel(0x4, &pmuC->write_sequence);
  4165. writel(0xB, &pmuC->write_sequence);
  4166. writel(0x2, &pmuC->write_sequence);
  4167. writel(0x7, &pmuC->write_sequence);
  4168. writel(0xD, &pmuC->write_sequence);
  4169. } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
  4170. writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
  4171. } else if (acb->dev_id == 0x1884) {
  4172. struct MessageUnit_E __iomem *pmuE = acb->pmuE;
  4173. do {
  4174. count++;
  4175. writel(0x4, &pmuE->write_sequence_3xxx);
  4176. writel(0xB, &pmuE->write_sequence_3xxx);
  4177. writel(0x2, &pmuE->write_sequence_3xxx);
  4178. writel(0x7, &pmuE->write_sequence_3xxx);
  4179. writel(0xD, &pmuE->write_sequence_3xxx);
  4180. mdelay(10);
  4181. } while (((readl(&pmuE->host_diagnostic_3xxx) &
  4182. ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5));
  4183. writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
  4184. } else if (acb->dev_id == 0x1214) {
  4185. writel(0x20, pmuD->reset_request);
  4186. } else {
  4187. pci_write_config_byte(acb->pdev, 0x84, 0x20);
  4188. }
  4189. msleep(2000);
  4190. /* write back pci config data */
  4191. for (i = 0; i < 64; i++) {
  4192. pci_write_config_byte(acb->pdev, i, value[i]);
  4193. }
  4194. msleep(1000);
  4195. return;
  4196. }
  4197. static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb)
  4198. {
  4199. bool rtn = true;
  4200. switch(acb->adapter_type) {
  4201. case ACB_ADAPTER_TYPE_A:{
  4202. struct MessageUnit_A __iomem *reg = acb->pmuA;
  4203. rtn = ((readl(&reg->outbound_msgaddr1) &
  4204. ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false;
  4205. }
  4206. break;
  4207. case ACB_ADAPTER_TYPE_B:{
  4208. struct MessageUnit_B *reg = acb->pmuB;
  4209. rtn = ((readl(reg->iop2drv_doorbell) &
  4210. ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false;
  4211. }
  4212. break;
  4213. case ACB_ADAPTER_TYPE_C:{
  4214. struct MessageUnit_C __iomem *reg = acb->pmuC;
  4215. rtn = (readl(&reg->host_diagnostic) & 0x04) ? true : false;
  4216. }
  4217. break;
  4218. case ACB_ADAPTER_TYPE_D:{
  4219. struct MessageUnit_D *reg = acb->pmuD;
  4220. rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ?
  4221. true : false;
  4222. }
  4223. break;
  4224. case ACB_ADAPTER_TYPE_E:
  4225. case ACB_ADAPTER_TYPE_F:{
  4226. struct MessageUnit_E __iomem *reg = acb->pmuE;
  4227. rtn = (readl(&reg->host_diagnostic_3xxx) &
  4228. ARCMSR_ARC188X_RESET_ADAPTER) ? true : false;
  4229. }
  4230. break;
  4231. }
  4232. return rtn;
  4233. }
  4234. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  4235. {
  4236. uint32_t intmask_org;
  4237. /* disable all outbound interrupt */
  4238. intmask_org = arcmsr_disable_outbound_ints(acb);
  4239. arcmsr_wait_firmware_ready(acb);
  4240. arcmsr_iop_confirm(acb);
  4241. /*start background rebuild*/
  4242. arcmsr_start_adapter_bgrb(acb);
  4243. /* empty doorbell Qbuffer if door bell ringed */
  4244. arcmsr_clear_doorbell_queue_buffer(acb);
  4245. arcmsr_enable_eoi_mode(acb);
  4246. /* enable outbound Post Queue,outbound doorbell Interrupt */
  4247. arcmsr_enable_outbound_ints(acb, intmask_org);
  4248. acb->acb_flags |= ACB_F_IOP_INITED;
  4249. }
  4250. static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
  4251. {
  4252. struct CommandControlBlock *ccb;
  4253. uint32_t intmask_org;
  4254. uint8_t rtnval = 0x00;
  4255. int i = 0;
  4256. unsigned long flags;
  4257. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  4258. /* disable all outbound interrupt */
  4259. intmask_org = arcmsr_disable_outbound_ints(acb);
  4260. /* talk to iop 331 outstanding command aborted */
  4261. rtnval = arcmsr_abort_allcmd(acb);
  4262. /* clear all outbound posted Q */
  4263. arcmsr_done4abort_postqueue(acb);
  4264. for (i = 0; i < acb->maxFreeCCB; i++) {
  4265. ccb = acb->pccb_pool[i];
  4266. if (ccb->startdone == ARCMSR_CCB_START) {
  4267. scsi_dma_unmap(ccb->pcmd);
  4268. ccb->startdone = ARCMSR_CCB_DONE;
  4269. ccb->ccb_flags = 0;
  4270. spin_lock_irqsave(&acb->ccblist_lock, flags);
  4271. list_add_tail(&ccb->list, &acb->ccb_free_list);
  4272. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  4273. }
  4274. }
  4275. atomic_set(&acb->ccboutstandingcount, 0);
  4276. /* enable all outbound interrupt */
  4277. arcmsr_enable_outbound_ints(acb, intmask_org);
  4278. return rtnval;
  4279. }
  4280. return rtnval;
  4281. }
  4282. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  4283. {
  4284. struct AdapterControlBlock *acb;
  4285. int retry_count = 0;
  4286. int rtn = FAILED;
  4287. acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
  4288. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
  4289. return SUCCESS;
  4290. pr_notice("arcmsr: executing bus reset eh.....num_resets = %d,"
  4291. " num_aborts = %d \n", acb->num_resets, acb->num_aborts);
  4292. acb->num_resets++;
  4293. if (acb->acb_flags & ACB_F_BUS_RESET) {
  4294. long timeout;
  4295. pr_notice("arcmsr: there is a bus reset eh proceeding...\n");
  4296. timeout = wait_event_timeout(wait_q, (acb->acb_flags
  4297. & ACB_F_BUS_RESET) == 0, 220 * HZ);
  4298. if (timeout)
  4299. return SUCCESS;
  4300. }
  4301. acb->acb_flags |= ACB_F_BUS_RESET;
  4302. if (!arcmsr_iop_reset(acb)) {
  4303. arcmsr_hardware_reset(acb);
  4304. acb->acb_flags &= ~ACB_F_IOP_INITED;
  4305. wait_reset_done:
  4306. ssleep(ARCMSR_SLEEPTIME);
  4307. if (arcmsr_reset_in_progress(acb)) {
  4308. if (retry_count > ARCMSR_RETRYCOUNT) {
  4309. acb->fw_flag = FW_DEADLOCK;
  4310. pr_notice("arcmsr%d: waiting for hw bus reset"
  4311. " return, RETRY TERMINATED!!\n",
  4312. acb->host->host_no);
  4313. return FAILED;
  4314. }
  4315. retry_count++;
  4316. goto wait_reset_done;
  4317. }
  4318. arcmsr_iop_init(acb);
  4319. acb->fw_flag = FW_NORMAL;
  4320. mod_timer(&acb->eternal_timer, jiffies +
  4321. msecs_to_jiffies(6 * HZ));
  4322. acb->acb_flags &= ~ACB_F_BUS_RESET;
  4323. rtn = SUCCESS;
  4324. pr_notice("arcmsr: scsi bus reset eh returns with success\n");
  4325. } else {
  4326. acb->acb_flags &= ~ACB_F_BUS_RESET;
  4327. acb->fw_flag = FW_NORMAL;
  4328. mod_timer(&acb->eternal_timer, jiffies +
  4329. msecs_to_jiffies(6 * HZ));
  4330. rtn = SUCCESS;
  4331. }
  4332. return rtn;
  4333. }
  4334. static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  4335. struct CommandControlBlock *ccb)
  4336. {
  4337. int rtn;
  4338. rtn = arcmsr_polling_ccbdone(acb, ccb);
  4339. return rtn;
  4340. }
  4341. static int arcmsr_abort(struct scsi_cmnd *cmd)
  4342. {
  4343. struct AdapterControlBlock *acb =
  4344. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  4345. int i = 0;
  4346. int rtn = FAILED;
  4347. uint32_t intmask_org;
  4348. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
  4349. return SUCCESS;
  4350. printk(KERN_NOTICE
  4351. "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
  4352. acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
  4353. acb->acb_flags |= ACB_F_ABORT;
  4354. acb->num_aborts++;
  4355. /*
  4356. ************************************************
  4357. ** the all interrupt service routine is locked
  4358. ** we need to handle it as soon as possible and exit
  4359. ************************************************
  4360. */
  4361. if (!atomic_read(&acb->ccboutstandingcount)) {
  4362. acb->acb_flags &= ~ACB_F_ABORT;
  4363. return rtn;
  4364. }
  4365. intmask_org = arcmsr_disable_outbound_ints(acb);
  4366. for (i = 0; i < acb->maxFreeCCB; i++) {
  4367. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  4368. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  4369. ccb->startdone = ARCMSR_CCB_ABORTED;
  4370. rtn = arcmsr_abort_one_cmd(acb, ccb);
  4371. break;
  4372. }
  4373. }
  4374. acb->acb_flags &= ~ACB_F_ABORT;
  4375. arcmsr_enable_outbound_ints(acb, intmask_org);
  4376. return rtn;
  4377. }
  4378. static const char *arcmsr_info(struct Scsi_Host *host)
  4379. {
  4380. struct AdapterControlBlock *acb =
  4381. (struct AdapterControlBlock *) host->hostdata;
  4382. static char buf[256];
  4383. char *type;
  4384. int raid6 = 1;
  4385. switch (acb->pdev->device) {
  4386. case PCI_DEVICE_ID_ARECA_1110:
  4387. case PCI_DEVICE_ID_ARECA_1200:
  4388. case PCI_DEVICE_ID_ARECA_1202:
  4389. case PCI_DEVICE_ID_ARECA_1210:
  4390. raid6 = 0;
  4391. fallthrough;
  4392. case PCI_DEVICE_ID_ARECA_1120:
  4393. case PCI_DEVICE_ID_ARECA_1130:
  4394. case PCI_DEVICE_ID_ARECA_1160:
  4395. case PCI_DEVICE_ID_ARECA_1170:
  4396. case PCI_DEVICE_ID_ARECA_1201:
  4397. case PCI_DEVICE_ID_ARECA_1203:
  4398. case PCI_DEVICE_ID_ARECA_1220:
  4399. case PCI_DEVICE_ID_ARECA_1230:
  4400. case PCI_DEVICE_ID_ARECA_1260:
  4401. case PCI_DEVICE_ID_ARECA_1270:
  4402. case PCI_DEVICE_ID_ARECA_1280:
  4403. type = "SATA";
  4404. break;
  4405. case PCI_DEVICE_ID_ARECA_1214:
  4406. case PCI_DEVICE_ID_ARECA_1380:
  4407. case PCI_DEVICE_ID_ARECA_1381:
  4408. case PCI_DEVICE_ID_ARECA_1680:
  4409. case PCI_DEVICE_ID_ARECA_1681:
  4410. case PCI_DEVICE_ID_ARECA_1880:
  4411. case PCI_DEVICE_ID_ARECA_1884:
  4412. type = "SAS/SATA";
  4413. break;
  4414. case PCI_DEVICE_ID_ARECA_1886:
  4415. type = "NVMe/SAS/SATA";
  4416. break;
  4417. default:
  4418. type = "unknown";
  4419. raid6 = 0;
  4420. break;
  4421. }
  4422. sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
  4423. type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
  4424. return buf;
  4425. }