reset-socfpga.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018, Intel Corporation
  4. * Copied from reset-sunxi.c
  5. */
  6. #include <linux/err.h>
  7. #include <linux/io.h>
  8. #include <linux/init.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/reset-controller.h>
  13. #include <linux/reset/reset-simple.h>
  14. #include <linux/reset/socfpga.h>
  15. #include <linux/slab.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/types.h>
  18. #define SOCFPGA_NR_BANKS 8
  19. static int a10_reset_init(struct device_node *np)
  20. {
  21. struct reset_simple_data *data;
  22. struct resource res;
  23. resource_size_t size;
  24. int ret;
  25. u32 reg_offset = 0x10;
  26. data = kzalloc(sizeof(*data), GFP_KERNEL);
  27. if (!data)
  28. return -ENOMEM;
  29. ret = of_address_to_resource(np, 0, &res);
  30. if (ret)
  31. goto err_alloc;
  32. size = resource_size(&res);
  33. if (!request_mem_region(res.start, size, np->name)) {
  34. ret = -EBUSY;
  35. goto err_alloc;
  36. }
  37. data->membase = ioremap(res.start, size);
  38. if (!data->membase) {
  39. ret = -ENOMEM;
  40. goto release_region;
  41. }
  42. if (of_property_read_u32(np, "altr,modrst-offset", &reg_offset))
  43. pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
  44. data->membase += reg_offset;
  45. spin_lock_init(&data->lock);
  46. data->rcdev.owner = THIS_MODULE;
  47. data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
  48. data->rcdev.ops = &reset_simple_ops;
  49. data->rcdev.of_node = np;
  50. data->status_active_low = true;
  51. ret = reset_controller_register(&data->rcdev);
  52. if (ret)
  53. pr_err("unable to register device\n");
  54. return ret;
  55. release_region:
  56. release_mem_region(res.start, size);
  57. err_alloc:
  58. kfree(data);
  59. return ret;
  60. };
  61. /*
  62. * These are the reset controller we need to initialize early on in
  63. * our system, before we can even think of using a regular device
  64. * driver for it.
  65. * The controllers that we can register through the regular device
  66. * model are handled by the simple reset driver directly.
  67. */
  68. static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
  69. { .compatible = "altr,rst-mgr", },
  70. { /* sentinel */ },
  71. };
  72. void __init socfpga_reset_init(void)
  73. {
  74. struct device_node *np;
  75. for_each_matching_node(np, socfpga_early_reset_dt_ids)
  76. a10_reset_init(np);
  77. }
  78. /*
  79. * The early driver is problematic, because it doesn't register
  80. * itself as a driver. This causes certain device links to prevent
  81. * consumer devices from probing. The hacky solution is to register
  82. * an empty driver, whose only job is to attach itself to the reset
  83. * manager and call probe.
  84. */
  85. static const struct of_device_id socfpga_reset_dt_ids[] = {
  86. { .compatible = "altr,rst-mgr", },
  87. { /* sentinel */ },
  88. };
  89. static int reset_simple_probe(struct platform_device *pdev)
  90. {
  91. return 0;
  92. }
  93. static struct platform_driver reset_socfpga_driver = {
  94. .probe = reset_simple_probe,
  95. .driver = {
  96. .name = "socfpga-reset",
  97. .of_match_table = socfpga_reset_dt_ids,
  98. },
  99. };
  100. builtin_platform_driver(reset_socfpga_driver);