reset-qcom-pdc.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/of_device.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/regmap.h>
  9. #include <linux/reset-controller.h>
  10. #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  11. #define RPMH_SDM845_PDC_SYNC_RESET 0x100
  12. #define RPMH_SC7280_PDC_SYNC_RESET 0x1000
  13. struct qcom_pdc_reset_map {
  14. u8 bit;
  15. };
  16. struct qcom_pdc_reset_desc {
  17. const struct qcom_pdc_reset_map *resets;
  18. size_t num_resets;
  19. unsigned int offset;
  20. };
  21. struct qcom_pdc_reset_data {
  22. struct reset_controller_dev rcdev;
  23. struct regmap *regmap;
  24. const struct qcom_pdc_reset_desc *desc;
  25. };
  26. static const struct regmap_config pdc_regmap_config = {
  27. .name = "pdc-reset",
  28. .reg_bits = 32,
  29. .reg_stride = 4,
  30. .val_bits = 32,
  31. .max_register = 0x20000,
  32. .fast_io = true,
  33. };
  34. static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
  35. [PDC_APPS_SYNC_RESET] = {0},
  36. [PDC_SP_SYNC_RESET] = {1},
  37. [PDC_AUDIO_SYNC_RESET] = {2},
  38. [PDC_SENSORS_SYNC_RESET] = {3},
  39. [PDC_AOP_SYNC_RESET] = {4},
  40. [PDC_DEBUG_SYNC_RESET] = {5},
  41. [PDC_GPU_SYNC_RESET] = {6},
  42. [PDC_DISPLAY_SYNC_RESET] = {7},
  43. [PDC_COMPUTE_SYNC_RESET] = {8},
  44. [PDC_MODEM_SYNC_RESET] = {9},
  45. };
  46. static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
  47. .resets = sdm845_pdc_resets,
  48. .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
  49. .offset = RPMH_SDM845_PDC_SYNC_RESET,
  50. };
  51. static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = {
  52. [PDC_APPS_SYNC_RESET] = {0},
  53. [PDC_SP_SYNC_RESET] = {1},
  54. [PDC_AUDIO_SYNC_RESET] = {2},
  55. [PDC_SENSORS_SYNC_RESET] = {3},
  56. [PDC_AOP_SYNC_RESET] = {4},
  57. [PDC_DEBUG_SYNC_RESET] = {5},
  58. [PDC_GPU_SYNC_RESET] = {6},
  59. [PDC_DISPLAY_SYNC_RESET] = {7},
  60. [PDC_COMPUTE_SYNC_RESET] = {8},
  61. [PDC_MODEM_SYNC_RESET] = {9},
  62. [PDC_WLAN_RF_SYNC_RESET] = {10},
  63. [PDC_WPSS_SYNC_RESET] = {11},
  64. };
  65. static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
  66. .resets = sc7280_pdc_resets,
  67. .num_resets = ARRAY_SIZE(sc7280_pdc_resets),
  68. .offset = RPMH_SC7280_PDC_SYNC_RESET,
  69. };
  70. static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
  71. struct reset_controller_dev *rcdev)
  72. {
  73. return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
  74. }
  75. static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
  76. unsigned long idx)
  77. {
  78. struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
  79. u32 mask = BIT(data->desc->resets[idx].bit);
  80. return regmap_update_bits(data->regmap, data->desc->offset, mask, mask);
  81. }
  82. static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
  83. unsigned long idx)
  84. {
  85. struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
  86. u32 mask = BIT(data->desc->resets[idx].bit);
  87. return regmap_update_bits(data->regmap, data->desc->offset, mask, 0);
  88. }
  89. static const struct reset_control_ops qcom_pdc_reset_ops = {
  90. .assert = qcom_pdc_control_assert,
  91. .deassert = qcom_pdc_control_deassert,
  92. };
  93. static int qcom_pdc_reset_probe(struct platform_device *pdev)
  94. {
  95. const struct qcom_pdc_reset_desc *desc;
  96. struct qcom_pdc_reset_data *data;
  97. struct device *dev = &pdev->dev;
  98. void __iomem *base;
  99. struct resource *res;
  100. desc = device_get_match_data(&pdev->dev);
  101. if (!desc)
  102. return -EINVAL;
  103. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  104. if (!data)
  105. return -ENOMEM;
  106. data->desc = desc;
  107. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  108. base = devm_ioremap_resource(dev, res);
  109. if (IS_ERR(base))
  110. return PTR_ERR(base);
  111. data->regmap = devm_regmap_init_mmio(dev, base, &pdc_regmap_config);
  112. if (IS_ERR(data->regmap)) {
  113. dev_err(dev, "Unable to initialize regmap\n");
  114. return PTR_ERR(data->regmap);
  115. }
  116. data->rcdev.owner = THIS_MODULE;
  117. data->rcdev.ops = &qcom_pdc_reset_ops;
  118. data->rcdev.nr_resets = desc->num_resets;
  119. data->rcdev.of_node = dev->of_node;
  120. return devm_reset_controller_register(dev, &data->rcdev);
  121. }
  122. static const struct of_device_id qcom_pdc_reset_of_match[] = {
  123. { .compatible = "qcom,sc7280-pdc-global", .data = &sc7280_pdc_reset_desc },
  124. { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_reset_desc },
  125. {}
  126. };
  127. MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
  128. static struct platform_driver qcom_pdc_reset_driver = {
  129. .probe = qcom_pdc_reset_probe,
  130. .driver = {
  131. .name = "qcom_pdc_reset",
  132. .of_match_table = qcom_pdc_reset_of_match,
  133. },
  134. };
  135. module_platform_driver(qcom_pdc_reset_driver);
  136. MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
  137. MODULE_LICENSE("GPL v2");