Kconfig 10 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. config ARCH_HAS_RESET_CONTROLLER
  3. bool
  4. menuconfig RESET_CONTROLLER
  5. bool "Reset Controller Support"
  6. default y if ARCH_HAS_RESET_CONTROLLER
  7. help
  8. Generic Reset Controller support.
  9. This framework is designed to abstract reset handling of devices
  10. via GPIOs or SoC-internal reset controller modules.
  11. If unsure, say no.
  12. if RESET_CONTROLLER
  13. config RESET_A10SR
  14. tristate "Altera Arria10 System Resource Reset"
  15. depends on MFD_ALTERA_A10SR || COMPILE_TEST
  16. help
  17. This option enables support for the external reset functions for
  18. peripheral PHYs on the Altera Arria10 System Resource Chip.
  19. config RESET_ATH79
  20. bool "AR71xx Reset Driver" if COMPILE_TEST
  21. default ATH79
  22. help
  23. This enables the ATH79 reset controller driver that supports the
  24. AR71xx SoC reset controller.
  25. config RESET_AXS10X
  26. bool "AXS10x Reset Driver" if COMPILE_TEST
  27. default ARC_PLAT_AXS10X
  28. help
  29. This enables the reset controller driver for AXS10x.
  30. config RESET_BCM6345
  31. bool "BCM6345 Reset Controller"
  32. depends on BMIPS_GENERIC || COMPILE_TEST
  33. default BMIPS_GENERIC
  34. help
  35. This enables the reset controller driver for BCM6345 SoCs.
  36. config RESET_BERLIN
  37. tristate "Berlin Reset Driver"
  38. depends on ARCH_BERLIN || COMPILE_TEST
  39. default m if ARCH_BERLIN
  40. help
  41. This enables the reset controller driver for Marvell Berlin SoCs.
  42. config RESET_BRCMSTB
  43. tristate "Broadcom STB reset controller"
  44. depends on ARCH_BRCMSTB || COMPILE_TEST
  45. default ARCH_BRCMSTB
  46. help
  47. This enables the reset controller driver for Broadcom STB SoCs using
  48. a SUN_TOP_CTRL_SW_INIT style controller.
  49. config RESET_BRCMSTB_RESCAL
  50. tristate "Broadcom STB RESCAL reset controller"
  51. depends on HAS_IOMEM
  52. depends on ARCH_BRCMSTB || COMPILE_TEST
  53. default ARCH_BRCMSTB
  54. help
  55. This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
  56. BCM7216.
  57. config RESET_HSDK
  58. bool "Synopsys HSDK Reset Driver"
  59. depends on HAS_IOMEM
  60. depends on ARC_SOC_HSDK || COMPILE_TEST
  61. help
  62. This enables the reset controller driver for HSDK board.
  63. config RESET_IMX7
  64. tristate "i.MX7/8 Reset Driver"
  65. depends on HAS_IOMEM
  66. depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
  67. default y if SOC_IMX7D
  68. select MFD_SYSCON
  69. help
  70. This enables the reset controller driver for i.MX7 SoCs.
  71. config RESET_INTEL_GW
  72. bool "Intel Reset Controller Driver"
  73. depends on X86 || COMPILE_TEST
  74. depends on OF && HAS_IOMEM
  75. select REGMAP_MMIO
  76. help
  77. This enables the reset controller driver for Intel Gateway SoCs.
  78. Say Y to control the reset signals provided by reset controller.
  79. Otherwise, say N.
  80. config RESET_K210
  81. bool "Reset controller driver for Canaan Kendryte K210 SoC"
  82. depends on (SOC_CANAAN || COMPILE_TEST) && OF
  83. select MFD_SYSCON
  84. default SOC_CANAAN
  85. help
  86. Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
  87. Say Y if you want to control reset signals provided by this
  88. controller.
  89. config RESET_LANTIQ
  90. bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
  91. default SOC_TYPE_XWAY
  92. help
  93. This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
  94. config RESET_LPC18XX
  95. bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
  96. default ARCH_LPC18XX
  97. help
  98. This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
  99. config RESET_MCHP_SPARX5
  100. bool "Microchip Sparx5 reset driver"
  101. depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
  102. default y if SPARX5_SWITCH
  103. select MFD_SYSCON
  104. help
  105. This driver supports switch core reset for the Microchip Sparx5 SoC.
  106. config RESET_MESON
  107. tristate "Meson Reset Driver"
  108. depends on ARCH_MESON || COMPILE_TEST
  109. default ARCH_MESON
  110. help
  111. This enables the reset driver for Amlogic Meson SoCs.
  112. config RESET_MESON_AUDIO_ARB
  113. tristate "Meson Audio Memory Arbiter Reset Driver"
  114. depends on ARCH_MESON || COMPILE_TEST
  115. help
  116. This enables the reset driver for Audio Memory Arbiter of
  117. Amlogic's A113 based SoCs
  118. config RESET_NPCM
  119. bool "NPCM BMC Reset Driver" if COMPILE_TEST
  120. default ARCH_NPCM
  121. help
  122. This enables the reset controller driver for Nuvoton NPCM
  123. BMC SoCs.
  124. config RESET_OXNAS
  125. bool
  126. config RESET_PISTACHIO
  127. bool "Pistachio Reset Driver"
  128. depends on MIPS || COMPILE_TEST
  129. help
  130. This enables the reset driver for ImgTec Pistachio SoCs.
  131. config RESET_POLARFIRE_SOC
  132. bool "Microchip PolarFire SoC (MPFS) Reset Driver"
  133. depends on AUXILIARY_BUS && MCHP_CLK_MPFS
  134. default MCHP_CLK_MPFS
  135. help
  136. This driver supports peripheral reset for the Microchip PolarFire SoC
  137. config RESET_QCOM_AOSS
  138. tristate "Qcom AOSS Reset Driver"
  139. depends on ARCH_QCOM || COMPILE_TEST
  140. help
  141. This enables the AOSS (always on subsystem) reset driver
  142. for Qualcomm SDM845 SoCs. Say Y if you want to control
  143. reset signals provided by AOSS for Modem, Venus, ADSP,
  144. GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
  145. config RESET_QCOM_PDC
  146. tristate "Qualcomm PDC Reset Driver"
  147. depends on ARCH_QCOM || COMPILE_TEST
  148. help
  149. This enables the PDC (Power Domain Controller) reset driver
  150. for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
  151. to control reset signals provided by PDC for Modem, Compute,
  152. Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
  153. config RESET_RASPBERRYPI
  154. tristate "Raspberry Pi 4 Firmware Reset Driver"
  155. depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
  156. default USB_XHCI_PCI
  157. help
  158. Raspberry Pi 4's co-processor controls some of the board's HW
  159. initialization process, but it's up to Linux to trigger it when
  160. relevant. This driver provides a reset controller capable of
  161. interfacing with RPi4's co-processor and model these firmware
  162. initialization routines as reset lines.
  163. config RESET_RZG2L_USBPHY_CTRL
  164. tristate "Renesas RZ/G2L USBPHY control driver"
  165. depends on ARCH_RZG2L || COMPILE_TEST
  166. help
  167. Support for USBPHY Control found on RZ/G2L family. It mainly
  168. controls reset and power down of the USB/PHY.
  169. config RESET_SCMI
  170. tristate "Reset driver controlled via ARM SCMI interface"
  171. depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
  172. default ARM_SCMI_PROTOCOL
  173. help
  174. This driver provides support for reset signal/domains that are
  175. controlled by firmware that implements the SCMI interface.
  176. This driver uses SCMI Message Protocol to interact with the
  177. firmware controlling all the reset signals.
  178. config RESET_SIMPLE
  179. bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
  180. default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
  181. depends on HAS_IOMEM
  182. help
  183. This enables a simple reset controller driver for reset lines that
  184. that can be asserted and deasserted by toggling bits in a contiguous,
  185. exclusive register space.
  186. Currently this driver supports:
  187. - Altera SoCFPGAs
  188. - ASPEED BMC SoCs
  189. - Bitmain BM1880 SoC
  190. - Realtek SoCs
  191. - RCC reset controller in STM32 MCUs
  192. - Allwinner SoCs
  193. - SiFive FU740 SoCs
  194. config RESET_SOCFPGA
  195. bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
  196. default ARM && ARCH_INTEL_SOCFPGA
  197. select RESET_SIMPLE
  198. help
  199. This enables the reset driver for the SoCFPGA ARMv7 platforms. This
  200. driver gets initialized early during platform init calls.
  201. config RESET_STARFIVE_JH7100
  202. bool "StarFive JH7100 Reset Driver"
  203. depends on SOC_STARFIVE || COMPILE_TEST
  204. default SOC_STARFIVE
  205. help
  206. This enables the reset controller driver for the StarFive JH7100 SoC.
  207. config RESET_SUNPLUS
  208. bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
  209. default ARCH_SUNPLUS
  210. help
  211. This enables the reset driver support for Sunplus SoCs.
  212. The reset lines that can be asserted and deasserted by toggling bits
  213. in a contiguous, exclusive register space. The register is HIWORD_MASKED,
  214. which means each register holds 16 reset lines.
  215. config RESET_SUNXI
  216. bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
  217. default ARCH_SUNXI
  218. select RESET_SIMPLE
  219. help
  220. This enables the reset driver for Allwinner SoCs.
  221. config RESET_TI_SCI
  222. tristate "TI System Control Interface (TI-SCI) reset driver"
  223. depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
  224. help
  225. This enables the reset driver support over TI System Control Interface
  226. available on some new TI's SoCs. If you wish to use reset resources
  227. managed by the TI System Controller, say Y here. Otherwise, say N.
  228. config RESET_TI_SYSCON
  229. tristate "TI SYSCON Reset Driver"
  230. depends on HAS_IOMEM
  231. select MFD_SYSCON
  232. help
  233. This enables the reset driver support for TI devices with
  234. memory-mapped reset registers as part of a syscon device node. If
  235. you wish to use the reset framework for such memory-mapped devices,
  236. say Y here. Otherwise, say N.
  237. config RESET_TI_TPS380X
  238. tristate "TI TPS380x Reset Driver"
  239. select GPIOLIB
  240. help
  241. This enables the reset driver support for TI TPS380x devices. If
  242. you wish to use the reset framework for such devices, say Y here.
  243. Otherwise, say N.
  244. config RESET_TN48M_CPLD
  245. tristate "Delta Networks TN48M switch CPLD reset controller"
  246. depends on MFD_TN48M_CPLD || COMPILE_TEST
  247. default MFD_TN48M_CPLD
  248. help
  249. This enables the reset controller driver for the Delta TN48M CPLD.
  250. It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
  251. switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
  252. Microchip PD69200 PoE PSE controller.
  253. This driver can also be built as a module. If so, the module will be
  254. called reset-tn48m.
  255. config RESET_UNIPHIER
  256. tristate "Reset controller driver for UniPhier SoCs"
  257. depends on ARCH_UNIPHIER || COMPILE_TEST
  258. depends on OF && MFD_SYSCON
  259. default ARCH_UNIPHIER
  260. help
  261. Support for reset controllers on UniPhier SoCs.
  262. Say Y if you want to control reset signals provided by System Control
  263. block, Media I/O block, Peripheral Block.
  264. config RESET_UNIPHIER_GLUE
  265. tristate "Reset driver in glue layer for UniPhier SoCs"
  266. depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
  267. default ARCH_UNIPHIER
  268. select RESET_SIMPLE
  269. help
  270. Support for peripheral core reset included in its own glue layer
  271. on UniPhier SoCs. Say Y if you want to control reset signals
  272. provided by the glue layer.
  273. config RESET_ZYNQ
  274. bool "ZYNQ Reset Driver" if COMPILE_TEST
  275. default ARCH_ZYNQ
  276. help
  277. This enables the reset controller driver for Xilinx Zynq SoCs.
  278. source "drivers/reset/sti/Kconfig"
  279. source "drivers/reset/hisilicon/Kconfig"
  280. source "drivers/reset/tegra/Kconfig"
  281. endif