mt6315-regulator.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2021 MediaTek Inc.
  4. #include <linux/module.h>
  5. #include <linux/of_device.h>
  6. #include <linux/regmap.h>
  7. #include <linux/regulator/driver.h>
  8. #include <linux/regulator/machine.h>
  9. #include <linux/regulator/mt6315-regulator.h>
  10. #include <linux/regulator/of_regulator.h>
  11. #include <linux/spmi.h>
  12. #define MT6315_BUCK_MODE_AUTO 0
  13. #define MT6315_BUCK_MODE_FORCE_PWM 1
  14. #define MT6315_BUCK_MODE_LP 2
  15. struct mt6315_regulator_info {
  16. struct regulator_desc desc;
  17. u32 status_reg;
  18. u32 lp_mode_mask;
  19. u32 lp_mode_shift;
  20. };
  21. struct mt_regulator_init_data {
  22. u32 modeset_mask[MT6315_VBUCK_MAX];
  23. };
  24. struct mt6315_chip {
  25. struct device *dev;
  26. struct regmap *regmap;
  27. };
  28. #define MT_BUCK(_name, _bid, _vsel) \
  29. [_bid] = { \
  30. .desc = { \
  31. .name = _name, \
  32. .of_match = of_match_ptr(_name), \
  33. .regulators_node = "regulators", \
  34. .ops = &mt6315_volt_range_ops, \
  35. .type = REGULATOR_VOLTAGE, \
  36. .id = _bid, \
  37. .owner = THIS_MODULE, \
  38. .n_voltages = 0xc0, \
  39. .linear_ranges = mt_volt_range1, \
  40. .n_linear_ranges = ARRAY_SIZE(mt_volt_range1), \
  41. .vsel_reg = _vsel, \
  42. .vsel_mask = 0xff, \
  43. .enable_reg = MT6315_BUCK_TOP_CON0, \
  44. .enable_mask = BIT(_bid), \
  45. .of_map_mode = mt6315_map_mode, \
  46. }, \
  47. .status_reg = _bid##_DBG4, \
  48. .lp_mode_mask = BIT(_bid), \
  49. .lp_mode_shift = _bid, \
  50. }
  51. static const struct linear_range mt_volt_range1[] = {
  52. REGULATOR_LINEAR_RANGE(0, 0, 0xbf, 6250),
  53. };
  54. static unsigned int mt6315_map_mode(unsigned int mode)
  55. {
  56. switch (mode) {
  57. case MT6315_BUCK_MODE_AUTO:
  58. return REGULATOR_MODE_NORMAL;
  59. case MT6315_BUCK_MODE_FORCE_PWM:
  60. return REGULATOR_MODE_FAST;
  61. case MT6315_BUCK_MODE_LP:
  62. return REGULATOR_MODE_IDLE;
  63. default:
  64. return REGULATOR_MODE_INVALID;
  65. }
  66. }
  67. static unsigned int mt6315_regulator_get_mode(struct regulator_dev *rdev)
  68. {
  69. struct mt_regulator_init_data *init = rdev_get_drvdata(rdev);
  70. const struct mt6315_regulator_info *info;
  71. int ret, regval;
  72. u32 modeset_mask;
  73. info = container_of(rdev->desc, struct mt6315_regulator_info, desc);
  74. modeset_mask = init->modeset_mask[rdev_get_id(rdev)];
  75. ret = regmap_read(rdev->regmap, MT6315_BUCK_TOP_4PHASE_ANA_CON42, &regval);
  76. if (ret != 0) {
  77. dev_err(&rdev->dev, "Failed to get mode: %d\n", ret);
  78. return ret;
  79. }
  80. if ((regval & modeset_mask) == modeset_mask)
  81. return REGULATOR_MODE_FAST;
  82. ret = regmap_read(rdev->regmap, MT6315_BUCK_TOP_CON1, &regval);
  83. if (ret != 0) {
  84. dev_err(&rdev->dev, "Failed to get lp mode: %d\n", ret);
  85. return ret;
  86. }
  87. if (regval & info->lp_mode_mask)
  88. return REGULATOR_MODE_IDLE;
  89. else
  90. return REGULATOR_MODE_NORMAL;
  91. }
  92. static int mt6315_regulator_set_mode(struct regulator_dev *rdev,
  93. u32 mode)
  94. {
  95. struct mt_regulator_init_data *init = rdev_get_drvdata(rdev);
  96. const struct mt6315_regulator_info *info;
  97. int ret, val, curr_mode;
  98. u32 modeset_mask;
  99. info = container_of(rdev->desc, struct mt6315_regulator_info, desc);
  100. modeset_mask = init->modeset_mask[rdev_get_id(rdev)];
  101. curr_mode = mt6315_regulator_get_mode(rdev);
  102. switch (mode) {
  103. case REGULATOR_MODE_FAST:
  104. ret = regmap_update_bits(rdev->regmap,
  105. MT6315_BUCK_TOP_4PHASE_ANA_CON42,
  106. modeset_mask,
  107. modeset_mask);
  108. break;
  109. case REGULATOR_MODE_NORMAL:
  110. if (curr_mode == REGULATOR_MODE_FAST) {
  111. ret = regmap_update_bits(rdev->regmap,
  112. MT6315_BUCK_TOP_4PHASE_ANA_CON42,
  113. modeset_mask,
  114. 0);
  115. } else if (curr_mode == REGULATOR_MODE_IDLE) {
  116. ret = regmap_update_bits(rdev->regmap,
  117. MT6315_BUCK_TOP_CON1,
  118. info->lp_mode_mask,
  119. 0);
  120. usleep_range(100, 110);
  121. } else {
  122. ret = -EINVAL;
  123. }
  124. break;
  125. case REGULATOR_MODE_IDLE:
  126. val = MT6315_BUCK_MODE_LP >> 1;
  127. val <<= info->lp_mode_shift;
  128. ret = regmap_update_bits(rdev->regmap,
  129. MT6315_BUCK_TOP_CON1,
  130. info->lp_mode_mask,
  131. val);
  132. break;
  133. default:
  134. ret = -EINVAL;
  135. dev_err(&rdev->dev, "Unsupported mode: %d\n", mode);
  136. break;
  137. }
  138. if (ret != 0) {
  139. dev_err(&rdev->dev, "Failed to set mode: %d\n", ret);
  140. return ret;
  141. }
  142. return 0;
  143. }
  144. static int mt6315_get_status(struct regulator_dev *rdev)
  145. {
  146. const struct mt6315_regulator_info *info;
  147. int ret;
  148. u32 regval;
  149. info = container_of(rdev->desc, struct mt6315_regulator_info, desc);
  150. ret = regmap_read(rdev->regmap, info->status_reg, &regval);
  151. if (ret < 0) {
  152. dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
  153. return ret;
  154. }
  155. return (regval & BIT(0)) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
  156. }
  157. static const struct regulator_ops mt6315_volt_range_ops = {
  158. .list_voltage = regulator_list_voltage_linear_range,
  159. .map_voltage = regulator_map_voltage_linear_range,
  160. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  161. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  162. .set_voltage_time_sel = regulator_set_voltage_time_sel,
  163. .enable = regulator_enable_regmap,
  164. .disable = regulator_disable_regmap,
  165. .is_enabled = regulator_is_enabled_regmap,
  166. .get_status = mt6315_get_status,
  167. .set_mode = mt6315_regulator_set_mode,
  168. .get_mode = mt6315_regulator_get_mode,
  169. };
  170. static const struct mt6315_regulator_info mt6315_regulators[MT6315_VBUCK_MAX] = {
  171. MT_BUCK("vbuck1", MT6315_VBUCK1, MT6315_BUCK_TOP_ELR0),
  172. MT_BUCK("vbuck2", MT6315_VBUCK2, MT6315_BUCK_TOP_ELR2),
  173. MT_BUCK("vbuck3", MT6315_VBUCK3, MT6315_BUCK_TOP_ELR4),
  174. MT_BUCK("vbuck4", MT6315_VBUCK4, MT6315_BUCK_TOP_ELR6),
  175. };
  176. static const struct regmap_config mt6315_regmap_config = {
  177. .reg_bits = 16,
  178. .val_bits = 8,
  179. .max_register = 0x16d0,
  180. .fast_io = true,
  181. };
  182. static const struct of_device_id mt6315_of_match[] = {
  183. {
  184. .compatible = "mediatek,mt6315-regulator",
  185. }, {
  186. /* sentinel */
  187. },
  188. };
  189. MODULE_DEVICE_TABLE(of, mt6315_of_match);
  190. static int mt6315_regulator_probe(struct spmi_device *pdev)
  191. {
  192. struct device *dev = &pdev->dev;
  193. struct regmap *regmap;
  194. struct mt6315_chip *chip;
  195. struct mt_regulator_init_data *init_data;
  196. struct regulator_config config = {};
  197. struct regulator_dev *rdev;
  198. int i;
  199. regmap = devm_regmap_init_spmi_ext(pdev, &mt6315_regmap_config);
  200. if (IS_ERR(regmap))
  201. return PTR_ERR(regmap);
  202. chip = devm_kzalloc(dev, sizeof(struct mt6315_chip), GFP_KERNEL);
  203. if (!chip)
  204. return -ENOMEM;
  205. init_data = devm_kzalloc(dev, sizeof(struct mt_regulator_init_data), GFP_KERNEL);
  206. if (!init_data)
  207. return -ENOMEM;
  208. switch (pdev->usid) {
  209. case MT6315_PP:
  210. init_data->modeset_mask[MT6315_VBUCK1] = BIT(MT6315_VBUCK1) | BIT(MT6315_VBUCK2) |
  211. BIT(MT6315_VBUCK4);
  212. break;
  213. case MT6315_SP:
  214. case MT6315_RP:
  215. init_data->modeset_mask[MT6315_VBUCK1] = BIT(MT6315_VBUCK1) | BIT(MT6315_VBUCK2);
  216. break;
  217. default:
  218. init_data->modeset_mask[MT6315_VBUCK1] = BIT(MT6315_VBUCK1);
  219. break;
  220. }
  221. for (i = MT6315_VBUCK2; i < MT6315_VBUCK_MAX; i++)
  222. init_data->modeset_mask[i] = BIT(i);
  223. chip->dev = dev;
  224. chip->regmap = regmap;
  225. dev_set_drvdata(dev, chip);
  226. config.dev = dev;
  227. config.regmap = regmap;
  228. for (i = MT6315_VBUCK1; i < MT6315_VBUCK_MAX; i++) {
  229. config.driver_data = init_data;
  230. rdev = devm_regulator_register(dev, &mt6315_regulators[i].desc, &config);
  231. if (IS_ERR(rdev)) {
  232. dev_err(dev, "Failed to register %s\n",
  233. mt6315_regulators[i].desc.name);
  234. return PTR_ERR(rdev);
  235. }
  236. }
  237. return 0;
  238. }
  239. static void mt6315_regulator_shutdown(struct spmi_device *pdev)
  240. {
  241. struct mt6315_chip *chip = dev_get_drvdata(&pdev->dev);
  242. int ret = 0;
  243. ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY_H, PROTECTION_KEY_H);
  244. ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY, PROTECTION_KEY);
  245. ret |= regmap_update_bits(chip->regmap, MT6315_TOP2_ELR7, 1, 1);
  246. ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY, 0);
  247. ret |= regmap_write(chip->regmap, MT6315_TOP_TMA_KEY_H, 0);
  248. if (ret < 0)
  249. dev_err(&pdev->dev, "[%#x] Failed to enable power off sequence. %d\n",
  250. pdev->usid, ret);
  251. }
  252. static struct spmi_driver mt6315_regulator_driver = {
  253. .driver = {
  254. .name = "mt6315-regulator",
  255. .of_match_table = mt6315_of_match,
  256. },
  257. .probe = mt6315_regulator_probe,
  258. .shutdown = mt6315_regulator_shutdown,
  259. };
  260. module_spmi_driver(mt6315_regulator_driver);
  261. MODULE_AUTHOR("Hsin-Hsiung Wang <[email protected]>");
  262. MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6315 PMIC");
  263. MODULE_LICENSE("GPL");