pwm-crc.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Intel Corporation. All rights reserved.
  4. *
  5. * Author: Shobhit Kumar <[email protected]>
  6. */
  7. #include <linux/platform_device.h>
  8. #include <linux/regmap.h>
  9. #include <linux/mfd/intel_soc_pmic.h>
  10. #include <linux/pwm.h>
  11. #define PWM0_CLK_DIV 0x4B
  12. #define PWM_OUTPUT_ENABLE BIT(7)
  13. #define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
  14. #define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
  15. #define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
  16. #define PWM0_DUTY_CYCLE 0x4E
  17. #define BACKLIGHT_EN 0x51
  18. #define PWM_MAX_LEVEL 0xFF
  19. #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */
  20. #define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */
  21. /**
  22. * struct crystalcove_pwm - Crystal Cove PWM controller
  23. * @chip: the abstract pwm_chip structure.
  24. * @regmap: the regmap from the parent device.
  25. */
  26. struct crystalcove_pwm {
  27. struct pwm_chip chip;
  28. struct regmap *regmap;
  29. };
  30. static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
  31. {
  32. return container_of(pc, struct crystalcove_pwm, chip);
  33. }
  34. static int crc_pwm_calc_clk_div(int period_ns)
  35. {
  36. int clk_div;
  37. clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
  38. /* clk_div 1 - 128, maps to register values 0-127 */
  39. if (clk_div > 0)
  40. clk_div--;
  41. return clk_div;
  42. }
  43. static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  44. const struct pwm_state *state)
  45. {
  46. struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
  47. struct device *dev = crc_pwm->chip.dev;
  48. int err;
  49. if (state->period > PWM_MAX_PERIOD_NS) {
  50. dev_err(dev, "un-supported period_ns\n");
  51. return -EINVAL;
  52. }
  53. if (state->polarity != PWM_POLARITY_NORMAL)
  54. return -EINVAL;
  55. if (pwm_is_enabled(pwm) && !state->enabled) {
  56. err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
  57. if (err) {
  58. dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
  59. return err;
  60. }
  61. }
  62. if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||
  63. pwm_get_period(pwm) != state->period) {
  64. u64 level = state->duty_cycle * PWM_MAX_LEVEL;
  65. do_div(level, state->period);
  66. err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
  67. if (err) {
  68. dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err);
  69. return err;
  70. }
  71. }
  72. if (pwm_is_enabled(pwm) && state->enabled &&
  73. pwm_get_period(pwm) != state->period) {
  74. /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
  75. err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
  76. if (err) {
  77. dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
  78. return err;
  79. }
  80. }
  81. if (pwm_get_period(pwm) != state->period ||
  82. pwm_is_enabled(pwm) != state->enabled) {
  83. int clk_div = crc_pwm_calc_clk_div(state->period);
  84. int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;
  85. err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
  86. clk_div | pwm_output_enable);
  87. if (err) {
  88. dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
  89. return err;
  90. }
  91. }
  92. if (!pwm_is_enabled(pwm) && state->enabled) {
  93. err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
  94. if (err) {
  95. dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
  96. return err;
  97. }
  98. }
  99. return 0;
  100. }
  101. static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  102. struct pwm_state *state)
  103. {
  104. struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
  105. struct device *dev = crc_pwm->chip.dev;
  106. unsigned int clk_div, clk_div_reg, duty_cycle_reg;
  107. int error;
  108. error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
  109. if (error) {
  110. dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
  111. return 0;
  112. }
  113. error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
  114. if (error) {
  115. dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
  116. return 0;
  117. }
  118. clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
  119. state->period =
  120. DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
  121. state->duty_cycle =
  122. DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
  123. state->polarity = PWM_POLARITY_NORMAL;
  124. state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
  125. return 0;
  126. }
  127. static const struct pwm_ops crc_pwm_ops = {
  128. .apply = crc_pwm_apply,
  129. .get_state = crc_pwm_get_state,
  130. };
  131. static int crystalcove_pwm_probe(struct platform_device *pdev)
  132. {
  133. struct crystalcove_pwm *pwm;
  134. struct device *dev = pdev->dev.parent;
  135. struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
  136. pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
  137. if (!pwm)
  138. return -ENOMEM;
  139. pwm->chip.dev = &pdev->dev;
  140. pwm->chip.ops = &crc_pwm_ops;
  141. pwm->chip.npwm = 1;
  142. /* get the PMIC regmap */
  143. pwm->regmap = pmic->regmap;
  144. return devm_pwmchip_add(&pdev->dev, &pwm->chip);
  145. }
  146. static struct platform_driver crystalcove_pwm_driver = {
  147. .probe = crystalcove_pwm_probe,
  148. .driver = {
  149. .name = "crystal_cove_pwm",
  150. },
  151. };
  152. builtin_platform_driver(crystalcove_pwm_driver);