at91-poweroff.c 6.2 KB

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  1. /*
  2. * Atmel AT91 SAM9 SoCs reset code
  3. *
  4. * Copyright (C) 2007 Atmel Corporation.
  5. * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
  6. * Copyright (C) 2014 Free Electrons
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/printk.h>
  19. #include <soc/at91/at91sam9_ddrsdr.h>
  20. #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
  21. #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */
  22. #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
  23. #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
  24. #define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */
  25. #define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */
  26. #define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
  27. #define AT91_SHDW_CPTWK0_(x) ((x) << 4)
  28. #define AT91_SHDW_RTTWKEN BIT(16) /* Real Time Timer Wake-up Enable */
  29. #define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */
  30. #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
  31. #define AT91_SHDW_WAKEUP0 BIT(0) /* Wake-up 0 Status */
  32. #define AT91_SHDW_RTTWK BIT(16) /* Real-time Timer Wake-up */
  33. #define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */
  34. enum wakeup_type {
  35. AT91_SHDW_WKMODE0_NONE = 0,
  36. AT91_SHDW_WKMODE0_HIGH = 1,
  37. AT91_SHDW_WKMODE0_LOW = 2,
  38. AT91_SHDW_WKMODE0_ANYLEVEL = 3,
  39. };
  40. static const char *shdwc_wakeup_modes[] = {
  41. [AT91_SHDW_WKMODE0_NONE] = "none",
  42. [AT91_SHDW_WKMODE0_HIGH] = "high",
  43. [AT91_SHDW_WKMODE0_LOW] = "low",
  44. [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
  45. };
  46. static struct shdwc {
  47. struct clk *sclk;
  48. void __iomem *shdwc_base;
  49. void __iomem *mpddrc_base;
  50. } at91_shdwc;
  51. static void __init at91_wakeup_status(struct platform_device *pdev)
  52. {
  53. const char *reason;
  54. u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR);
  55. /* Simple power-on, just bail out */
  56. if (!reg)
  57. return;
  58. if (reg & AT91_SHDW_RTTWK)
  59. reason = "RTT";
  60. else if (reg & AT91_SHDW_RTCWK)
  61. reason = "RTC";
  62. else
  63. reason = "unknown";
  64. dev_info(&pdev->dev, "Wake-Up source: %s\n", reason);
  65. }
  66. static void at91_poweroff(void)
  67. {
  68. asm volatile(
  69. /* Align to cache lines */
  70. ".balign 32\n\t"
  71. /* Ensure AT91_SHDW_CR is in the TLB by reading it */
  72. " ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  73. /* Power down SDRAM0 */
  74. " tst %0, #0\n\t"
  75. " beq 1f\n\t"
  76. " str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
  77. /* Shutdown CPU */
  78. "1: str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  79. " b .\n\t"
  80. :
  81. : "r" (at91_shdwc.mpddrc_base),
  82. "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
  83. "r" (at91_shdwc.shdwc_base),
  84. "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
  85. : "r6");
  86. }
  87. static int at91_poweroff_get_wakeup_mode(struct device_node *np)
  88. {
  89. const char *pm;
  90. unsigned int i;
  91. int err;
  92. err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
  93. if (err < 0)
  94. return AT91_SHDW_WKMODE0_ANYLEVEL;
  95. for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
  96. if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
  97. return i;
  98. return -ENODEV;
  99. }
  100. static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
  101. {
  102. struct device_node *np = pdev->dev.of_node;
  103. int wakeup_mode;
  104. u32 mode = 0, tmp;
  105. wakeup_mode = at91_poweroff_get_wakeup_mode(np);
  106. if (wakeup_mode < 0) {
  107. dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n");
  108. return;
  109. }
  110. if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) {
  111. if (tmp > AT91_SHDW_CPTWK0_MAX) {
  112. dev_warn(&pdev->dev,
  113. "shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
  114. tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
  115. tmp = AT91_SHDW_CPTWK0_MAX;
  116. }
  117. mode |= AT91_SHDW_CPTWK0_(tmp);
  118. }
  119. if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
  120. mode |= AT91_SHDW_RTCWKEN;
  121. if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
  122. mode |= AT91_SHDW_RTTWKEN;
  123. writel(wakeup_mode | mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
  124. }
  125. static int __init at91_poweroff_probe(struct platform_device *pdev)
  126. {
  127. struct resource *res;
  128. struct device_node *np;
  129. u32 ddr_type;
  130. int ret;
  131. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  132. at91_shdwc.shdwc_base = devm_ioremap_resource(&pdev->dev, res);
  133. if (IS_ERR(at91_shdwc.shdwc_base))
  134. return PTR_ERR(at91_shdwc.shdwc_base);
  135. at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
  136. if (IS_ERR(at91_shdwc.sclk))
  137. return PTR_ERR(at91_shdwc.sclk);
  138. ret = clk_prepare_enable(at91_shdwc.sclk);
  139. if (ret) {
  140. dev_err(&pdev->dev, "Could not enable slow clock\n");
  141. return ret;
  142. }
  143. at91_wakeup_status(pdev);
  144. if (pdev->dev.of_node)
  145. at91_poweroff_dt_set_wakeup_mode(pdev);
  146. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
  147. if (np) {
  148. at91_shdwc.mpddrc_base = of_iomap(np, 0);
  149. of_node_put(np);
  150. if (!at91_shdwc.mpddrc_base) {
  151. ret = -ENOMEM;
  152. goto clk_disable;
  153. }
  154. ddr_type = readl(at91_shdwc.mpddrc_base + AT91_DDRSDRC_MDR) &
  155. AT91_DDRSDRC_MD;
  156. if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
  157. ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
  158. iounmap(at91_shdwc.mpddrc_base);
  159. at91_shdwc.mpddrc_base = NULL;
  160. }
  161. }
  162. pm_power_off = at91_poweroff;
  163. return 0;
  164. clk_disable:
  165. clk_disable_unprepare(at91_shdwc.sclk);
  166. return ret;
  167. }
  168. static int __exit at91_poweroff_remove(struct platform_device *pdev)
  169. {
  170. if (pm_power_off == at91_poweroff)
  171. pm_power_off = NULL;
  172. if (at91_shdwc.mpddrc_base)
  173. iounmap(at91_shdwc.mpddrc_base);
  174. clk_disable_unprepare(at91_shdwc.sclk);
  175. return 0;
  176. }
  177. static const struct of_device_id at91_poweroff_of_match[] = {
  178. { .compatible = "atmel,at91sam9260-shdwc", },
  179. { .compatible = "atmel,at91sam9rl-shdwc", },
  180. { .compatible = "atmel,at91sam9x5-shdwc", },
  181. { /*sentinel*/ }
  182. };
  183. MODULE_DEVICE_TABLE(of, at91_poweroff_of_match);
  184. static struct platform_driver at91_poweroff_driver = {
  185. .remove = __exit_p(at91_poweroff_remove),
  186. .driver = {
  187. .name = "at91-poweroff",
  188. .of_match_table = at91_poweroff_of_match,
  189. },
  190. };
  191. module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe);
  192. MODULE_AUTHOR("Atmel Corporation");
  193. MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs");
  194. MODULE_LICENSE("GPL v2");