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android_kernel_...
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drivers
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platform
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mellanox
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mlxbf-tmfifo-regs.h

mlxbf-tmfifo-regs.h 2.7 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2019, Mellanox Technologies. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef __MLXBF_TMFIFO_REGS_H__
    7. 

  7. #define __MLXBF_TMFIFO_REGS_H__
    8. 

  8. 

  9. #include <linux/types.h>
    10. 

  10. #include <linux/bits.h>
    11. 

  11. 

  12. #define MLXBF_TMFIFO_TX_DATA				0x00
    13. 

  13. #define MLXBF_TMFIFO_TX_STS				0x08
    14. 

  14. #define MLXBF_TMFIFO_TX_STS__LENGTH			0x0001
    15. 

  15. #define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT		0
    16. 

  16. #define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH		9
    17. 

  17. #define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL		0
    18. 

  18. #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK		GENMASK_ULL(8, 0)
    19. 

  19. #define MLXBF_TMFIFO_TX_STS__COUNT_MASK			GENMASK_ULL(8, 0)
    20. 

  20. #define MLXBF_TMFIFO_TX_CTL				0x10
    21. 

  21. #define MLXBF_TMFIFO_TX_CTL__LENGTH			0x0001
    22. 

  22. #define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT			0
    23. 

  23. #define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH			8
    24. 

  24. #define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL		128
    25. 

  25. #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK			GENMASK_ULL(7, 0)
    26. 

  26. #define MLXBF_TMFIFO_TX_CTL__LWM_MASK			GENMASK_ULL(7, 0)
    27. 

  27. #define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT			8
    28. 

  28. #define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH			8
    29. 

  29. #define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL		128
    30. 

  30. #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK			GENMASK_ULL(7, 0)
    31. 

  31. #define MLXBF_TMFIFO_TX_CTL__HWM_MASK			GENMASK_ULL(15, 8)
    32. 

  32. #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT		32
    33. 

  33. #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH		9
    34. 

  34. #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL	256
    35. 

  35. #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK		GENMASK_ULL(8, 0)
    36. 

  36. #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK		GENMASK_ULL(40, 32)
    37. 

  37. #define MLXBF_TMFIFO_RX_DATA				0x00
    38. 

  38. #define MLXBF_TMFIFO_RX_STS				0x08
    39. 

  39. #define MLXBF_TMFIFO_RX_STS__LENGTH			0x0001
    40. 

  40. #define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT		0
    41. 

  41. #define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH		9
    42. 

  42. #define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL		0
    43. 

  43. #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK		GENMASK_ULL(8, 0)
    44. 

  44. #define MLXBF_TMFIFO_RX_STS__COUNT_MASK			GENMASK_ULL(8, 0)
    45. 

  45. #define MLXBF_TMFIFO_RX_CTL				0x10
    46. 

  46. #define MLXBF_TMFIFO_RX_CTL__LENGTH			0x0001
    47. 

  47. #define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT			0
    48. 

  48. #define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH			8
    49. 

  49. #define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL		128
    50. 

  50. #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK			GENMASK_ULL(7, 0)
    51. 

  51. #define MLXBF_TMFIFO_RX_CTL__LWM_MASK			GENMASK_ULL(7, 0)
    52. 

  52. #define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT			8
    53. 

  53. #define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH			8
    54. 

  54. #define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL		128
    55. 

  55. #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK			GENMASK_ULL(7, 0)
    56. 

  56. #define MLXBF_TMFIFO_RX_CTL__HWM_MASK			GENMASK_ULL(15, 8)
    57. 

  57. #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT		32
    58. 

  58. #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH		9
    59. 

  59. #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL	256
    60. 

  60. #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK		GENMASK_ULL(8, 0)
    61. 

  61. #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK		GENMASK_ULL(40, 32)
    62. 

  62. 

  63. #endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */
    64.