pinctrl-mt2712.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 MediaTek Inc.
  4. * Author: Zhiyong Tao <[email protected]>
  5. *
  6. */
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/of.h>
  10. #include <linux/of_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pinctrl/pinconf-generic.h>
  14. #include <dt-bindings/pinctrl/mt65xx.h>
  15. #include "pinctrl-mtk-common.h"
  16. #include "pinctrl-mtk-mt2712.h"
  17. static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
  18. MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
  19. MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
  20. MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
  21. MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
  22. MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
  23. MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
  24. MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
  25. MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
  26. MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
  27. MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
  28. MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
  29. MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
  30. MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
  31. MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
  32. MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
  33. MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
  34. MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
  35. MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
  36. MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
  37. MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
  38. MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
  39. MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
  40. MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
  41. MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
  42. MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
  43. MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
  44. MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
  45. MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
  46. MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
  47. MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
  48. MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
  49. MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
  50. MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
  51. MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
  52. MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
  53. MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
  54. MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
  55. MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
  56. MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
  57. MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
  58. MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
  59. MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
  60. MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
  61. MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
  62. MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
  63. MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
  64. MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
  65. MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
  66. MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
  67. MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
  68. MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
  69. MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
  70. MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
  71. MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
  72. MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12),
  73. MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
  74. MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
  75. };
  76. static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
  77. MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
  78. MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
  79. MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
  80. MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6),
  81. MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7),
  82. MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6),
  83. MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7),
  84. MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1),
  85. MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
  86. MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3),
  87. MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4),
  88. MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3),
  89. MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13),
  90. MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13),
  91. MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13),
  92. MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13),
  93. MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13),
  94. MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13),
  95. MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13),
  96. MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13),
  97. MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13),
  98. MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13),
  99. MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13),
  100. MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3),
  101. MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13),
  102. MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13),
  103. MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13),
  104. MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13),
  105. MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13),
  106. MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13),
  107. MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
  108. MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9),
  109. MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10),
  110. MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9),
  111. MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13),
  112. MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13),
  113. MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13),
  114. MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13),
  115. MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11),
  116. MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12),
  117. MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13),
  118. MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14),
  119. MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15),
  120. MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0),
  121. MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1),
  122. MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
  123. MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13),
  124. MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14),
  125. MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15),
  126. MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0),
  127. MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1),
  128. MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
  129. MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3),
  130. MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4),
  131. MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5),
  132. MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3),
  133. MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4),
  134. MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5),
  135. MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6),
  136. MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7),
  137. MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
  138. MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1),
  139. MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9),
  140. MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10),
  141. MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11),
  142. MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12),
  143. MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13),
  144. MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14),
  145. MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15),
  146. MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0),
  147. MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1),
  148. MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
  149. MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1),
  150. MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3),
  151. MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4),
  152. MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3),
  153. MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4),
  154. MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5),
  155. MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6),
  156. MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5),
  157. MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6),
  158. MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7),
  159. MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
  160. MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9),
  161. MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
  162. MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9),
  163. MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10),
  164. MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11),
  165. MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10),
  166. MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11),
  167. MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12),
  168. MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13),
  169. MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14),
  170. MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15)
  171. };
  172. static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
  173. MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
  174. MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0),
  175. MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
  176. MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4),
  177. MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6),
  178. MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7),
  179. MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6),
  180. MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7),
  181. MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1),
  182. MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
  183. MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3),
  184. MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4),
  185. MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3),
  186. MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14),
  187. MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14),
  188. MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14),
  189. MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14),
  190. MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14),
  191. MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14),
  192. MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14),
  193. MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14),
  194. MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14),
  195. MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14),
  196. MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14),
  197. MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3),
  198. MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14),
  199. MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14),
  200. MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14),
  201. MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14),
  202. MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14),
  203. MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
  204. MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9),
  205. MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10),
  206. MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9),
  207. MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14),
  208. MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14),
  209. MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14),
  210. MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14),
  211. MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11),
  212. MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12),
  213. MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13),
  214. MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14),
  215. MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15),
  216. MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0),
  217. MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1),
  218. MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
  219. MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13),
  220. MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14),
  221. MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15),
  222. MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0),
  223. MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1),
  224. MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
  225. MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3),
  226. MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4),
  227. MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5),
  228. MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3),
  229. MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4),
  230. MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5),
  231. MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6),
  232. MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7),
  233. MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
  234. MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1),
  235. MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9),
  236. MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10),
  237. MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11),
  238. MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12),
  239. MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13),
  240. MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14),
  241. MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15),
  242. MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0),
  243. MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1),
  244. MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
  245. MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1),
  246. MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3),
  247. MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4),
  248. MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3),
  249. MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4),
  250. MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5),
  251. MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6),
  252. MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5),
  253. MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6),
  254. MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7),
  255. MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
  256. MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9),
  257. MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
  258. MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9),
  259. MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10),
  260. MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11),
  261. MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10),
  262. MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11),
  263. MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12),
  264. MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13),
  265. MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14),
  266. MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
  267. };
  268. static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
  269. /* 0E4E8SR 4/8/12/16 */
  270. MTK_DRV_GRP(4, 16, 1, 2, 4),
  271. /* 0E2E4SR 2/4/6/8 */
  272. MTK_DRV_GRP(2, 8, 1, 2, 2),
  273. /* E8E4E2 2/4/6/8/10/12/14/16 */
  274. MTK_DRV_GRP(2, 16, 0, 2, 2)
  275. };
  276. static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
  277. MTK_PIN_DRV_GRP(0, 0xc10, 4, 0),
  278. MTK_PIN_DRV_GRP(1, 0xc10, 4, 0),
  279. MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
  280. MTK_PIN_DRV_GRP(3, 0xc10, 4, 0),
  281. MTK_PIN_DRV_GRP(4, 0xc00, 12, 0),
  282. MTK_PIN_DRV_GRP(5, 0xc00, 12, 0),
  283. MTK_PIN_DRV_GRP(6, 0xc00, 12, 0),
  284. MTK_PIN_DRV_GRP(7, 0xc00, 12, 0),
  285. MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
  286. MTK_PIN_DRV_GRP(9, 0xc10, 0, 0),
  287. MTK_PIN_DRV_GRP(10, 0xc10, 0, 0),
  288. MTK_PIN_DRV_GRP(11, 0xc10, 0, 0),
  289. MTK_PIN_DRV_GRP(12, 0xb60, 0, 0),
  290. MTK_PIN_DRV_GRP(13, 0xb60, 4, 0),
  291. MTK_PIN_DRV_GRP(14, 0xb60, 0, 0),
  292. MTK_PIN_DRV_GRP(15, 0xb60, 4, 0),
  293. MTK_PIN_DRV_GRP(18, 0xb40, 0, 1),
  294. MTK_PIN_DRV_GRP(19, 0xb40, 0, 1),
  295. MTK_PIN_DRV_GRP(20, 0xb40, 0, 1),
  296. MTK_PIN_DRV_GRP(21, 0xb40, 0, 1),
  297. MTK_PIN_DRV_GRP(22, 0xb40, 0, 1),
  298. MTK_PIN_DRV_GRP(23, 0xb40, 0, 1),
  299. MTK_PIN_DRV_GRP(24, 0xb40, 4, 0),
  300. MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
  301. MTK_PIN_DRV_GRP(26, 0xb40, 12, 0),
  302. MTK_PIN_DRV_GRP(27, 0xb50, 0, 0),
  303. MTK_PIN_DRV_GRP(28, 0xb40, 12, 0),
  304. MTK_PIN_DRV_GRP(29, 0xb40, 12, 0),
  305. MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
  306. MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
  307. MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
  308. MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
  309. MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
  310. MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
  311. MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
  312. MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
  313. MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
  314. MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
  315. MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
  316. MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
  317. MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
  318. MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
  319. MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
  320. MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
  321. MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
  322. MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
  323. MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
  324. MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
  325. MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
  326. MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
  327. MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
  328. MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
  329. MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
  330. MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
  331. MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
  332. MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
  333. MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
  334. MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
  335. MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
  336. MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
  337. MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
  338. MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
  339. MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
  340. MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
  341. MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
  342. MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
  343. MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
  344. MTK_PIN_DRV_GRP(75, 0xb60, 12, 1),
  345. MTK_PIN_DRV_GRP(76, 0xb60, 12, 1),
  346. MTK_PIN_DRV_GRP(77, 0xb60, 12, 1),
  347. MTK_PIN_DRV_GRP(78, 0xb70, 0, 1),
  348. MTK_PIN_DRV_GRP(79, 0xb70, 0, 1),
  349. MTK_PIN_DRV_GRP(80, 0xb70, 0, 1),
  350. MTK_PIN_DRV_GRP(81, 0xb70, 0, 1),
  351. MTK_PIN_DRV_GRP(82, 0xb60, 12, 1),
  352. MTK_PIN_DRV_GRP(83, 0xb60, 12, 1),
  353. MTK_PIN_DRV_GRP(84, 0xb60, 12, 1),
  354. MTK_PIN_DRV_GRP(85, 0xb60, 12, 1),
  355. MTK_PIN_DRV_GRP(86, 0xb60, 12, 1),
  356. MTK_PIN_DRV_GRP(87, 0xb60, 12, 1),
  357. MTK_PIN_DRV_GRP(88, 0xb60, 12, 1),
  358. MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
  359. MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
  360. MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
  361. MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
  362. MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
  363. MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
  364. MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
  365. MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
  366. MTK_PIN_DRV_GRP(97, 0xb70, 4, 0),
  367. MTK_PIN_DRV_GRP(98, 0xb70, 4, 0),
  368. MTK_PIN_DRV_GRP(99, 0xb70, 4, 0),
  369. MTK_PIN_DRV_GRP(100, 0xb70, 4, 0),
  370. MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
  371. MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
  372. MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
  373. MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
  374. MTK_PIN_DRV_GRP(135, 0xb40, 0, 1),
  375. MTK_PIN_DRV_GRP(136, 0xb40, 0, 1),
  376. MTK_PIN_DRV_GRP(137, 0xb40, 0, 1),
  377. MTK_PIN_DRV_GRP(138, 0xb40, 0, 1),
  378. MTK_PIN_DRV_GRP(139, 0xb40, 0, 1),
  379. MTK_PIN_DRV_GRP(140, 0xb40, 0, 1),
  380. MTK_PIN_DRV_GRP(141, 0xb40, 0, 1),
  381. MTK_PIN_DRV_GRP(142, 0xb40, 0, 1),
  382. MTK_PIN_DRV_GRP(143, 0xba0, 12, 0),
  383. MTK_PIN_DRV_GRP(144, 0xba0, 12, 0),
  384. MTK_PIN_DRV_GRP(145, 0xba0, 12, 0),
  385. MTK_PIN_DRV_GRP(146, 0xba0, 12, 0),
  386. MTK_PIN_DRV_GRP(147, 0xba0, 12, 0),
  387. MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0),
  388. MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0),
  389. MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0),
  390. MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0),
  391. MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0),
  392. MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0),
  393. MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0),
  394. MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0),
  395. MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0),
  396. MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
  397. MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
  398. MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
  399. MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
  400. MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0),
  401. MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0),
  402. MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0),
  403. MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0),
  404. MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0),
  405. MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0),
  406. MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0),
  407. MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0),
  408. MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0),
  409. MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0),
  410. MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
  411. MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
  412. MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0),
  413. MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0),
  414. MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0),
  415. MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0),
  416. MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0),
  417. MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
  418. MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0),
  419. MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
  420. MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0),
  421. MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0),
  422. MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0),
  423. MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0),
  424. MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0),
  425. MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
  426. MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0),
  427. MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0),
  428. MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0),
  429. MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0),
  430. MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0),
  431. MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
  432. MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0),
  433. MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0),
  434. MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
  435. MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0),
  436. MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0),
  437. MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0),
  438. MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0),
  439. MTK_PIN_DRV_GRP(200, 0xc00, 0, 0),
  440. MTK_PIN_DRV_GRP(201, 0xc00, 0, 0),
  441. MTK_PIN_DRV_GRP(202, 0xc00, 0, 0),
  442. MTK_PIN_DRV_GRP(203, 0xc00, 0, 0),
  443. MTK_PIN_DRV_GRP(204, 0xc00, 4, 0),
  444. MTK_PIN_DRV_GRP(205, 0xc00, 4, 0),
  445. MTK_PIN_DRV_GRP(206, 0xc00, 4, 0),
  446. MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
  447. MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
  448. MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
  449. };
  450. static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
  451. .pins = mtk_pins_mt2712,
  452. .npins = ARRAY_SIZE(mtk_pins_mt2712),
  453. .grp_desc = mt2712_drv_grp,
  454. .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
  455. .pin_drv_grp = mt2712_pin_drv,
  456. .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
  457. .spec_ies = mt2712_ies_set,
  458. .n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
  459. .spec_pupd = mt2712_spec_pupd,
  460. .n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
  461. .spec_smt = mt2712_smt_set,
  462. .n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
  463. .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
  464. .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
  465. .dir_offset = 0x0000,
  466. .pullen_offset = 0x0100,
  467. .pullsel_offset = 0x0200,
  468. .dout_offset = 0x0300,
  469. .din_offset = 0x0400,
  470. .pinmux_offset = 0x0500,
  471. .type1_start = 210,
  472. .type1_end = 210,
  473. .port_shf = 4,
  474. .port_mask = 0xf,
  475. .port_align = 4,
  476. .mode_mask = 0xf,
  477. .mode_per_reg = 5,
  478. .mode_shf = 4,
  479. .eint_hw = {
  480. .port_mask = 0xf,
  481. .ports = 8,
  482. .ap_num = 229,
  483. .db_cnt = 40,
  484. .db_time = debounce_time_mt2701,
  485. },
  486. };
  487. static const struct of_device_id mt2712_pctrl_match[] = {
  488. { .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
  489. { }
  490. };
  491. MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
  492. static struct platform_driver mtk_pinctrl_driver = {
  493. .probe = mtk_pctrl_common_probe,
  494. .driver = {
  495. .name = "mediatek-mt2712-pinctrl",
  496. .of_match_table = mt2712_pctrl_match,
  497. .pm = &mtk_eint_pm_ops,
  498. },
  499. };
  500. static int __init mtk_pinctrl_init(void)
  501. {
  502. return platform_driver_register(&mtk_pinctrl_driver);
  503. }
  504. arch_initcall(mtk_pinctrl_init);