Kconfig 15 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. #
  3. # PINCTRL infrastructure and drivers
  4. #
  5. menuconfig PINCTRL
  6. bool "Pin controllers"
  7. if PINCTRL
  8. config GENERIC_PINCTRL_GROUPS
  9. bool
  10. config PINMUX
  11. bool "Support pin multiplexing controllers" if COMPILE_TEST
  12. config GENERIC_PINMUX_FUNCTIONS
  13. bool
  14. select PINMUX
  15. config PINCONF
  16. bool "Support pin configuration controllers" if COMPILE_TEST
  17. config GENERIC_PINCONF
  18. bool
  19. select PINCONF
  20. config DEBUG_PINCTRL
  21. bool "Debug PINCTRL calls"
  22. depends on DEBUG_KERNEL
  23. help
  24. Say Y here to add some extra checks and diagnostics to PINCTRL calls.
  25. config PINCTRL_AMD
  26. bool "AMD GPIO pin control"
  27. depends on HAS_IOMEM
  28. depends on ACPI || COMPILE_TEST
  29. select GPIOLIB
  30. select GPIOLIB_IRQCHIP
  31. select PINMUX
  32. select PINCONF
  33. select GENERIC_PINCONF
  34. help
  35. The driver for memory mapped GPIO functionality on AMD platforms
  36. (x86 or arm). Most of the pins are usually muxed to some other
  37. functionality by firmware, so only a small amount is available
  38. for GPIO use.
  39. Requires ACPI/FDT device enumeration code to set up a platform
  40. device.
  41. config PINCTRL_APPLE_GPIO
  42. tristate "Apple SoC GPIO pin controller driver"
  43. depends on ARCH_APPLE
  44. select PINMUX
  45. select GPIOLIB
  46. select GPIOLIB_IRQCHIP
  47. select GENERIC_PINCTRL_GROUPS
  48. select GENERIC_PINMUX_FUNCTIONS
  49. select OF_GPIO
  50. help
  51. This is the driver for the GPIO controller found on Apple ARM SoCs,
  52. including M1.
  53. This driver can also be built as a module. If so, the module
  54. will be called pinctrl-apple-gpio.
  55. config PINCTRL_ARTPEC6
  56. bool "Axis ARTPEC-6 pin controller driver"
  57. depends on MACH_ARTPEC6
  58. select PINMUX
  59. select GENERIC_PINCONF
  60. help
  61. This is the driver for the Axis ARTPEC-6 pin controller. This driver
  62. supports pin function multiplexing as well as pin bias and drive
  63. strength configuration. Device tree integration instructions can be
  64. found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
  65. config PINCTRL_AS3722
  66. tristate "Pinctrl and GPIO driver for ams AS3722 PMIC"
  67. depends on MFD_AS3722 && GPIOLIB
  68. select PINMUX
  69. select GENERIC_PINCONF
  70. help
  71. AS3722 device supports the configuration of GPIO pins for different
  72. functionality. This driver supports the pinmux, push-pull and
  73. open drain configuration for the GPIO pins of AS3722 devices. It also
  74. supports the GPIO functionality through gpiolib.
  75. config PINCTRL_AT91
  76. bool "AT91 pinctrl driver"
  77. depends on OF
  78. depends on ARCH_AT91
  79. select PINMUX
  80. select PINCONF
  81. select GPIOLIB
  82. select OF_GPIO
  83. select GPIOLIB_IRQCHIP
  84. help
  85. Say Y here to enable the at91 pinctrl driver
  86. config PINCTRL_AT91PIO4
  87. bool "AT91 PIO4 pinctrl driver"
  88. depends on OF
  89. depends on HAS_IOMEM
  90. depends on ARCH_AT91 || COMPILE_TEST
  91. select PINMUX
  92. select GENERIC_PINCONF
  93. select GPIOLIB
  94. select GPIOLIB_IRQCHIP
  95. select OF_GPIO
  96. help
  97. Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
  98. controller available on sama5d2 SoC.
  99. config PINCTRL_AXP209
  100. tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
  101. depends on MFD_AXP20X
  102. depends on OF
  103. select PINMUX
  104. select GENERIC_PINCONF
  105. select GPIOLIB
  106. help
  107. AXP PMICs provides multiple GPIOs that can be muxed for different
  108. functions. This driver bundles a pinctrl driver to select the function
  109. muxing and a GPIO driver to handle the GPIO when the GPIO function is
  110. selected.
  111. Say Y to enable pinctrl and GPIO support for the AXP209 PMIC.
  112. config PINCTRL_BM1880
  113. bool "Bitmain BM1880 Pinctrl driver"
  114. depends on OF && (ARCH_BITMAIN || COMPILE_TEST)
  115. default ARCH_BITMAIN
  116. select PINMUX
  117. help
  118. Pinctrl driver for Bitmain BM1880 SoC.
  119. config PINCTRL_CY8C95X0
  120. tristate "Cypress CY8C95X0 I2C pinctrl and GPIO driver"
  121. depends on I2C
  122. select GPIOLIB
  123. select GPIOLIB_IRQCHIP
  124. select PINMUX
  125. select PINCONF
  126. select GENERIC_PINCONF
  127. select REGMAP_I2C
  128. help
  129. Support for 20/40/60 pin Cypress Cy8C95x0 pinctrl/gpio I2C expander.
  130. This driver can also be built as a module. If so, the module will be
  131. called pinctrl-cy8c95x0.
  132. config PINCTRL_DA850_PUPD
  133. tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups"
  134. depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST)
  135. select PINCONF
  136. select GENERIC_PINCONF
  137. help
  138. Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control
  139. pull-up and pull-down pin groups.
  140. config PINCTRL_DA9062
  141. tristate "Dialog Semiconductor DA9062 PMIC pinctrl and GPIO Support"
  142. depends on MFD_DA9062
  143. select GPIOLIB
  144. help
  145. The Dialog DA9062 PMIC provides multiple GPIOs that can be muxed for
  146. different functions. This driver bundles a pinctrl driver to select the
  147. function muxing and a GPIO driver to handle the GPIO when the GPIO
  148. function is selected.
  149. Say Y to enable pinctrl and GPIO support for the DA9062 PMIC.
  150. config PINCTRL_DIGICOLOR
  151. bool
  152. depends on OF && (ARCH_DIGICOLOR || COMPILE_TEST)
  153. select PINMUX
  154. select GENERIC_PINCONF
  155. config PINCTRL_EQUILIBRIUM
  156. tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
  157. depends on OF && HAS_IOMEM
  158. depends on X86 || COMPILE_TEST
  159. select PINMUX
  160. select PINCONF
  161. select GPIOLIB
  162. select GPIO_GENERIC
  163. select GPIOLIB_IRQCHIP
  164. select GENERIC_PINCONF
  165. select GENERIC_PINCTRL_GROUPS
  166. select GENERIC_PINMUX_FUNCTIONS
  167. help
  168. Equilibrium driver is a pinctrl and GPIO driver for Intel Lightning
  169. Mountain network processor SoC that supports both the GPIO and pin
  170. control frameworks. It provides interfaces to setup pin muxing, assign
  171. desired pin functions, configure GPIO attributes for LGM SoC pins.
  172. Pin muxing and pin config settings are retrieved from device tree.
  173. config PINCTRL_GEMINI
  174. bool
  175. depends on ARCH_GEMINI
  176. default ARCH_GEMINI
  177. select PINMUX
  178. select GENERIC_PINCONF
  179. select MFD_SYSCON
  180. config PINCTRL_INGENIC
  181. bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
  182. default MACH_INGENIC
  183. depends on OF
  184. depends on MIPS || COMPILE_TEST
  185. select GENERIC_PINCONF
  186. select GENERIC_PINCTRL_GROUPS
  187. select GENERIC_PINMUX_FUNCTIONS
  188. select GPIOLIB
  189. select GPIOLIB_IRQCHIP
  190. select REGMAP_MMIO
  191. config PINCTRL_K210
  192. bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
  193. depends on RISCV && SOC_CANAAN && OF
  194. select GENERIC_PINMUX_FUNCTIONS
  195. select GENERIC_PINCONF
  196. select GPIOLIB
  197. select OF_GPIO
  198. select REGMAP_MMIO
  199. default SOC_CANAAN
  200. help
  201. Add support for the Canaan Kendryte K210 RISC-V SOC Field
  202. Programmable IO Array (FPIOA) controller.
  203. config PINCTRL_KEEMBAY
  204. tristate "Pinctrl driver for Intel Keem Bay SoC"
  205. depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
  206. depends on HAS_IOMEM
  207. select PINMUX
  208. select PINCONF
  209. select GENERIC_PINCONF
  210. select GENERIC_PINCTRL_GROUPS
  211. select GENERIC_PINMUX_FUNCTIONS
  212. select GPIOLIB
  213. select GPIOLIB_IRQCHIP
  214. select GPIO_GENERIC
  215. help
  216. This selects pin control driver for the Intel Keem Bay SoC.
  217. It provides pin config functions such as pull-up, pull-down,
  218. interrupt, drive strength, sec lock, Schmitt trigger, slew
  219. rate control and direction control. This module will be
  220. called as pinctrl-keembay.
  221. config PINCTRL_LANTIQ
  222. bool
  223. depends on LANTIQ
  224. select PINMUX
  225. select PINCONF
  226. config PINCTRL_FALCON
  227. bool
  228. depends on SOC_FALCON
  229. depends on PINCTRL_LANTIQ
  230. config PINCTRL_XWAY
  231. bool
  232. depends on SOC_TYPE_XWAY
  233. depends on PINCTRL_LANTIQ
  234. config PINCTRL_LPC18XX
  235. bool "NXP LPC18XX/43XX SCU pinctrl driver"
  236. depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
  237. default ARCH_LPC18XX
  238. select PINMUX
  239. select GENERIC_PINCONF
  240. help
  241. Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
  242. config PINCTRL_MAX77620
  243. tristate "MAX77620/MAX20024 Pincontrol support"
  244. depends on MFD_MAX77620 && OF
  245. select PINMUX
  246. select GENERIC_PINCONF
  247. help
  248. Say Y here to enable Pin control support for Maxim MAX77620 PMIC.
  249. This PMIC has 8 GPIO pins that work as GPIO as well as special
  250. function in alternate mode. This driver also configure push-pull,
  251. open drain, FPS slots etc.
  252. config PINCTRL_MCP23S08_I2C
  253. tristate
  254. select REGMAP_I2C
  255. config PINCTRL_MCP23S08_SPI
  256. tristate
  257. select REGMAP_SPI
  258. config PINCTRL_MCP23S08
  259. tristate "Microchip MCP23xxx I/O expander"
  260. depends on SPI_MASTER || I2C
  261. select GPIOLIB
  262. select GPIOLIB_IRQCHIP
  263. select GENERIC_PINCONF
  264. select PINCTRL_MCP23S08_I2C if I2C
  265. select PINCTRL_MCP23S08_SPI if SPI_MASTER
  266. help
  267. SPI/I2C driver for Microchip MCP23S08 / MCP23S17 / MCP23S18 /
  268. MCP23008 / MCP23017 / MCP23018 I/O expanders.
  269. This provides a GPIO interface supporting inputs and outputs and a
  270. corresponding interrupt-controller.
  271. config PINCTRL_MICROCHIP_SGPIO
  272. tristate "Pinctrl driver for Microsemi/Microchip Serial GPIO"
  273. depends on OF
  274. depends on HAS_IOMEM
  275. select GPIOLIB
  276. select GPIOLIB_IRQCHIP
  277. select GENERIC_PINCONF
  278. select GENERIC_PINCTRL_GROUPS
  279. select GENERIC_PINMUX_FUNCTIONS
  280. select OF_GPIO
  281. help
  282. Support for the serial GPIO interface used on Microsemi and
  283. Microchip SoCs. By using a serial interface, the SIO
  284. controller significantly extends the number of available
  285. GPIOs with a minimum number of additional pins on the
  286. device. The primary purpose of the SIO controller is to
  287. connect control signals from SFP modules and to act as an
  288. LED controller.
  289. If compiled as a module, the module name will be
  290. pinctrl-microchip-sgpio.
  291. config PINCTRL_OCELOT
  292. tristate "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
  293. depends on OF
  294. depends on HAS_IOMEM
  295. select GPIOLIB
  296. select GPIOLIB_IRQCHIP
  297. select GENERIC_PINCONF
  298. select GENERIC_PINCTRL_GROUPS
  299. select GENERIC_PINMUX_FUNCTIONS
  300. select OF_GPIO
  301. select REGMAP_MMIO
  302. help
  303. Support for the internal GPIO interfaces on Microsemi Ocelot and
  304. Jaguar2 SoCs.
  305. If conpiled as a module, the module name will be pinctrl-ocelot.
  306. config PINCTRL_OXNAS
  307. bool
  308. depends on OF
  309. select PINMUX
  310. select PINCONF
  311. select GENERIC_PINCONF
  312. select GPIOLIB
  313. select OF_GPIO
  314. select GPIOLIB_IRQCHIP
  315. select MFD_SYSCON
  316. config PINCTRL_PALMAS
  317. tristate "Pinctrl driver for the PALMAS Series MFD devices"
  318. depends on OF && MFD_PALMAS
  319. select PINMUX
  320. select GENERIC_PINCONF
  321. help
  322. Palmas device supports the configuration of pins for different
  323. functionality. This driver supports the pinmux, push-pull and
  324. open drain configuration for the Palmas series devices like
  325. TPS65913, TPS80036 etc.
  326. config PINCTRL_PIC32
  327. bool "Microchip PIC32 pin controller driver"
  328. depends on OF
  329. depends on MACH_PIC32
  330. select PINMUX
  331. select GENERIC_PINCONF
  332. select GPIOLIB_IRQCHIP
  333. select OF_GPIO
  334. help
  335. This is the pin controller and gpio driver for Microchip PIC32
  336. microcontrollers. This option is selected automatically when specific
  337. machine and arch are selected to build.
  338. config PINCTRL_PIC32MZDA
  339. def_bool y if PIC32MZDA
  340. select PINCTRL_PIC32
  341. config PINCTRL_PISTACHIO
  342. bool "IMG Pistachio SoC pinctrl driver"
  343. depends on OF && (MIPS || COMPILE_TEST)
  344. depends on GPIOLIB
  345. select PINMUX
  346. select GENERIC_PINCONF
  347. select GPIOLIB_IRQCHIP
  348. select OF_GPIO
  349. help
  350. This support pinctrl and GPIO driver for IMG Pistachio SoC.
  351. config PINCTRL_RK805
  352. tristate "Pinctrl and GPIO driver for RK805 PMIC"
  353. depends on MFD_RK808
  354. select GPIOLIB
  355. select PINMUX
  356. select GENERIC_PINCONF
  357. help
  358. This selects the pinctrl driver for RK805.
  359. config PINCTRL_ROCKCHIP
  360. tristate "Rockchip gpio and pinctrl driver"
  361. depends on ARCH_ROCKCHIP || COMPILE_TEST
  362. depends on OF
  363. select GPIOLIB
  364. select PINMUX
  365. select GENERIC_PINCONF
  366. select GENERIC_IRQ_CHIP
  367. select MFD_SYSCON
  368. select OF_GPIO
  369. default ARCH_ROCKCHIP
  370. help
  371. This support pinctrl and GPIO driver for Rockchip SoCs.
  372. config PINCTRL_SINGLE
  373. tristate "One-register-per-pin type device tree based pinctrl driver"
  374. depends on OF
  375. depends on HAS_IOMEM
  376. select GENERIC_PINCTRL_GROUPS
  377. select GENERIC_PINMUX_FUNCTIONS
  378. select GENERIC_PINCONF
  379. help
  380. This selects the device tree based generic pinctrl driver.
  381. config PINCTRL_ST
  382. bool
  383. depends on OF
  384. select PINMUX
  385. select PINCONF
  386. select GPIOLIB_IRQCHIP
  387. config PINCTRL_STMFX
  388. tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
  389. depends on I2C
  390. depends on OF_GPIO
  391. select GENERIC_PINCONF
  392. select GPIOLIB_IRQCHIP
  393. select MFD_STMFX
  394. help
  395. Driver for STMicroelectronics Multi-Function eXpander (STMFX)
  396. GPIO expander.
  397. This provides a GPIO interface supporting inputs and outputs,
  398. and configuring push-pull, open-drain, and can also be used as
  399. interrupt-controller.
  400. config PINCTRL_SX150X
  401. tristate "Semtech SX150x I2C GPIO expander pinctrl driver"
  402. depends on I2C=y
  403. select PINMUX
  404. select PINCONF
  405. select GENERIC_PINCONF
  406. select GPIOLIB
  407. select GPIOLIB_IRQCHIP
  408. select REGMAP
  409. help
  410. Say Y here to provide support for Semtech SX150x-series I2C
  411. GPIO expanders as pinctrl module.
  412. Compatible models include:
  413. - 8 bits: sx1508q, sx1502q
  414. - 16 bits: sx1509q, sx1506q
  415. config PINCTRL_TB10X
  416. bool
  417. depends on OF && ARC_PLAT_TB10X
  418. select GPIOLIB
  419. config PINCTRL_THUNDERBAY
  420. tristate "Generic pinctrl and GPIO driver for Intel Thunder Bay SoC"
  421. depends on ARCH_THUNDERBAY || (ARM64 && COMPILE_TEST)
  422. depends on HAS_IOMEM
  423. select PINMUX
  424. select PINCONF
  425. select GENERIC_PINCONF
  426. select GENERIC_PINCTRL_GROUPS
  427. select GENERIC_PINMUX_FUNCTIONS
  428. select GPIOLIB
  429. select GPIOLIB_IRQCHIP
  430. select GPIO_GENERIC
  431. help
  432. This selects pin control driver for the Intel Thunder Bay SoC.
  433. It provides pin config functions such as pull-up, pull-down,
  434. interrupt, drive strength, sec lock, Schmitt trigger, slew
  435. rate control and direction control. This module will be
  436. called as pinctrl-thunderbay.
  437. config PINCTRL_ZYNQ
  438. bool "Pinctrl driver for Xilinx Zynq"
  439. depends on ARCH_ZYNQ
  440. select PINMUX
  441. select GENERIC_PINCONF
  442. help
  443. This selects the pinctrl driver for Xilinx Zynq.
  444. config PINCTRL_ZYNQMP
  445. tristate "Pinctrl driver for Xilinx ZynqMP"
  446. depends on ZYNQMP_FIRMWARE
  447. select PINMUX
  448. select GENERIC_PINCONF
  449. default ZYNQMP_FIRMWARE
  450. help
  451. This selects the pinctrl driver for Xilinx ZynqMP platform.
  452. This driver will query the pin information from the firmware
  453. and allow configuring the pins.
  454. Configuration can include the mux function to select on those
  455. pin(s)/group(s), and various pin configuration parameters
  456. such as pull-up, slew rate, etc.
  457. This driver can also be built as a module. If so, the module
  458. will be called pinctrl-zynqmp.
  459. source "drivers/pinctrl/actions/Kconfig"
  460. source "drivers/pinctrl/aspeed/Kconfig"
  461. source "drivers/pinctrl/bcm/Kconfig"
  462. source "drivers/pinctrl/berlin/Kconfig"
  463. source "drivers/pinctrl/cirrus/Kconfig"
  464. source "drivers/pinctrl/freescale/Kconfig"
  465. source "drivers/pinctrl/intel/Kconfig"
  466. source "drivers/pinctrl/mediatek/Kconfig"
  467. source "drivers/pinctrl/meson/Kconfig"
  468. source "drivers/pinctrl/mvebu/Kconfig"
  469. source "drivers/pinctrl/nomadik/Kconfig"
  470. source "drivers/pinctrl/nuvoton/Kconfig"
  471. source "drivers/pinctrl/pxa/Kconfig"
  472. source "drivers/pinctrl/qcom/Kconfig"
  473. source "drivers/pinctrl/ralink/Kconfig"
  474. source "drivers/pinctrl/renesas/Kconfig"
  475. source "drivers/pinctrl/samsung/Kconfig"
  476. source "drivers/pinctrl/spear/Kconfig"
  477. source "drivers/pinctrl/sprd/Kconfig"
  478. source "drivers/pinctrl/starfive/Kconfig"
  479. source "drivers/pinctrl/stm32/Kconfig"
  480. source "drivers/pinctrl/sunplus/Kconfig"
  481. source "drivers/pinctrl/sunxi/Kconfig"
  482. source "drivers/pinctrl/tegra/Kconfig"
  483. source "drivers/pinctrl/ti/Kconfig"
  484. source "drivers/pinctrl/uniphier/Kconfig"
  485. source "drivers/pinctrl/visconti/Kconfig"
  486. source "drivers/pinctrl/vt8500/Kconfig"
  487. endif