phy-qcom-ufs-qmp-v4.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #ifndef UFS_QCOM_PHY_QMP_V4_H_
  6. #define UFS_QCOM_PHY_QMP_V4_H_
  7. #include "phy-qcom-ufs-i.h"
  8. /* QCOM UFS PHY control registers */
  9. #define COM_BASE 0x000
  10. #define COM_SIZE 0x1C0
  11. #define PHY_BASE 0xC00
  12. #define PHY_SIZE 0x200
  13. #define PCS2_BASE 0x200
  14. #define PCS2_SIZE 0x40
  15. #define TX_BASE(n) (0x400 + (0x400 * n))
  16. #define TX_SIZE 0x16C
  17. #define RX_BASE(n) (0x600 + (0x400 * n))
  18. #define RX_SIZE 0x200
  19. #define COM_OFF(x) (COM_BASE + x)
  20. #define PHY_OFF(x) (PHY_BASE + x)
  21. #define TX_OFF(n, x) (TX_BASE(n) + x)
  22. #define RX_OFF(n, x) (RX_BASE(n) + x)
  23. /* UFS PHY QSERDES COM registers */
  24. #define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x94)
  25. #define QSERDES_COM_HSCLK_SEL COM_OFF(0x158)
  26. #define QSERDES_COM_HSCLK_HS_SWITCH_SEL COM_OFF(0x15C)
  27. #define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xA4)
  28. #define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x10C)
  29. #define QSERDES_COM_PLL_IVCO COM_OFF(0x58)
  30. #define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x124)
  31. #define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL COM_OFF(0x1BC)
  32. #define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xBC)
  33. #define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x74)
  34. #define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x7C)
  35. #define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x84)
  36. #define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0xAC)
  37. #define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0xB0)
  38. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 COM_OFF(0x1AC)
  39. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 COM_OFF(0x1B0)
  40. #define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xC4)
  41. #define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x78)
  42. #define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x80)
  43. #define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x88)
  44. #define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0xB4)
  45. #define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0xB8)
  46. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 COM_OFF(0x1B4)
  47. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 COM_OFF(0x1B8)
  48. #define QSERDES_COM_CMN_IPTRIM COM_OFF(0x60)
  49. /* UFS PHY registers */
  50. #define UFS_PHY_PHY_START PHY_OFF(0x00)
  51. #define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
  52. #define UFS_PHY_SW_RESET PHY_OFF(0x08)
  53. #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x180)
  54. #define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x148)
  55. #define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1E0)
  56. #define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x158)
  57. #define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x30)
  58. #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x38)
  59. #define UFS_PHY_TX_MID_TERM_CTRL1 PHY_OFF(0x1D8)
  60. #define UFS_PHY_DEBUG_BUS_CLKSEL PHY_OFF(0x124)
  61. #define UFS_PHY_PLL_CNTL PHY_OFF(0x2C)
  62. #define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x0C)
  63. #define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x10)
  64. #define UFS_PHY_TX_PWM_GEAR_BAND PHY_OFF(0x160)
  65. #define UFS_PHY_TX_HS_GEAR_BAND PHY_OFF(0x168)
  66. #define UFS_PHY_TX_HSGEAR_CAPABILITY PHY_OFF(0x74)
  67. #define UFS_PHY_RX_HSGEAR_CAPABILITY PHY_OFF(0xB4)
  68. #define UFS_PHY_RX_MIN_HIBERN8_TIME PHY_OFF(0x150)
  69. #define UFS_PHY_BIST_FIXED_PAT_CTRL PHY_OFF(0x60)
  70. /* UFS PHY TX registers */
  71. #define QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(0, 0xD8)
  72. #define QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(0, 0xDC)
  73. #define QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(0, 0xE0)
  74. #define QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(0, 0xE4)
  75. #define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x84)
  76. #define QSERDES_TX0_TRAN_DRVR_EMP_EN TX_OFF(0, 0xB8)
  77. #define QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(1, 0xD8)
  78. #define QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(1, 0xDC)
  79. #define QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(1, 0xE0)
  80. #define QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(1, 0xE4)
  81. #define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x84)
  82. #define QSERDES_TX1_TRAN_DRVR_EMP_EN TX_OFF(1, 0xB8)
  83. /* UFS PHY RX registers */
  84. #define QSERDES_RX0_SIGDET_LVL RX_OFF(0, 0x120)
  85. #define QSERDES_RX0_SIGDET_CNTRL RX_OFF(0, 0x11C)
  86. #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x124)
  87. #define QSERDES_RX0_RX_BAND RX_OFF(0, 0x128)
  88. #define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x30)
  89. #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(0, 0x34)
  90. #define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0x44)
  91. #define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW RX_OFF(0, 0x3C)
  92. #define QSERDES_RX0_UCDR_PI_CTRL2 RX_OFF(0, 0x48)
  93. #define QSERDES_RX0_RX_TERM_BW RX_OFF(0, 0x80)
  94. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xEC)
  95. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(0, 0xF0)
  96. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0xF4)
  97. #define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 RX_OFF(0, 0x114)
  98. #define QSERDES_RX0_RX_IDAC_MEASURE_TIME RX_OFF(0, 0x100)
  99. #define QSERDES_RX0_RX_IDAC_TSETTLE_LOW RX_OFF(0, 0xF8)
  100. #define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH RX_OFF(0, 0xFC)
  101. #define QSERDES_RX0_RX_MODE_00_LOW RX_OFF(0, 0x170)
  102. #define QSERDES_RX0_RX_MODE_00_HIGH RX_OFF(0, 0x174)
  103. #define QSERDES_RX0_RX_MODE_00_HIGH2 RX_OFF(0, 0x178)
  104. #define QSERDES_RX0_RX_MODE_00_HIGH3 RX_OFF(0, 0x17C)
  105. #define QSERDES_RX0_RX_MODE_00_HIGH4 RX_OFF(0, 0x180)
  106. #define QSERDES_RX0_RX_MODE_01_LOW RX_OFF(0, 0x184)
  107. #define QSERDES_RX0_RX_MODE_01_HIGH RX_OFF(0, 0x188)
  108. #define QSERDES_RX0_RX_MODE_01_HIGH2 RX_OFF(0, 0x18C)
  109. #define QSERDES_RX0_RX_MODE_01_HIGH3 RX_OFF(0, 0x190)
  110. #define QSERDES_RX0_RX_MODE_01_HIGH4 RX_OFF(0, 0x194)
  111. #define QSERDES_RX0_RX_MODE_10_LOW RX_OFF(0, 0x198)
  112. #define QSERDES_RX0_RX_MODE_10_HIGH RX_OFF(0, 0x19C)
  113. #define QSERDES_RX0_RX_MODE_10_HIGH2 RX_OFF(0, 0x1A0)
  114. #define QSERDES_RX0_RX_MODE_10_HIGH3 RX_OFF(0, 0x1A4)
  115. #define QSERDES_RX0_RX_MODE_10_HIGH4 RX_OFF(0, 0x1A8)
  116. #define QSERDES_RX0_DCC_CTRL1 RX_OFF(0, 0x1BC)
  117. #define QSERDES_RX0_AC_JTAG_ENABLE RX_OFF(0, 0x68)
  118. #define QSERDES_RX0_UCDR_FO_GAIN RX_OFF(0, 0x08)
  119. #define QSERDES_RX0_UCDR_SO_GAIN RX_OFF(0, 0x14)
  120. #define QSERDES_RX0_AC_JTAG_MODE RX_OFF(0, 0x78)
  121. #define QSERDES_RX1_SIGDET_LVL RX_OFF(1, 0x120)
  122. #define QSERDES_RX1_SIGDET_CNTRL RX_OFF(1, 0x11C)
  123. #define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL RX_OFF(1, 0x124)
  124. #define QSERDES_RX1_RX_BAND RX_OFF(1, 0x128)
  125. #define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN RX_OFF(1, 0x30)
  126. #define QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(1, 0x34)
  127. #define QSERDES_RX1_UCDR_PI_CONTROLS RX_OFF(1, 0x44)
  128. #define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW RX_OFF(1, 0x3C)
  129. #define QSERDES_RX1_UCDR_PI_CTRL2 RX_OFF(1, 0x48)
  130. #define QSERDES_RX1_RX_TERM_BW RX_OFF(1, 0x80)
  131. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(1, 0xEC)
  132. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(1, 0xF0)
  133. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(1, 0xF4)
  134. #define QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2 RX_OFF(1, 0x114)
  135. #define QSERDES_RX1_RX_IDAC_MEASURE_TIME RX_OFF(1, 0x100)
  136. #define QSERDES_RX1_RX_IDAC_TSETTLE_LOW RX_OFF(1, 0xF8)
  137. #define QSERDES_RX1_RX_IDAC_TSETTLE_HIGH RX_OFF(1, 0xFC)
  138. #define QSERDES_RX1_RX_MODE_00_LOW RX_OFF(1, 0x170)
  139. #define QSERDES_RX1_RX_MODE_00_HIGH RX_OFF(1, 0x174)
  140. #define QSERDES_RX1_RX_MODE_00_HIGH2 RX_OFF(1, 0x178)
  141. #define QSERDES_RX1_RX_MODE_00_HIGH3 RX_OFF(1, 0x17C)
  142. #define QSERDES_RX1_RX_MODE_00_HIGH4 RX_OFF(1, 0x180)
  143. #define QSERDES_RX1_RX_MODE_01_LOW RX_OFF(1, 0x184)
  144. #define QSERDES_RX1_RX_MODE_01_HIGH RX_OFF(1, 0x188)
  145. #define QSERDES_RX1_RX_MODE_01_HIGH2 RX_OFF(1, 0x18C)
  146. #define QSERDES_RX1_RX_MODE_01_HIGH3 RX_OFF(1, 0x190)
  147. #define QSERDES_RX1_RX_MODE_01_HIGH4 RX_OFF(1, 0x194)
  148. #define QSERDES_RX1_RX_MODE_10_LOW RX_OFF(1, 0x198)
  149. #define QSERDES_RX1_RX_MODE_10_HIGH RX_OFF(1, 0x19C)
  150. #define QSERDES_RX1_RX_MODE_10_HIGH2 RX_OFF(1, 0x1A0)
  151. #define QSERDES_RX1_RX_MODE_10_HIGH3 RX_OFF(1, 0x1A4)
  152. #define QSERDES_RX1_RX_MODE_10_HIGH4 RX_OFF(1, 0x1A8)
  153. #define QSERDES_RX1_DCC_CTRL1 RX_OFF(1, 0x1BC)
  154. #define QSERDES_RX1_AC_JTAG_ENABLE RX_OFF(1, 0x68)
  155. #define QSERDES_RX1_UCDR_FO_GAIN RX_OFF(1, 0x08)
  156. #define QSERDES_RX1_UCDR_SO_GAIN RX_OFF(1, 0x14)
  157. #define QSERDES_RX1_AC_JTAG_MODE RX_OFF(1, 0x78)
  158. #define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
  159. /*
  160. * This structure represents the v4 specific phy.
  161. * common_cfg MUST remain the first field in this structure
  162. * in case extra fields are added. This way, when calling
  163. * get_ufs_qcom_phy() of generic phy, we can extract the
  164. * common phy structure (struct ufs_qcom_phy) out of it
  165. * regardless of the relevant specific phy.
  166. */
  167. struct ufs_qcom_phy_qmp_v4 {
  168. struct ufs_qcom_phy common_cfg;
  169. };
  170. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
  171. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
  172. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9),
  173. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x11),
  174. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00),
  175. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
  176. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x02),
  177. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
  178. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
  179. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
  180. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
  181. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
  182. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
  183. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
  184. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
  185. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
  186. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xAC),
  187. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
  188. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
  189. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
  190. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
  191. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
  192. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
  193. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
  194. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xDD),
  195. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
  196. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
  197. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
  198. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
  199. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
  200. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x05),
  201. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TRAN_DRVR_EMP_EN, 0x0C),
  202. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
  203. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
  204. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
  205. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_BAND, 0x18),
  206. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0A),
  207. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
  208. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),
  209. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
  210. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x80),
  211. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C),
  212. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
  213. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x1B),
  214. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
  215. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
  216. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
  217. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
  218. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x10),
  219. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xC0),
  220. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
  221. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x36),
  222. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0x36),
  223. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xF6),
  224. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x3B),
  225. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3D),
  226. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_LOW, 0xE0),
  227. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH, 0xC8),
  228. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH2, 0xC8),
  229. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH3, 0x3B),
  230. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH4, 0xB1),
  231. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_LOW, 0xE0),
  232. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH, 0xC8),
  233. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH2, 0xC8),
  234. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B),
  235. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1),
  236. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D),
  237. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
  238. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
  239. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
  240. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_DEBUG_BUS_CLKSEL, 0x1F),
  241. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF),
  242. };
  243. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g3[] = {
  244. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x03),
  245. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
  246. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xD8),
  247. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWM_GEAR_BAND, 0xAA),
  248. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06),
  249. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
  250. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
  251. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C),
  252. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
  253. };
  254. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g4[] = {
  255. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x81),
  256. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x6F),
  257. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x20),
  258. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0x80),
  259. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x01),
  260. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x3F),
  261. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0xFF),
  262. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xFF),
  263. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x7F),
  264. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x6D),
  265. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C),
  266. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x10),
  267. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_BIST_FIXED_PAT_CTRL, 0x0A),
  268. };
  269. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2_g3[] = {
  270. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x35),
  271. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  272. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
  273. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x6D),
  274. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0x6D),
  275. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xED),
  276. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3C),
  277. };
  278. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2_g4[] = {
  279. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x75),
  280. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  281. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
  282. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x6C),
  283. };
  284. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
  285. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
  286. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
  287. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
  288. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
  289. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x05),
  290. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TRAN_DRVR_EMP_EN, 0x0C),
  291. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
  292. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
  293. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
  294. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_BAND, 0x18),
  295. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0A),
  296. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
  297. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0xF1),
  298. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
  299. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x80),
  300. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C),
  301. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),
  302. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x1B),
  303. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),
  304. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),
  305. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
  306. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
  307. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x10),
  308. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0xC0),
  309. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x00),
  310. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x36),
  311. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0x36),
  312. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xF6),
  313. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x3B),
  314. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3D),
  315. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_LOW, 0xE0),
  316. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH, 0xC8),
  317. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH2, 0xC8),
  318. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH3, 0x3B),
  319. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH4, 0xB1),
  320. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_LOW, 0xE0),
  321. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH, 0xC8),
  322. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH2, 0xC8),
  323. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B),
  324. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1),
  325. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
  326. };
  327. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2_g3[] = {
  328. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x35),
  329. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  330. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
  331. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x6D),
  332. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0x6D),
  333. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xED),
  334. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3C),
  335. };
  336. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2_g4[] = {
  337. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x75),
  338. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  339. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
  340. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x6C),
  341. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x81),
  342. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x6F),
  343. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x20),
  344. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0x80),
  345. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x01),
  346. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x3F),
  347. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0xFF),
  348. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xFF),
  349. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x7F),
  350. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x6D),
  351. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C),
  352. };
  353. static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
  354. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x06),
  355. };
  356. #endif