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phy-qcom-ufs-qmp-v4.h

phy-qcom-ufs-qmp-v4.h 19 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef UFS_QCOM_PHY_QMP_V4_H_
    7. 

  7. #define UFS_QCOM_PHY_QMP_V4_H_
    8. 

  8. 

  9. #include "phy-qcom-ufs-i.h"
    10. 

  10. 

  11. /* QCOM UFS PHY control registers */
    12. 

  12. #define COM_BASE	0x000
    13. 

  13. #define COM_SIZE	0x1C0
    14. 

  14. #define PHY_BASE	0xC00
    15. 

  15. #define PHY_SIZE	0x200
    16. 

  16. #define PCS2_BASE	0x200
    17. 

  17. #define PCS2_SIZE	0x40
    18. 

  18. #define TX_BASE(n)	(0x400 + (0x400 * n))
    19. 

  19. #define TX_SIZE		0x16C
    20. 

  20. #define RX_BASE(n)	(0x600 + (0x400 * n))
    21. 

  21. #define RX_SIZE		0x200
    22. 

  22. #define COM_OFF(x)	(COM_BASE + x)
    23. 

  23. #define PHY_OFF(x)	(PHY_BASE + x)
    24. 

  24. #define TX_OFF(n, x)	(TX_BASE(n) + x)
    25. 

  25. #define RX_OFF(n, x)	(RX_BASE(n) + x)
    26. 

  26. 

  27. /* UFS PHY QSERDES COM registers */
    28. 

  28. #define QSERDES_COM_SYSCLK_EN_SEL		COM_OFF(0x94)
    29. 

  29. #define QSERDES_COM_HSCLK_SEL			COM_OFF(0x158)
    30. 

  30. #define QSERDES_COM_HSCLK_HS_SWITCH_SEL		COM_OFF(0x15C)
    31. 

  31. #define QSERDES_COM_LOCK_CMP_EN			COM_OFF(0xA4)
    32. 

  32. #define QSERDES_COM_VCO_TUNE_MAP		COM_OFF(0x10C)
    33. 

  33. #define QSERDES_COM_PLL_IVCO			COM_OFF(0x58)
    34. 

  34. #define QSERDES_COM_VCO_TUNE_INITVAL2		COM_OFF(0x124)
    35. 

  35. #define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	COM_OFF(0x1BC)
    36. 

  36. #define QSERDES_COM_DEC_START_MODE0		COM_OFF(0xBC)
    37. 

  37. #define QSERDES_COM_CP_CTRL_MODE0		COM_OFF(0x74)
    38. 

  38. #define QSERDES_COM_PLL_RCTRL_MODE0		COM_OFF(0x7C)
    39. 

  39. #define QSERDES_COM_PLL_CCTRL_MODE0		COM_OFF(0x84)
    40. 

  40. #define QSERDES_COM_LOCK_CMP1_MODE0		COM_OFF(0xAC)
    41. 

  41. #define QSERDES_COM_LOCK_CMP2_MODE0		COM_OFF(0xB0)
    42. 

  42. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	COM_OFF(0x1AC)
    43. 

  43. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	COM_OFF(0x1B0)
    44. 

  44. #define QSERDES_COM_DEC_START_MODE1		COM_OFF(0xC4)
    45. 

  45. #define QSERDES_COM_CP_CTRL_MODE1		COM_OFF(0x78)
    46. 

  46. #define QSERDES_COM_PLL_RCTRL_MODE1		COM_OFF(0x80)
    47. 

  47. #define QSERDES_COM_PLL_CCTRL_MODE1		COM_OFF(0x88)
    48. 

  48. #define QSERDES_COM_LOCK_CMP1_MODE1		COM_OFF(0xB4)
    49. 

  49. #define QSERDES_COM_LOCK_CMP2_MODE1		COM_OFF(0xB8)
    50. 

  50. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	COM_OFF(0x1B4)
    51. 

  51. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	COM_OFF(0x1B8)
    52. 

  52. #define QSERDES_COM_CMN_IPTRIM			COM_OFF(0x60)
    53. 

  53. 

  54. /* UFS PHY registers */
    55. 

  55. #define UFS_PHY_PHY_START			PHY_OFF(0x00)
    56. 

  56. #define UFS_PHY_POWER_DOWN_CONTROL		PHY_OFF(0x04)
    57. 

  57. #define UFS_PHY_SW_RESET			PHY_OFF(0x08)
    58. 

  58. #define UFS_PHY_PCS_READY_STATUS		PHY_OFF(0x180)
    59. 

  59. #define UFS_PHY_LINECFG_DISABLE			PHY_OFF(0x148)
    60. 

  60. #define UFS_PHY_MULTI_LANE_CTRL1		PHY_OFF(0x1E0)
    61. 

  61. #define UFS_PHY_RX_SIGDET_CTRL2			PHY_OFF(0x158)
    62. 

  62. #define UFS_PHY_TX_LARGE_AMP_DRV_LVL		PHY_OFF(0x30)
    63. 

  63. #define UFS_PHY_TX_SMALL_AMP_DRV_LVL		PHY_OFF(0x38)
    64. 

  64. #define UFS_PHY_TX_MID_TERM_CTRL1		PHY_OFF(0x1D8)
    65. 

  65. #define UFS_PHY_DEBUG_BUS_CLKSEL		PHY_OFF(0x124)
    66. 

  66. #define UFS_PHY_PLL_CNTL			PHY_OFF(0x2C)
    67. 

  67. #define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB	PHY_OFF(0x0C)
    68. 

  68. #define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB	PHY_OFF(0x10)
    69. 

  69. #define UFS_PHY_TX_PWM_GEAR_BAND		PHY_OFF(0x160)
    70. 

  70. #define UFS_PHY_TX_HS_GEAR_BAND			PHY_OFF(0x168)
    71. 

  71. #define UFS_PHY_TX_HSGEAR_CAPABILITY		PHY_OFF(0x74)
    72. 

  72. #define UFS_PHY_RX_HSGEAR_CAPABILITY		PHY_OFF(0xB4)
    73. 

  73. #define UFS_PHY_RX_MIN_HIBERN8_TIME		PHY_OFF(0x150)
    74. 

  74. #define UFS_PHY_BIST_FIXED_PAT_CTRL		PHY_OFF(0x60)
    75. 

  75. 

  76. /* UFS PHY TX registers */
    77. 

  77. #define QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1	TX_OFF(0, 0xD8)
    78. 

  78. #define QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1	TX_OFF(0, 0xDC)
    79. 

  79. #define QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1	TX_OFF(0, 0xE0)
    80. 

  80. #define QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1	TX_OFF(0, 0xE4)
    81. 

  81. #define QSERDES_TX0_LANE_MODE_1			TX_OFF(0, 0x84)
    82. 

  82. #define QSERDES_TX0_TRAN_DRVR_EMP_EN		TX_OFF(0, 0xB8)
    83. 

  83. 

  84. #define QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1	TX_OFF(1, 0xD8)
    85. 

  85. #define QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1	TX_OFF(1, 0xDC)
    86. 

  86. #define QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1	TX_OFF(1, 0xE0)
    87. 

  87. #define QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1	TX_OFF(1, 0xE4)
    88. 

  88. #define QSERDES_TX1_LANE_MODE_1			TX_OFF(1, 0x84)
    89. 

  89. #define QSERDES_TX1_TRAN_DRVR_EMP_EN		TX_OFF(1, 0xB8)
    90. 

  90. 

  91. /* UFS PHY RX registers */
    92. 

  92. #define QSERDES_RX0_SIGDET_LVL				RX_OFF(0, 0x120)
    93. 

  93. #define QSERDES_RX0_SIGDET_CNTRL			RX_OFF(0, 0x11C)
    94. 

  94. #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL		RX_OFF(0, 0x124)
    95. 

  95. #define QSERDES_RX0_RX_BAND				RX_OFF(0, 0x128)
    96. 

  96. #define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN		RX_OFF(0, 0x30)
    97. 

  97. #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE	RX_OFF(0, 0x34)
    98. 

  98. #define QSERDES_RX0_UCDR_PI_CONTROLS			RX_OFF(0, 0x44)
    99. 

  99. #define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW		RX_OFF(0, 0x3C)
    100. 

  100. #define QSERDES_RX0_UCDR_PI_CTRL2			RX_OFF(0, 0x48)
    101. 

  101. #define QSERDES_RX0_RX_TERM_BW				RX_OFF(0, 0x80)
    102. 

  102. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2		RX_OFF(0, 0xEC)
    103. 

  103. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3		RX_OFF(0, 0xF0)
    104. 

  104. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4		RX_OFF(0, 0xF4)
    105. 

  105. #define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2		RX_OFF(0, 0x114)
    106. 

  106. #define QSERDES_RX0_RX_IDAC_MEASURE_TIME		RX_OFF(0, 0x100)
    107. 

  107. #define QSERDES_RX0_RX_IDAC_TSETTLE_LOW			RX_OFF(0, 0xF8)
    108. 

  108. #define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH		RX_OFF(0, 0xFC)
    109. 

  109. #define QSERDES_RX0_RX_MODE_00_LOW			RX_OFF(0, 0x170)
    110. 

  110. #define QSERDES_RX0_RX_MODE_00_HIGH			RX_OFF(0, 0x174)
    111. 

  111. #define QSERDES_RX0_RX_MODE_00_HIGH2			RX_OFF(0, 0x178)
    112. 

  112. #define QSERDES_RX0_RX_MODE_00_HIGH3			RX_OFF(0, 0x17C)
    113. 

  113. #define QSERDES_RX0_RX_MODE_00_HIGH4			RX_OFF(0, 0x180)
    114. 

  114. #define QSERDES_RX0_RX_MODE_01_LOW			RX_OFF(0, 0x184)
    115. 

  115. #define QSERDES_RX0_RX_MODE_01_HIGH			RX_OFF(0, 0x188)
    116. 

  116. #define QSERDES_RX0_RX_MODE_01_HIGH2			RX_OFF(0, 0x18C)
    117. 

  117. #define QSERDES_RX0_RX_MODE_01_HIGH3			RX_OFF(0, 0x190)
    118. 

  118. #define QSERDES_RX0_RX_MODE_01_HIGH4			RX_OFF(0, 0x194)
    119. 

  119. #define QSERDES_RX0_RX_MODE_10_LOW			RX_OFF(0, 0x198)
    120. 

  120. #define QSERDES_RX0_RX_MODE_10_HIGH			RX_OFF(0, 0x19C)
    121. 

  121. #define QSERDES_RX0_RX_MODE_10_HIGH2			RX_OFF(0, 0x1A0)
    122. 

  122. #define QSERDES_RX0_RX_MODE_10_HIGH3			RX_OFF(0, 0x1A4)
    123. 

  123. #define QSERDES_RX0_RX_MODE_10_HIGH4			RX_OFF(0, 0x1A8)
    124. 

  124. #define QSERDES_RX0_DCC_CTRL1				RX_OFF(0, 0x1BC)
    125. 

  125. #define QSERDES_RX0_AC_JTAG_ENABLE			RX_OFF(0, 0x68)
    126. 

  126. #define QSERDES_RX0_UCDR_FO_GAIN			RX_OFF(0, 0x08)
    127. 

  127. #define QSERDES_RX0_UCDR_SO_GAIN			RX_OFF(0, 0x14)
    128. 

  128. #define QSERDES_RX0_AC_JTAG_MODE			RX_OFF(0, 0x78)
    129. 

  129. 

  130. #define QSERDES_RX1_SIGDET_LVL				RX_OFF(1, 0x120)
    131. 

  131. #define QSERDES_RX1_SIGDET_CNTRL			RX_OFF(1, 0x11C)
    132. 

  132. #define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL		RX_OFF(1, 0x124)
    133. 

  133. #define QSERDES_RX1_RX_BAND				RX_OFF(1, 0x128)
    134. 

  134. #define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN		RX_OFF(1, 0x30)
    135. 

  135. #define QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE	RX_OFF(1, 0x34)
    136. 

  136. #define QSERDES_RX1_UCDR_PI_CONTROLS			RX_OFF(1, 0x44)
    137. 

  137. #define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW		RX_OFF(1, 0x3C)
    138. 

  138. #define QSERDES_RX1_UCDR_PI_CTRL2			RX_OFF(1, 0x48)
    139. 

  139. #define QSERDES_RX1_RX_TERM_BW				RX_OFF(1, 0x80)
    140. 

  140. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2		RX_OFF(1, 0xEC)
    141. 

  141. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3		RX_OFF(1, 0xF0)
    142. 

  142. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4		RX_OFF(1, 0xF4)
    143. 

  143. #define QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2		RX_OFF(1, 0x114)
    144. 

  144. #define QSERDES_RX1_RX_IDAC_MEASURE_TIME		RX_OFF(1, 0x100)
    145. 

  145. #define QSERDES_RX1_RX_IDAC_TSETTLE_LOW			RX_OFF(1, 0xF8)
    146. 

  146. #define QSERDES_RX1_RX_IDAC_TSETTLE_HIGH		RX_OFF(1, 0xFC)
    147. 

  147. #define QSERDES_RX1_RX_MODE_00_LOW			RX_OFF(1, 0x170)
    148. 

  148. #define QSERDES_RX1_RX_MODE_00_HIGH			RX_OFF(1, 0x174)
    149. 

  149. #define QSERDES_RX1_RX_MODE_00_HIGH2			RX_OFF(1, 0x178)
    150. 

  150. #define QSERDES_RX1_RX_MODE_00_HIGH3			RX_OFF(1, 0x17C)
    151. 

  151. #define QSERDES_RX1_RX_MODE_00_HIGH4			RX_OFF(1, 0x180)
    152. 

  152. #define QSERDES_RX1_RX_MODE_01_LOW			RX_OFF(1, 0x184)
    153. 

  153. #define QSERDES_RX1_RX_MODE_01_HIGH			RX_OFF(1, 0x188)
    154. 

  154. #define QSERDES_RX1_RX_MODE_01_HIGH2			RX_OFF(1, 0x18C)
    155. 

  155. #define QSERDES_RX1_RX_MODE_01_HIGH3			RX_OFF(1, 0x190)
    156. 

  156. #define QSERDES_RX1_RX_MODE_01_HIGH4			RX_OFF(1, 0x194)
    157. 

  157. #define QSERDES_RX1_RX_MODE_10_LOW			RX_OFF(1, 0x198)
    158. 

  158. #define QSERDES_RX1_RX_MODE_10_HIGH			RX_OFF(1, 0x19C)
    159. 

  159. #define QSERDES_RX1_RX_MODE_10_HIGH2			RX_OFF(1, 0x1A0)
    160. 

  160. #define QSERDES_RX1_RX_MODE_10_HIGH3			RX_OFF(1, 0x1A4)
    161. 

  161. #define QSERDES_RX1_RX_MODE_10_HIGH4			RX_OFF(1, 0x1A8)
    162. 

  162. #define QSERDES_RX1_DCC_CTRL1				RX_OFF(1, 0x1BC)
    163. 

  163. #define QSERDES_RX1_AC_JTAG_ENABLE			RX_OFF(1, 0x68)
    164. 

  164. #define QSERDES_RX1_UCDR_FO_GAIN			RX_OFF(1, 0x08)
    165. 

  165. #define QSERDES_RX1_UCDR_SO_GAIN			RX_OFF(1, 0x14)
    166. 

  166. #define QSERDES_RX1_AC_JTAG_MODE			RX_OFF(1, 0x78)
    167. 

  167. 

  168. #define UFS_PHY_RX_LINECFG_DISABLE_BIT		BIT(1)
    169. 

  169. 

  170. /*
    171. 

  171.  * This structure represents the v4 specific phy.
    172. 

  172.  * common_cfg MUST remain the first field in this structure
    173. 

  173.  * in case extra fields are added. This way, when calling
    174. 

  174.  * get_ufs_qcom_phy() of generic phy, we can extract the
    175. 

  175.  * common phy structure (struct ufs_qcom_phy) out of it
    176. 

  176.  * regardless of the relevant specific phy.
    177. 

  177.  */
    178. 

  178. struct ufs_qcom_phy_qmp_v4 {
    179. 

  179. 	struct ufs_qcom_phy common_cfg;
    180. 

  180. };
    181. 

  181. 

  182. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
    183. 

  183. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
    184. 

  184. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9),
    185. 

  185. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x11),
    186. 

  186. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00),
    187. 

  187. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
    188. 

  188. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x02),
    189. 

  189. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
    190. 

  190. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
    191. 

  191. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
    192. 

  192. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
    193. 

  193. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
    194. 

  194. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
    195. 

  195. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
    196. 

  196. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
    197. 

  197. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
    198. 

  198. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xAC),
    199. 

  199. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
    200. 

  200. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
    201. 

  201. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
    202. 

  202. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
    203. 

  203. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
    204. 

  204. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
    205. 

  205. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
    206. 

  206. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xDD),
    207. 

  207. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
    208. 

  208. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
    209. 

  209. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
    210. 

  210. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
    211. 

  211. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
    212. 

  212. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x05),
    213. 

  213. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TRAN_DRVR_EMP_EN, 0x0C),
    214. 

  214. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
    215. 

  215. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
    216. 

  216. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
    217. 

  217. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_BAND, 0x18),
    218. 

  218. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0A),
    219. 

  219. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
    220. 

  220. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),
    221. 

  221. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
    222. 

  222. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x80),
    223. 

  223. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C),
    224. 

  224. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
    225. 

  225. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x1B),
    226. 

  226. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
    227. 

  227. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
    228. 

  228. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
    229. 

  229. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
    230. 

  230. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x10),
    231. 

  231. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xC0),
    232. 

  232. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
    233. 

  233. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x36),
    234. 

  234. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0x36),
    235. 

  235. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xF6),
    236. 

  236. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x3B),
    237. 

  237. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3D),
    238. 

  238. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_LOW, 0xE0),
    239. 

  239. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH, 0xC8),
    240. 

  240. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH2, 0xC8),
    241. 

  241. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH3, 0x3B),
    242. 

  242. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH4, 0xB1),
    243. 

  243. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_LOW, 0xE0),
    244. 

  244. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH, 0xC8),
    245. 

  245. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH2, 0xC8),
    246. 

  246. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B),
    247. 

  247. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1),
    248. 

  248. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D),
    249. 

  249. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
    250. 

  250. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
    251. 

  251. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
    252. 

  252. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_DEBUG_BUS_CLKSEL, 0x1F),
    253. 

  253. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF),
    254. 

  254. };
    255. 

  255. 

  256. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g3[] = {
    257. 

  257. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x03),
    258. 

  258. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
    259. 

  259. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xD8),
    260. 

  260. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWM_GEAR_BAND, 0xAA),
    261. 

  261. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06),
    262. 

  262. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
    263. 

  263. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
    264. 

  264. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C),
    265. 

  265. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
    266. 

  266. };
    267. 

  267. 

  268. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g4[] = {
    269. 

  269. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x81),
    270. 

  270. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x6F),
    271. 

  271. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x20),
    272. 

  272. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0x80),
    273. 

  273. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x01),
    274. 

  274. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x3F),
    275. 

  275. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0xFF),
    276. 

  276. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xFF),
    277. 

  277. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x7F),
    278. 

  278. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x6D),
    279. 

  279. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C),
    280. 

  280. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x10),
    281. 

  281. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_BIST_FIXED_PAT_CTRL, 0x0A),
    282. 

  282. };
    283. 

  283. 

  284. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2_g3[] = {
    285. 

  285. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x35),
    286. 

  286. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
    287. 

  287. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
    288. 

  288. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x6D),
    289. 

  289. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0x6D),
    290. 

  290. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xED),
    291. 

  291. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3C),
    292. 

  292. };
    293. 

  293. 

  294. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2_g4[] = {
    295. 

  295. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x75),
    296. 

  296. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
    297. 

  297. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
    298. 

  298. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x6C),
    299. 

  299. };
    300. 

  300. 

  301. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
    302. 

  302. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
    303. 

  303. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
    304. 

  304. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
    305. 

  305. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
    306. 

  306. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x05),
    307. 

  307. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TRAN_DRVR_EMP_EN, 0x0C),
    308. 

  308. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
    309. 

  309. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
    310. 

  310. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
    311. 

  311. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_BAND, 0x18),
    312. 

  312. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0A),
    313. 

  313. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
    314. 

  314. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0xF1),
    315. 

  315. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
    316. 

  316. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x80),
    317. 

  317. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C),
    318. 

  318. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),
    319. 

  319. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x1B),
    320. 

  320. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),
    321. 

  321. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),
    322. 

  322. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
    323. 

  323. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
    324. 

  324. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x10),
    325. 

  325. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0xC0),
    326. 

  326. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x00),
    327. 

  327. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x36),
    328. 

  328. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0x36),
    329. 

  329. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xF6),
    330. 

  330. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x3B),
    331. 

  331. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3D),
    332. 

  332. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_LOW, 0xE0),
    333. 

  333. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH, 0xC8),
    334. 

  334. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH2, 0xC8),
    335. 

  335. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH3, 0x3B),
    336. 

  336. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH4, 0xB1),
    337. 

  337. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_LOW, 0xE0),
    338. 

  338. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH, 0xC8),
    339. 

  339. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH2, 0xC8),
    340. 

  340. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B),
    341. 

  341. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1),
    342. 

  342. 	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
    343. 

  343. };
    344. 

  344. 

  345. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2_g3[] = {
    346. 

  346. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x35),
    347. 

  347. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
    348. 

  348. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
    349. 

  349. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x6D),
    350. 

  350. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0x6D),
    351. 

  351. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xED),
    352. 

  352. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3C),
    353. 

  353. };
    354. 

  354. 

  355. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2_g4[] = {
    356. 

  356. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x75),
    357. 

  357. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
    358. 

  358. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
    359. 

  359. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x6C),
    360. 

  360. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x81),
    361. 

  361. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x6F),
    362. 

  362. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x20),
    363. 

  363. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0x80),
    364. 

  364. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x01),
    365. 

  365. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x3F),
    366. 

  366. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0xFF),
    367. 

  367. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xFF),
    368. 

  368. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x7F),
    369. 

  369. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x6D),
    370. 

  370. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C),
    371. 

  371. };
    372. 

  372. 

  373. static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
    374. 

  374. 	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x06),
    375. 

  375. };
    376. 

  376. 

  377. #endif
    378.