phy-qcom-ufs-qmp-v4-waipio.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021, Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "phy-qcom-ufs-qmp-v4-waipio.h"
  7. #define UFS_PHY_NAME "ufs_phy_qmp_v4_waipio"
  8. static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy);
  9. static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common);
  10. static int ufs_qcom_phy_qmp_v4_phy_calibrate(struct phy *generic_phy)
  11. {
  12. struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
  13. struct device *dev = ufs_qcom_phy->dev;
  14. bool is_g4, is_rate_B;
  15. int err;
  16. err = reset_control_assert(ufs_qcom_phy->ufs_reset);
  17. if (err) {
  18. dev_err(dev, "Failed to assert UFS PHY reset %d\n", err);
  19. goto out;
  20. }
  21. /* For UFS PHY's submode, 1 = G4, 0 = non-G4 */
  22. is_g4 = !!ufs_qcom_phy->submode;
  23. is_rate_B = (ufs_qcom_phy->mode == PHY_MODE_UFS_HS_B) ? true : false;
  24. writel_relaxed(0x01, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET);
  25. /* Ensure PHY is in reset before writing PHY calibration data */
  26. wmb();
  27. /*
  28. * Writing PHY calibration in this order:
  29. * 1. Write Rate-A calibration first (1-lane mode).
  30. * 2. Write 2nd lane configuration if needed.
  31. * 3. Write Rate-B calibration overrides
  32. */
  33. if (is_g4) {
  34. ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A,
  35. ARRAY_SIZE(phy_cal_table_rate_A));
  36. if (ufs_qcom_phy->lanes_per_direction == 2)
  37. ufs_qcom_phy_write_tbl(ufs_qcom_phy,
  38. phy_cal_table_2nd_lane,
  39. ARRAY_SIZE(phy_cal_table_2nd_lane));
  40. } else {
  41. ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_no_g4,
  42. ARRAY_SIZE(phy_cal_table_rate_A_no_g4));
  43. if (ufs_qcom_phy->lanes_per_direction == 2)
  44. ufs_qcom_phy_write_tbl(ufs_qcom_phy,
  45. phy_cal_table_2nd_lane_no_g4,
  46. ARRAY_SIZE(phy_cal_table_2nd_lane_no_g4));
  47. }
  48. if (is_rate_B)
  49. ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B,
  50. ARRAY_SIZE(phy_cal_table_rate_B));
  51. writel_relaxed(0x00, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET);
  52. /* flush buffered writes */
  53. wmb();
  54. err = reset_control_deassert(ufs_qcom_phy->ufs_reset);
  55. if (err) {
  56. dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err);
  57. goto out;
  58. }
  59. ufs_qcom_phy_qmp_v4_start_serdes(ufs_qcom_phy);
  60. err = ufs_qcom_phy_qmp_v4_is_pcs_ready(ufs_qcom_phy);
  61. out:
  62. return err;
  63. }
  64. static int ufs_qcom_phy_qmp_v4_init(struct phy *generic_phy)
  65. {
  66. struct ufs_qcom_phy_qmp_v4 *phy = phy_get_drvdata(generic_phy);
  67. struct ufs_qcom_phy *phy_common = &phy->common_cfg;
  68. int err;
  69. err = ufs_qcom_phy_init_clks(phy_common);
  70. if (err) {
  71. dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
  72. __func__, err);
  73. goto out;
  74. }
  75. err = ufs_qcom_phy_init_vregulators(phy_common);
  76. if (err) {
  77. dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
  78. __func__, err);
  79. goto out;
  80. }
  81. /* Optional */
  82. ufs_qcom_phy_get_reset(phy_common);
  83. out:
  84. return err;
  85. }
  86. static int ufs_qcom_phy_qmp_v4_exit(struct phy *generic_phy)
  87. {
  88. return 0;
  89. }
  90. static
  91. int ufs_qcom_phy_qmp_v4_set_mode(struct phy *generic_phy,
  92. enum phy_mode mode, int submode)
  93. {
  94. struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
  95. phy_common->mode = PHY_MODE_INVALID;
  96. if (mode > 0)
  97. phy_common->mode = mode;
  98. phy_common->submode = submode;
  99. return 0;
  100. }
  101. static inline
  102. void ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(struct ufs_qcom_phy *phy,
  103. bool enable)
  104. {
  105. u32 temp;
  106. temp = readl_relaxed(phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE);
  107. if (enable)
  108. temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
  109. else
  110. temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
  111. writel_relaxed(temp, phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE);
  112. if (phy->lanes_per_direction == 1)
  113. goto out;
  114. temp = readl_relaxed(phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE);
  115. if (enable)
  116. temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
  117. else
  118. temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;
  119. writel_relaxed(temp, phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE);
  120. out:
  121. /* ensure register value is committed */
  122. mb();
  123. }
  124. static
  125. void ufs_qcom_phy_qmp_v4_power_control(struct ufs_qcom_phy *phy,
  126. bool power_ctrl)
  127. {
  128. if (!power_ctrl) {
  129. /* apply analog power collapse */
  130. writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  131. /*
  132. * Make sure that PHY knows its analog rail is going to be
  133. * powered OFF.
  134. */
  135. mb();
  136. ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, true);
  137. } else {
  138. ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, false);
  139. /* bring PHY out of analog power collapse */
  140. writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  141. /*
  142. * Before any transactions involving PHY, ensure PHY knows
  143. * that it's analog rail is powered ON.
  144. */
  145. mb();
  146. }
  147. }
  148. static inline
  149. void ufs_qcom_phy_qmp_v4_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
  150. {
  151. /*
  152. * v4 PHY does not have TX_LANE_ENABLE register.
  153. * Implement this function so as not to propagate error to caller.
  154. */
  155. }
  156. static
  157. void ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)
  158. {
  159. u32 temp;
  160. temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);
  161. if (ctrl) /* enable RX LineCfg */
  162. temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;
  163. else /* disable RX LineCfg */
  164. temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;
  165. writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);
  166. /* make sure that RX LineCfg config applied before we return */
  167. mb();
  168. }
  169. static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy)
  170. {
  171. u32 tmp;
  172. tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
  173. tmp &= ~MASK_SERDES_START;
  174. tmp |= (1 << OFFSET_SERDES_START);
  175. writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
  176. /* Ensure register value is committed */
  177. mb();
  178. }
  179. static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common)
  180. {
  181. int err = 0;
  182. u32 val;
  183. err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
  184. val, (val & MASK_PCS_READY), 10, 1000000);
  185. if (err) {
  186. dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
  187. __func__, err);
  188. goto out;
  189. }
  190. out:
  191. return err;
  192. }
  193. static void ufs_qcom_phy_qmp_v4_dbg_register_dump(struct ufs_qcom_phy *phy)
  194. {
  195. ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
  196. "PHY QSERDES COM Registers ");
  197. ufs_qcom_phy_dump_regs(phy, PCS2_BASE, PCS2_SIZE,
  198. "PHY PCS2 Registers ");
  199. ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE,
  200. "PHY Registers ");
  201. ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE,
  202. "PHY RX0 Registers ");
  203. ufs_qcom_phy_dump_regs(phy, TX_BASE(0), TX_SIZE,
  204. "PHY TX0 Registers ");
  205. ufs_qcom_phy_dump_regs(phy, RX_BASE(1), RX_SIZE,
  206. "PHY RX1 Registers ");
  207. ufs_qcom_phy_dump_regs(phy, TX_BASE(1), TX_SIZE,
  208. "PHY TX1 Registers ");
  209. }
  210. static const struct phy_ops ufs_qcom_phy_qmp_v4_phy_ops = {
  211. .init = ufs_qcom_phy_qmp_v4_init,
  212. .exit = ufs_qcom_phy_qmp_v4_exit,
  213. .power_on = ufs_qcom_phy_power_on,
  214. .power_off = ufs_qcom_phy_power_off,
  215. .set_mode = ufs_qcom_phy_qmp_v4_set_mode,
  216. .calibrate = ufs_qcom_phy_qmp_v4_phy_calibrate,
  217. .owner = THIS_MODULE,
  218. };
  219. static struct ufs_qcom_phy_specific_ops phy_v4_ops = {
  220. .start_serdes = ufs_qcom_phy_qmp_v4_start_serdes,
  221. .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v4_is_pcs_ready,
  222. .set_tx_lane_enable = ufs_qcom_phy_qmp_v4_set_tx_lane_enable,
  223. .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg,
  224. .power_control = ufs_qcom_phy_qmp_v4_power_control,
  225. .dbg_register_dump = ufs_qcom_phy_qmp_v4_dbg_register_dump,
  226. };
  227. static int ufs_qcom_phy_qmp_v4_probe(struct platform_device *pdev)
  228. {
  229. struct device *dev = &pdev->dev;
  230. struct phy *generic_phy;
  231. struct ufs_qcom_phy_qmp_v4 *phy;
  232. int err = 0;
  233. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  234. if (!phy) {
  235. err = -ENOMEM;
  236. goto out;
  237. }
  238. generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
  239. &ufs_qcom_phy_qmp_v4_phy_ops, &phy_v4_ops);
  240. if (!generic_phy) {
  241. dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
  242. __func__);
  243. err = -EIO;
  244. goto out;
  245. }
  246. phy_set_drvdata(generic_phy, phy);
  247. strscpy(phy->common_cfg.name, UFS_PHY_NAME,
  248. sizeof(phy->common_cfg.name));
  249. out:
  250. return err;
  251. }
  252. static const struct of_device_id ufs_qcom_phy_qmp_v4_of_match[] = {
  253. {.compatible = "qcom,ufs-phy-qmp-v4-waipio"},
  254. {},
  255. };
  256. MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v4_of_match);
  257. static struct platform_driver ufs_qcom_phy_qmp_v4_driver = {
  258. .probe = ufs_qcom_phy_qmp_v4_probe,
  259. .driver = {
  260. .of_match_table = ufs_qcom_phy_qmp_v4_of_match,
  261. .name = "ufs_qcom_phy_qmp_v4_waipio",
  262. },
  263. };
  264. module_platform_driver(ufs_qcom_phy_qmp_v4_driver);
  265. MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v4 WAIPIO");
  266. MODULE_LICENSE("GPL");