phy-lantiq-rcu-usb2.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
  4. *
  5. * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/property.h>
  18. #include <linux/regmap.h>
  19. #include <linux/reset.h>
  20. /* Transmitter HS Pre-Emphasis Enable */
  21. #define RCU_CFG1_TX_PEE BIT(0)
  22. /* Disconnect Threshold */
  23. #define RCU_CFG1_DIS_THR_MASK 0x00038000
  24. #define RCU_CFG1_DIS_THR_SHIFT 15
  25. struct ltq_rcu_usb2_bits {
  26. u8 hostmode;
  27. u8 slave_endianness;
  28. u8 host_endianness;
  29. bool have_ana_cfg;
  30. };
  31. struct ltq_rcu_usb2_priv {
  32. struct regmap *regmap;
  33. unsigned int phy_reg_offset;
  34. unsigned int ana_cfg1_reg_offset;
  35. const struct ltq_rcu_usb2_bits *reg_bits;
  36. struct device *dev;
  37. struct phy *phy;
  38. struct clk *phy_gate_clk;
  39. struct reset_control *ctrl_reset;
  40. struct reset_control *phy_reset;
  41. };
  42. static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
  43. .hostmode = 11,
  44. .slave_endianness = 9,
  45. .host_endianness = 10,
  46. .have_ana_cfg = false,
  47. };
  48. static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
  49. .hostmode = 11,
  50. .slave_endianness = 17,
  51. .host_endianness = 10,
  52. .have_ana_cfg = false,
  53. };
  54. static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
  55. .hostmode = 11,
  56. .slave_endianness = 9,
  57. .host_endianness = 10,
  58. .have_ana_cfg = true,
  59. };
  60. static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
  61. {
  62. .compatible = "lantiq,ase-usb2-phy",
  63. .data = &xway_rcu_usb2_reg_bits,
  64. },
  65. {
  66. .compatible = "lantiq,danube-usb2-phy",
  67. .data = &xway_rcu_usb2_reg_bits,
  68. },
  69. {
  70. .compatible = "lantiq,xrx100-usb2-phy",
  71. .data = &xrx100_rcu_usb2_reg_bits,
  72. },
  73. {
  74. .compatible = "lantiq,xrx200-usb2-phy",
  75. .data = &xrx200_rcu_usb2_reg_bits,
  76. },
  77. {
  78. .compatible = "lantiq,xrx300-usb2-phy",
  79. .data = &xrx200_rcu_usb2_reg_bits,
  80. },
  81. { },
  82. };
  83. MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
  84. static int ltq_rcu_usb2_phy_init(struct phy *phy)
  85. {
  86. struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
  87. if (priv->reg_bits->have_ana_cfg) {
  88. regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
  89. RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
  90. regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
  91. RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
  92. }
  93. /* Configure core to host mode */
  94. regmap_update_bits(priv->regmap, priv->phy_reg_offset,
  95. BIT(priv->reg_bits->hostmode), 0);
  96. /* Select DMA endianness (Host-endian: big-endian) */
  97. regmap_update_bits(priv->regmap, priv->phy_reg_offset,
  98. BIT(priv->reg_bits->slave_endianness), 0);
  99. regmap_update_bits(priv->regmap, priv->phy_reg_offset,
  100. BIT(priv->reg_bits->host_endianness),
  101. BIT(priv->reg_bits->host_endianness));
  102. return 0;
  103. }
  104. static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
  105. {
  106. struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
  107. struct device *dev = priv->dev;
  108. int ret;
  109. reset_control_deassert(priv->phy_reset);
  110. ret = clk_prepare_enable(priv->phy_gate_clk);
  111. if (ret) {
  112. dev_err(dev, "failed to enable PHY gate\n");
  113. return ret;
  114. }
  115. /*
  116. * at least the xrx200 usb2 phy requires some extra time to be
  117. * operational after enabling the clock
  118. */
  119. usleep_range(100, 200);
  120. return ret;
  121. }
  122. static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
  123. {
  124. struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
  125. reset_control_assert(priv->phy_reset);
  126. clk_disable_unprepare(priv->phy_gate_clk);
  127. return 0;
  128. }
  129. static const struct phy_ops ltq_rcu_usb2_phy_ops = {
  130. .init = ltq_rcu_usb2_phy_init,
  131. .power_on = ltq_rcu_usb2_phy_power_on,
  132. .power_off = ltq_rcu_usb2_phy_power_off,
  133. .owner = THIS_MODULE,
  134. };
  135. static int ltq_rcu_usb2_of_parse(struct ltq_rcu_usb2_priv *priv,
  136. struct platform_device *pdev)
  137. {
  138. struct device *dev = priv->dev;
  139. const __be32 *offset;
  140. priv->reg_bits = of_device_get_match_data(dev);
  141. priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
  142. if (IS_ERR(priv->regmap)) {
  143. dev_err(dev, "Failed to lookup RCU regmap\n");
  144. return PTR_ERR(priv->regmap);
  145. }
  146. offset = of_get_address(dev->of_node, 0, NULL, NULL);
  147. if (!offset) {
  148. dev_err(dev, "Failed to get RCU PHY reg offset\n");
  149. return -ENOENT;
  150. }
  151. priv->phy_reg_offset = __be32_to_cpu(*offset);
  152. if (priv->reg_bits->have_ana_cfg) {
  153. offset = of_get_address(dev->of_node, 1, NULL, NULL);
  154. if (!offset) {
  155. dev_err(dev, "Failed to get RCU ANA CFG1 reg offset\n");
  156. return -ENOENT;
  157. }
  158. priv->ana_cfg1_reg_offset = __be32_to_cpu(*offset);
  159. }
  160. priv->phy_gate_clk = devm_clk_get(dev, "phy");
  161. if (IS_ERR(priv->phy_gate_clk)) {
  162. dev_err(dev, "Unable to get USB phy gate clk\n");
  163. return PTR_ERR(priv->phy_gate_clk);
  164. }
  165. priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
  166. if (IS_ERR(priv->ctrl_reset)) {
  167. if (PTR_ERR(priv->ctrl_reset) != -EPROBE_DEFER)
  168. dev_err(dev, "failed to get 'ctrl' reset\n");
  169. return PTR_ERR(priv->ctrl_reset);
  170. }
  171. priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
  172. return PTR_ERR_OR_ZERO(priv->phy_reset);
  173. }
  174. static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
  175. {
  176. struct device *dev = &pdev->dev;
  177. struct ltq_rcu_usb2_priv *priv;
  178. struct phy_provider *provider;
  179. int ret;
  180. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  181. if (!priv)
  182. return -ENOMEM;
  183. priv->dev = dev;
  184. ret = ltq_rcu_usb2_of_parse(priv, pdev);
  185. if (ret)
  186. return ret;
  187. /* Reset USB core through reset controller */
  188. reset_control_deassert(priv->ctrl_reset);
  189. reset_control_assert(priv->phy_reset);
  190. priv->phy = devm_phy_create(dev, dev->of_node, &ltq_rcu_usb2_phy_ops);
  191. if (IS_ERR(priv->phy)) {
  192. dev_err(dev, "failed to create PHY\n");
  193. return PTR_ERR(priv->phy);
  194. }
  195. phy_set_drvdata(priv->phy, priv);
  196. provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  197. if (IS_ERR(provider))
  198. return PTR_ERR(provider);
  199. dev_set_drvdata(priv->dev, priv);
  200. return 0;
  201. }
  202. static struct platform_driver ltq_rcu_usb2_phy_driver = {
  203. .probe = ltq_rcu_usb2_phy_probe,
  204. .driver = {
  205. .name = "lantiq-rcu-usb2-phy",
  206. .of_match_table = ltq_rcu_usb2_phy_of_match,
  207. }
  208. };
  209. module_platform_driver(ltq_rcu_usb2_phy_driver);
  210. MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
  211. MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
  212. MODULE_LICENSE("GPL v2");