phy-intel-thunderbay-emmc.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel ThunderBay eMMC PHY driver
  4. *
  5. * Copyright (C) 2021 Intel Corporation
  6. *
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/io.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/phy/phy.h>
  15. #include <linux/platform_device.h>
  16. /* eMMC/SD/SDIO core/phy configuration registers */
  17. #define CTRL_CFG_0 0x00
  18. #define CTRL_CFG_1 0x04
  19. #define CTRL_PRESET_0 0x08
  20. #define CTRL_PRESET_1 0x0c
  21. #define CTRL_PRESET_2 0x10
  22. #define CTRL_PRESET_3 0x14
  23. #define CTRL_PRESET_4 0x18
  24. #define CTRL_CFG_2 0x1c
  25. #define CTRL_CFG_3 0x20
  26. #define PHY_CFG_0 0x24
  27. #define PHY_CFG_1 0x28
  28. #define PHY_CFG_2 0x2c
  29. #define PHYBIST_CTRL 0x30
  30. #define SDHC_STAT3 0x34
  31. #define PHY_STAT 0x38
  32. #define PHYBIST_STAT_0 0x3c
  33. #define PHYBIST_STAT_1 0x40
  34. #define EMMC_AXI 0x44
  35. /* CTRL_PRESET_3 */
  36. #define CTRL_PRESET3_MASK GENMASK(31, 0)
  37. #define CTRL_PRESET3_SHIFT 0
  38. /* CTRL_CFG_0 bit fields */
  39. #define SUPPORT_HS_MASK BIT(26)
  40. #define SUPPORT_HS_SHIFT 26
  41. #define SUPPORT_8B_MASK BIT(24)
  42. #define SUPPORT_8B_SHIFT 24
  43. /* CTRL_CFG_1 bit fields */
  44. #define SUPPORT_SDR50_MASK BIT(28)
  45. #define SUPPORT_SDR50_SHIFT 28
  46. #define SLOT_TYPE_MASK GENMASK(27, 26)
  47. #define SLOT_TYPE_OFFSET 26
  48. #define SUPPORT_64B_MASK BIT(24)
  49. #define SUPPORT_64B_SHIFT 24
  50. #define SUPPORT_HS400_MASK BIT(2)
  51. #define SUPPORT_HS400_SHIFT 2
  52. #define SUPPORT_DDR50_MASK BIT(1)
  53. #define SUPPORT_DDR50_SHIFT 1
  54. #define SUPPORT_SDR104_MASK BIT(0)
  55. #define SUPPORT_SDR104_SHIFT 0
  56. /* PHY_CFG_0 bit fields */
  57. #define SEL_DLY_TXCLK_MASK BIT(29)
  58. #define SEL_DLY_TXCLK_SHIFT 29
  59. #define SEL_DLY_RXCLK_MASK BIT(28)
  60. #define SEL_DLY_RXCLK_SHIFT 28
  61. #define OTAP_DLY_ENA_MASK BIT(27)
  62. #define OTAP_DLY_ENA_SHIFT 27
  63. #define OTAP_DLY_SEL_MASK GENMASK(26, 23)
  64. #define OTAP_DLY_SEL_SHIFT 23
  65. #define ITAP_CHG_WIN_MASK BIT(22)
  66. #define ITAP_CHG_WIN_SHIFT 22
  67. #define ITAP_DLY_ENA_MASK BIT(21)
  68. #define ITAP_DLY_ENA_SHIFT 21
  69. #define ITAP_DLY_SEL_MASK GENMASK(20, 16)
  70. #define ITAP_DLY_SEL_SHIFT 16
  71. #define RET_ENB_MASK BIT(15)
  72. #define RET_ENB_SHIFT 15
  73. #define RET_EN_MASK BIT(14)
  74. #define RET_EN_SHIFT 14
  75. #define DLL_IFF_MASK GENMASK(13, 11)
  76. #define DLL_IFF_SHIFT 11
  77. #define DLL_EN_MASK BIT(10)
  78. #define DLL_EN_SHIFT 10
  79. #define DLL_TRIM_ICP_MASK GENMASK(9, 6)
  80. #define DLL_TRIM_ICP_SHIFT 6
  81. #define RETRIM_EN_MASK BIT(5)
  82. #define RETRIM_EN_SHIFT 5
  83. #define RETRIM_MASK BIT(4)
  84. #define RETRIM_SHIFT 4
  85. #define DR_TY_MASK GENMASK(3, 1)
  86. #define DR_TY_SHIFT 1
  87. #define PWR_DOWN_MASK BIT(0)
  88. #define PWR_DOWN_SHIFT 0
  89. /* PHY_CFG_1 bit fields */
  90. #define REN_DAT_MASK GENMASK(19, 12)
  91. #define REN_DAT_SHIFT 12
  92. #define REN_CMD_MASK BIT(11)
  93. #define REN_CMD_SHIFT 11
  94. #define REN_STRB_MASK BIT(10)
  95. #define REN_STRB_SHIFT 10
  96. #define PU_STRB_MASK BIT(20)
  97. #define PU_STRB_SHIFT 20
  98. /* PHY_CFG_2 bit fields */
  99. #define CLKBUF_MASK GENMASK(24, 21)
  100. #define CLKBUF_SHIFT 21
  101. #define SEL_STRB_MASK GENMASK(20, 13)
  102. #define SEL_STRB_SHIFT 13
  103. #define SEL_FREQ_MASK GENMASK(12, 10)
  104. #define SEL_FREQ_SHIFT 10
  105. /* PHY_STAT bit fields */
  106. #define CAL_DONE BIT(6)
  107. #define DLL_RDY BIT(5)
  108. #define OTAP_DLY 0x0
  109. #define ITAP_DLY 0x0
  110. #define STRB 0x33
  111. /* From ACS_eMMC51_16nFFC_RO1100_Userguide_v1p0.pdf p17 */
  112. #define FREQSEL_200M_170M 0x0
  113. #define FREQSEL_170M_140M 0x1
  114. #define FREQSEL_140M_110M 0x2
  115. #define FREQSEL_110M_80M 0x3
  116. #define FREQSEL_80M_50M 0x4
  117. #define FREQSEL_275M_250M 0x5
  118. #define FREQSEL_250M_225M 0x6
  119. #define FREQSEL_225M_200M 0x7
  120. /* Phy power status */
  121. #define PHY_UNINITIALIZED 0
  122. #define PHY_INITIALIZED 1
  123. /*
  124. * During init(400KHz) phy_settings will be called with 200MHZ clock
  125. * To avoid incorrectly setting the phy for init(400KHZ) "phy_power_sts" is used.
  126. * When actual clock is set always phy is powered off once and then powered on.
  127. * (sdhci_arasan_set_clock). That feature will be used to identify whether the
  128. * settings are for init phy_power_on or actual clock phy_power_on
  129. * 0 --> init settings
  130. * 1 --> actual settings
  131. */
  132. struct thunderbay_emmc_phy {
  133. void __iomem *reg_base;
  134. struct clk *emmcclk;
  135. int phy_power_sts;
  136. };
  137. static inline void update_reg(struct thunderbay_emmc_phy *tbh_phy, u32 offset,
  138. u32 mask, u32 shift, u32 val)
  139. {
  140. u32 tmp;
  141. tmp = readl(tbh_phy->reg_base + offset);
  142. tmp &= ~mask;
  143. tmp |= val << shift;
  144. writel(tmp, tbh_phy->reg_base + offset);
  145. }
  146. static int thunderbay_emmc_phy_power(struct phy *phy, bool power_on)
  147. {
  148. struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
  149. unsigned int freqsel = FREQSEL_200M_170M;
  150. unsigned long rate;
  151. static int lock;
  152. u32 val;
  153. int ret;
  154. /* Disable DLL */
  155. rate = clk_get_rate(tbh_phy->emmcclk);
  156. switch (rate) {
  157. case 200000000:
  158. /* lock dll only when it is used, i.e only if SEL_DLY_TXCLK/RXCLK are 0 */
  159. update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x0);
  160. break;
  161. /* dll lock not required for other frequencies */
  162. case 50000000 ... 52000000:
  163. case 400000:
  164. default:
  165. break;
  166. }
  167. if (!power_on)
  168. return 0;
  169. rate = clk_get_rate(tbh_phy->emmcclk);
  170. switch (rate) {
  171. case 170000001 ... 200000000:
  172. freqsel = FREQSEL_200M_170M;
  173. break;
  174. case 140000001 ... 170000000:
  175. freqsel = FREQSEL_170M_140M;
  176. break;
  177. case 110000001 ... 140000000:
  178. freqsel = FREQSEL_140M_110M;
  179. break;
  180. case 80000001 ... 110000000:
  181. freqsel = FREQSEL_110M_80M;
  182. break;
  183. case 50000000 ... 80000000:
  184. freqsel = FREQSEL_80M_50M;
  185. break;
  186. case 250000001 ... 275000000:
  187. freqsel = FREQSEL_275M_250M;
  188. break;
  189. case 225000001 ... 250000000:
  190. freqsel = FREQSEL_250M_225M;
  191. break;
  192. case 200000001 ... 225000000:
  193. freqsel = FREQSEL_225M_200M;
  194. break;
  195. default:
  196. break;
  197. }
  198. /* Clock rate is checked against upper limit. It may fall low during init */
  199. if (rate > 200000000)
  200. dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
  201. udelay(5);
  202. if (lock == 0) {
  203. /* PDB will be done only once per boot */
  204. update_reg(tbh_phy, PHY_CFG_0, PWR_DOWN_MASK,
  205. PWR_DOWN_SHIFT, 0x1);
  206. lock = 1;
  207. /*
  208. * According to the user manual, it asks driver to wait 5us for
  209. * calpad busy trimming. However it is documented that this value is
  210. * PVT(A.K.A. process, voltage and temperature) relevant, so some
  211. * failure cases are found which indicates we should be more tolerant
  212. * to calpad busy trimming.
  213. */
  214. ret = readl_poll_timeout(tbh_phy->reg_base + PHY_STAT,
  215. val, (val & CAL_DONE), 10, 50);
  216. if (ret) {
  217. dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
  218. return ret;
  219. }
  220. }
  221. rate = clk_get_rate(tbh_phy->emmcclk);
  222. switch (rate) {
  223. case 200000000:
  224. /* Set frequency of the DLL operation */
  225. update_reg(tbh_phy, PHY_CFG_2, SEL_FREQ_MASK, SEL_FREQ_SHIFT, freqsel);
  226. /* Enable DLL */
  227. update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x1);
  228. /*
  229. * After enabling analog DLL circuits docs say that we need 10.2 us if
  230. * our source clock is at 50 MHz and that lock time scales linearly
  231. * with clock speed. If we are powering on the PHY and the card clock
  232. * is super slow (like 100kHz) this could take as long as 5.1 ms as
  233. * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
  234. * hopefully we won't be running at 100 kHz, but we should still make
  235. * sure we wait long enough.
  236. *
  237. * NOTE: There appear to be corner cases where the DLL seems to take
  238. * extra long to lock for reasons that aren't understood. In some
  239. * extreme cases we've seen it take up to over 10ms (!). We'll be
  240. * generous and give it 50ms.
  241. */
  242. ret = readl_poll_timeout(tbh_phy->reg_base + PHY_STAT,
  243. val, (val & DLL_RDY), 10, 50 * USEC_PER_MSEC);
  244. if (ret) {
  245. dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);
  246. return ret;
  247. }
  248. break;
  249. default:
  250. break;
  251. }
  252. return 0;
  253. }
  254. static int thunderbay_emmc_phy_init(struct phy *phy)
  255. {
  256. struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
  257. tbh_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
  258. return PTR_ERR_OR_ZERO(tbh_phy->emmcclk);
  259. }
  260. static int thunderbay_emmc_phy_exit(struct phy *phy)
  261. {
  262. struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
  263. clk_put(tbh_phy->emmcclk);
  264. return 0;
  265. }
  266. static int thunderbay_emmc_phy_power_on(struct phy *phy)
  267. {
  268. struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
  269. unsigned long rate;
  270. /* Overwrite capability bits configurable in bootloader */
  271. update_reg(tbh_phy, CTRL_CFG_0,
  272. SUPPORT_HS_MASK, SUPPORT_HS_SHIFT, 0x1);
  273. update_reg(tbh_phy, CTRL_CFG_0,
  274. SUPPORT_8B_MASK, SUPPORT_8B_SHIFT, 0x1);
  275. update_reg(tbh_phy, CTRL_CFG_1,
  276. SUPPORT_SDR50_MASK, SUPPORT_SDR50_SHIFT, 0x1);
  277. update_reg(tbh_phy, CTRL_CFG_1,
  278. SUPPORT_DDR50_MASK, SUPPORT_DDR50_SHIFT, 0x1);
  279. update_reg(tbh_phy, CTRL_CFG_1,
  280. SUPPORT_SDR104_MASK, SUPPORT_SDR104_SHIFT, 0x1);
  281. update_reg(tbh_phy, CTRL_CFG_1,
  282. SUPPORT_HS400_MASK, SUPPORT_HS400_SHIFT, 0x1);
  283. update_reg(tbh_phy, CTRL_CFG_1,
  284. SUPPORT_64B_MASK, SUPPORT_64B_SHIFT, 0x1);
  285. if (tbh_phy->phy_power_sts == PHY_UNINITIALIZED) {
  286. /* Indicates initialization, settings for init, same as 400KHZ setting */
  287. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK, SEL_DLY_TXCLK_SHIFT, 0x1);
  288. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK, SEL_DLY_RXCLK_SHIFT, 0x1);
  289. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK, ITAP_DLY_ENA_SHIFT, 0x0);
  290. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK, ITAP_DLY_SEL_SHIFT, 0x0);
  291. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK, OTAP_DLY_ENA_SHIFT, 0x0);
  292. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK, OTAP_DLY_SEL_SHIFT, 0);
  293. update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK, DLL_TRIM_ICP_SHIFT, 0);
  294. update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
  295. } else if (tbh_phy->phy_power_sts == PHY_INITIALIZED) {
  296. /* Indicates actual clock setting */
  297. rate = clk_get_rate(tbh_phy->emmcclk);
  298. switch (rate) {
  299. case 200000000:
  300. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
  301. SEL_DLY_TXCLK_SHIFT, 0x0);
  302. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
  303. SEL_DLY_RXCLK_SHIFT, 0x0);
  304. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
  305. ITAP_DLY_ENA_SHIFT, 0x0);
  306. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
  307. ITAP_DLY_SEL_SHIFT, 0x0);
  308. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
  309. OTAP_DLY_ENA_SHIFT, 0x1);
  310. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
  311. OTAP_DLY_SEL_SHIFT, 2);
  312. update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
  313. DLL_TRIM_ICP_SHIFT, 0x8);
  314. update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
  315. DR_TY_SHIFT, 0x1);
  316. /* For HS400 only */
  317. update_reg(tbh_phy, PHY_CFG_2, SEL_STRB_MASK,
  318. SEL_STRB_SHIFT, STRB);
  319. break;
  320. case 50000000 ... 52000000:
  321. /* For both HS and DDR52 this setting works */
  322. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
  323. SEL_DLY_TXCLK_SHIFT, 0x1);
  324. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
  325. SEL_DLY_RXCLK_SHIFT, 0x1);
  326. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
  327. ITAP_DLY_ENA_SHIFT, 0x0);
  328. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
  329. ITAP_DLY_SEL_SHIFT, 0x0);
  330. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
  331. OTAP_DLY_ENA_SHIFT, 0x1);
  332. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
  333. OTAP_DLY_SEL_SHIFT, 4);
  334. update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
  335. DLL_TRIM_ICP_SHIFT, 0x8);
  336. update_reg(tbh_phy, PHY_CFG_0,
  337. DR_TY_MASK, DR_TY_SHIFT, 0x1);
  338. break;
  339. case 400000:
  340. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
  341. SEL_DLY_TXCLK_SHIFT, 0x1);
  342. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
  343. SEL_DLY_RXCLK_SHIFT, 0x1);
  344. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
  345. ITAP_DLY_ENA_SHIFT, 0x0);
  346. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
  347. ITAP_DLY_SEL_SHIFT, 0x0);
  348. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
  349. OTAP_DLY_ENA_SHIFT, 0x0);
  350. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
  351. OTAP_DLY_SEL_SHIFT, 0);
  352. update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
  353. DLL_TRIM_ICP_SHIFT, 0);
  354. update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
  355. break;
  356. default:
  357. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
  358. SEL_DLY_TXCLK_SHIFT, 0x1);
  359. update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
  360. SEL_DLY_RXCLK_SHIFT, 0x1);
  361. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
  362. ITAP_DLY_ENA_SHIFT, 0x0);
  363. update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
  364. ITAP_DLY_SEL_SHIFT, 0x0);
  365. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
  366. OTAP_DLY_ENA_SHIFT, 0x1);
  367. update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
  368. OTAP_DLY_SEL_SHIFT, 2);
  369. update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
  370. DLL_TRIM_ICP_SHIFT, 0x8);
  371. update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
  372. DR_TY_SHIFT, 0x1);
  373. break;
  374. }
  375. /* Reset, init seq called without phy_power_off, this indicates init seq */
  376. tbh_phy->phy_power_sts = PHY_UNINITIALIZED;
  377. }
  378. update_reg(tbh_phy, PHY_CFG_0, RETRIM_EN_MASK, RETRIM_EN_SHIFT, 0x1);
  379. update_reg(tbh_phy, PHY_CFG_0, RETRIM_MASK, RETRIM_SHIFT, 0x0);
  380. return thunderbay_emmc_phy_power(phy, 1);
  381. }
  382. static int thunderbay_emmc_phy_power_off(struct phy *phy)
  383. {
  384. struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
  385. tbh_phy->phy_power_sts = PHY_INITIALIZED;
  386. return thunderbay_emmc_phy_power(phy, 0);
  387. }
  388. static const struct phy_ops thunderbay_emmc_phy_ops = {
  389. .init = thunderbay_emmc_phy_init,
  390. .exit = thunderbay_emmc_phy_exit,
  391. .power_on = thunderbay_emmc_phy_power_on,
  392. .power_off = thunderbay_emmc_phy_power_off,
  393. .owner = THIS_MODULE,
  394. };
  395. static const struct of_device_id thunderbay_emmc_phy_of_match[] = {
  396. { .compatible = "intel,thunderbay-emmc-phy",
  397. (void *)&thunderbay_emmc_phy_ops },
  398. {}
  399. };
  400. MODULE_DEVICE_TABLE(of, thunderbay_emmc_phy_of_match);
  401. static int thunderbay_emmc_phy_probe(struct platform_device *pdev)
  402. {
  403. struct thunderbay_emmc_phy *tbh_phy;
  404. struct phy_provider *phy_provider;
  405. struct device *dev = &pdev->dev;
  406. const struct of_device_id *id;
  407. struct phy *generic_phy;
  408. struct resource *res;
  409. if (!dev->of_node)
  410. return -ENODEV;
  411. tbh_phy = devm_kzalloc(dev, sizeof(*tbh_phy), GFP_KERNEL);
  412. if (!tbh_phy)
  413. return -ENOMEM;
  414. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  415. tbh_phy->reg_base = devm_ioremap_resource(&pdev->dev, res);
  416. if (IS_ERR(tbh_phy->reg_base))
  417. return PTR_ERR(tbh_phy->reg_base);
  418. tbh_phy->phy_power_sts = PHY_UNINITIALIZED;
  419. id = of_match_node(thunderbay_emmc_phy_of_match, pdev->dev.of_node);
  420. if (!id) {
  421. dev_err(dev, "failed to get match_node\n");
  422. return -EINVAL;
  423. }
  424. generic_phy = devm_phy_create(dev, dev->of_node, id->data);
  425. if (IS_ERR(generic_phy)) {
  426. dev_err(dev, "failed to create PHY\n");
  427. return PTR_ERR(generic_phy);
  428. }
  429. phy_set_drvdata(generic_phy, tbh_phy);
  430. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  431. return PTR_ERR_OR_ZERO(phy_provider);
  432. }
  433. static struct platform_driver thunderbay_emmc_phy_driver = {
  434. .probe = thunderbay_emmc_phy_probe,
  435. .driver = {
  436. .name = "thunderbay-emmc-phy",
  437. .of_match_table = thunderbay_emmc_phy_of_match,
  438. },
  439. };
  440. module_platform_driver(thunderbay_emmc_phy_driver);
  441. MODULE_AUTHOR("Nandhini S <nandhini.srikandan@intel.com>");
  442. MODULE_AUTHOR("Rashmi A <rashmi.a@intel.com>");
  443. MODULE_DESCRIPTION("Intel Thunder Bay eMMC PHY driver");
  444. MODULE_LICENSE("GPL v2");