phy-meson-g12a-mipi-dphy-analog.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Meson G12A MIPI DSI Analog PHY
  4. *
  5. * Copyright (C) 2018 Amlogic, Inc. All rights reserved
  6. * Copyright (C) 2022 BayLibre, SAS
  7. * Author: Neil Armstrong <[email protected]>
  8. */
  9. #include <linux/bitfield.h>
  10. #include <linux/bitops.h>
  11. #include <linux/module.h>
  12. #include <linux/phy/phy.h>
  13. #include <linux/regmap.h>
  14. #include <linux/delay.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/platform_device.h>
  17. #include <dt-bindings/phy/phy.h>
  18. #define HHI_MIPI_CNTL0 0x00
  19. #define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)
  20. #define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
  21. #define HHI_MIPI_CNTL1 0x04
  22. #define HHI_MIPI_CNTL1_BANDGAP BIT(16)
  23. #define HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0)
  24. #define HHI_MIPI_CNTL2 0x08
  25. #define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)
  26. #define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
  27. #define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)
  28. #define DSI_LANE_0 BIT(4)
  29. #define DSI_LANE_1 BIT(3)
  30. #define DSI_LANE_CLK BIT(2)
  31. #define DSI_LANE_2 BIT(1)
  32. #define DSI_LANE_3 BIT(0)
  33. struct phy_g12a_mipi_dphy_analog_priv {
  34. struct phy *phy;
  35. struct regmap *regmap;
  36. struct phy_configure_opts_mipi_dphy config;
  37. };
  38. static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy,
  39. union phy_configure_opts *opts)
  40. {
  41. struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
  42. int ret;
  43. ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
  44. if (ret)
  45. return ret;
  46. memcpy(&priv->config, opts, sizeof(priv->config));
  47. return 0;
  48. }
  49. static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy)
  50. {
  51. struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
  52. unsigned int reg;
  53. regmap_write(priv->regmap, HHI_MIPI_CNTL0,
  54. FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8) |
  55. FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0xa487));
  56. regmap_write(priv->regmap, HHI_MIPI_CNTL1,
  57. FIELD_PREP(HHI_MIPI_CNTL2_DIF_REF_CTL2, 0x2e) |
  58. HHI_MIPI_CNTL1_BANDGAP);
  59. regmap_write(priv->regmap, HHI_MIPI_CNTL2,
  60. FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x45a) |
  61. FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680));
  62. reg = DSI_LANE_CLK;
  63. switch (priv->config.lanes) {
  64. case 4:
  65. reg |= DSI_LANE_3;
  66. fallthrough;
  67. case 3:
  68. reg |= DSI_LANE_2;
  69. fallthrough;
  70. case 2:
  71. reg |= DSI_LANE_1;
  72. fallthrough;
  73. case 1:
  74. reg |= DSI_LANE_0;
  75. break;
  76. default:
  77. reg = 0;
  78. }
  79. regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
  80. HHI_MIPI_CNTL2_CH_EN,
  81. FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
  82. return 0;
  83. }
  84. static int phy_g12a_mipi_dphy_analog_power_off(struct phy *phy)
  85. {
  86. struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
  87. regmap_write(priv->regmap, HHI_MIPI_CNTL0, 0);
  88. regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0);
  89. regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0);
  90. return 0;
  91. }
  92. static const struct phy_ops phy_g12a_mipi_dphy_analog_ops = {
  93. .configure = phy_g12a_mipi_dphy_analog_configure,
  94. .power_on = phy_g12a_mipi_dphy_analog_power_on,
  95. .power_off = phy_g12a_mipi_dphy_analog_power_off,
  96. .owner = THIS_MODULE,
  97. };
  98. static int phy_g12a_mipi_dphy_analog_probe(struct platform_device *pdev)
  99. {
  100. struct phy_provider *phy;
  101. struct device *dev = &pdev->dev;
  102. struct phy_g12a_mipi_dphy_analog_priv *priv;
  103. struct device_node *np = dev->of_node, *parent_np;
  104. struct regmap *map;
  105. priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
  106. if (!priv)
  107. return -ENOMEM;
  108. /* Get the hhi system controller node */
  109. parent_np = of_get_parent(np);
  110. map = syscon_node_to_regmap(parent_np);
  111. of_node_put(parent_np);
  112. if (IS_ERR(map))
  113. return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n");
  114. priv->regmap = map;
  115. priv->phy = devm_phy_create(dev, np, &phy_g12a_mipi_dphy_analog_ops);
  116. if (IS_ERR(priv->phy))
  117. return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n");
  118. phy_set_drvdata(priv->phy, priv);
  119. dev_set_drvdata(dev, priv);
  120. phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  121. return PTR_ERR_OR_ZERO(phy);
  122. }
  123. static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
  124. {
  125. .compatible = "amlogic,g12a-mipi-dphy-analog",
  126. },
  127. { /* sentinel */ }
  128. };
  129. MODULE_DEVICE_TABLE(of, phy_g12a_mipi_dphy_analog_of_match);
  130. static struct platform_driver phy_g12a_mipi_dphy_analog_driver = {
  131. .probe = phy_g12a_mipi_dphy_analog_probe,
  132. .driver = {
  133. .name = "phy-meson-g12a-mipi-dphy-analog",
  134. .of_match_table = phy_g12a_mipi_dphy_analog_of_match,
  135. },
  136. };
  137. module_platform_driver(phy_g12a_mipi_dphy_analog_driver);
  138. MODULE_AUTHOR("Neil Armstrong <[email protected]>");
  139. MODULE_DESCRIPTION("Meson G12A MIPI Analog D-PHY driver");
  140. MODULE_LICENSE("GPL v2");