arm-cmn.c 72 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2016-2020 Arm Limited
  3. // CMN-600 Coherent Mesh Network PMU driver
  4. #include <linux/acpi.h>
  5. #include <linux/bitfield.h>
  6. #include <linux/bitops.h>
  7. #include <linux/debugfs.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/io-64-nonatomic-lo-hi.h>
  11. #include <linux/kernel.h>
  12. #include <linux/list.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/perf_event.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/sort.h>
  19. /* Common register stuff */
  20. #define CMN_NODE_INFO 0x0000
  21. #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0)
  22. #define CMN_NI_NODE_ID GENMASK_ULL(31, 16)
  23. #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32)
  24. #define CMN_NODEID_DEVID(reg) ((reg) & 3)
  25. #define CMN_NODEID_EXT_DEVID(reg) ((reg) & 1)
  26. #define CMN_NODEID_PID(reg) (((reg) >> 2) & 1)
  27. #define CMN_NODEID_EXT_PID(reg) (((reg) >> 1) & 3)
  28. #define CMN_NODEID_1x1_PID(reg) (((reg) >> 2) & 7)
  29. #define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits)))
  30. #define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1))
  31. #define CMN_CHILD_INFO 0x0080
  32. #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0)
  33. #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16)
  34. #define CMN_CHILD_NODE_ADDR GENMASK(29, 0)
  35. #define CMN_CHILD_NODE_EXTERNAL BIT(31)
  36. #define CMN_MAX_DIMENSION 12
  37. #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)
  38. #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
  39. /* The CFG node has various info besides the discovery tree */
  40. #define CMN_CFGM_PERIPH_ID_01 0x0008
  41. #define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0)
  42. #define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32)
  43. #define CMN_CFGM_PERIPH_ID_23 0x0010
  44. #define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4)
  45. #define CMN_CFGM_INFO_GLOBAL 0x900
  46. #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63)
  47. #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52)
  48. #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50)
  49. #define CMN_CFGM_INFO_GLOBAL_1 0x908
  50. #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2)
  51. #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0)
  52. /* XPs also have some local topology info which has uses too */
  53. #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p))
  54. #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(4, 0)
  55. #define CMN_MAX_PORTS 6
  56. #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10
  57. /* PMU registers occupy the 3rd 4KB page of each node's region */
  58. #define CMN_PMU_OFFSET 0x2000
  59. /* For most nodes, this is all there is */
  60. #define CMN_PMU_EVENT_SEL 0x000
  61. #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42)
  62. #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35)
  63. /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */
  64. #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32)
  65. /* HN-Ps are weird... */
  66. #define CMN_HNP_PMU_EVENT_SEL 0x008
  67. /* DTMs live in the PMU space of XP registers */
  68. #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18)
  69. #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00)
  70. #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19)
  71. #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17)
  72. #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9)
  73. #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8)
  74. #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6)
  75. #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
  76. #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4)
  77. #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1)
  78. #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0)
  79. #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08)
  80. #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10)
  81. #define CMN_DTM_PMU_CONFIG 0x210
  82. #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32)
  83. #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00
  84. #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04
  85. #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10
  86. #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16)
  87. #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4)
  88. #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n))
  89. #define CMN__PMEVCNT23_COMBINED BIT(2)
  90. #define CMN__PMEVCNT01_COMBINED BIT(1)
  91. #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0)
  92. #define CMN_DTM_PMEVCNT 0x220
  93. #define CMN_DTM_PMEVCNTSR 0x240
  94. #define CMN650_DTM_UNIT_INFO 0x0910
  95. #define CMN_DTM_UNIT_INFO 0x0960
  96. #define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0)
  97. #define CMN_DTM_NUM_COUNTERS 4
  98. /* Want more local counters? Why not replicate the whole DTM! Ugh... */
  99. #define CMN_DTM_OFFSET(n) ((n) * 0x200)
  100. /* The DTC node is where the magic happens */
  101. #define CMN_DT_DTC_CTL 0x0a00
  102. #define CMN_DT_DTC_CTL_DT_EN BIT(0)
  103. /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
  104. #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4)
  105. #define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n))
  106. #define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40)
  107. #define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n))
  108. #define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90)
  109. #define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100)
  110. #define CMN_DT_PMCR_PMU_EN BIT(0)
  111. #define CMN_DT_PMCR_CNTR_RST BIT(5)
  112. #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6)
  113. #define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118)
  114. #define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120)
  115. #define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128)
  116. #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n)
  117. #define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130)
  118. #define CMN_DT_PMSRR_SS_REQ BIT(0)
  119. #define CMN_DT_NUM_COUNTERS 8
  120. #define CMN_MAX_DTCS 4
  121. /*
  122. * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
  123. * so throwing away one bit to make overflow handling easy is no big deal.
  124. */
  125. #define CMN_COUNTER_INIT 0x80000000
  126. /* Similarly for the 40-bit cycle counter */
  127. #define CMN_CC_INIT 0x8000000000ULL
  128. /* Event attributes */
  129. #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0)
  130. #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16)
  131. #define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27)
  132. #define CMN_CONFIG_BYNODEID BIT_ULL(31)
  133. #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32)
  134. #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
  135. #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
  136. #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
  137. #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
  138. #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
  139. #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27)
  140. #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48)
  141. #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51)
  142. /* Note that we don't yet support the tertiary match group on newer IPs */
  143. #define CMN_CONFIG_WP_GRP BIT_ULL(56)
  144. #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(57)
  145. #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0)
  146. #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0)
  147. #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
  148. #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
  149. #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
  150. #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
  151. #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
  152. #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
  153. #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
  154. /* Made-up event IDs for watchpoint direction */
  155. #define CMN_WP_UP 0
  156. #define CMN_WP_DOWN 2
  157. /* Internal values for encoding event support */
  158. enum cmn_model {
  159. CMN600 = 1,
  160. CMN650 = 2,
  161. CMN700 = 4,
  162. CI700 = 8,
  163. /* ...and then we can use bitmap tricks for commonality */
  164. CMN_ANY = -1,
  165. NOT_CMN600 = -2,
  166. CMN_650ON = CMN650 | CMN700,
  167. };
  168. /* Actual part numbers and revision IDs defined by the hardware */
  169. enum cmn_part {
  170. PART_CMN600 = 0x434,
  171. PART_CMN650 = 0x436,
  172. PART_CMN700 = 0x43c,
  173. PART_CI700 = 0x43a,
  174. };
  175. /* CMN-600 r0px shouldn't exist in silicon, thankfully */
  176. enum cmn_revision {
  177. REV_CMN600_R1P0,
  178. REV_CMN600_R1P1,
  179. REV_CMN600_R1P2,
  180. REV_CMN600_R1P3,
  181. REV_CMN600_R2P0,
  182. REV_CMN600_R3P0,
  183. REV_CMN600_R3P1,
  184. REV_CMN650_R0P0 = 0,
  185. REV_CMN650_R1P0,
  186. REV_CMN650_R1P1,
  187. REV_CMN650_R2P0,
  188. REV_CMN650_R1P2,
  189. REV_CMN700_R0P0 = 0,
  190. REV_CMN700_R1P0,
  191. REV_CMN700_R2P0,
  192. REV_CI700_R0P0 = 0,
  193. REV_CI700_R1P0,
  194. REV_CI700_R2P0,
  195. };
  196. enum cmn_node_type {
  197. CMN_TYPE_INVALID,
  198. CMN_TYPE_DVM,
  199. CMN_TYPE_CFG,
  200. CMN_TYPE_DTC,
  201. CMN_TYPE_HNI,
  202. CMN_TYPE_HNF,
  203. CMN_TYPE_XP,
  204. CMN_TYPE_SBSX,
  205. CMN_TYPE_MPAM_S,
  206. CMN_TYPE_MPAM_NS,
  207. CMN_TYPE_RNI,
  208. CMN_TYPE_RND = 0xd,
  209. CMN_TYPE_RNSAM = 0xf,
  210. CMN_TYPE_MTSX,
  211. CMN_TYPE_HNP,
  212. CMN_TYPE_CXRA = 0x100,
  213. CMN_TYPE_CXHA,
  214. CMN_TYPE_CXLA,
  215. CMN_TYPE_CCRA,
  216. CMN_TYPE_CCHA,
  217. CMN_TYPE_CCLA,
  218. CMN_TYPE_CCLA_RNI,
  219. /* Not a real node type */
  220. CMN_TYPE_WP = 0x7770
  221. };
  222. enum cmn_filter_select {
  223. SEL_NONE = -1,
  224. SEL_OCCUP1ID,
  225. SEL_CLASS_OCCUP_ID,
  226. SEL_CBUSY_SNTHROTTLE_SEL,
  227. SEL_MAX
  228. };
  229. struct arm_cmn_node {
  230. void __iomem *pmu_base;
  231. u16 id, logid;
  232. enum cmn_node_type type;
  233. int dtm;
  234. union {
  235. /* DN/HN-F/CXHA */
  236. struct {
  237. u8 val : 4;
  238. u8 count : 4;
  239. } occupid[SEL_MAX];
  240. /* XP */
  241. u8 dtc;
  242. };
  243. union {
  244. u8 event[4];
  245. __le32 event_sel;
  246. u16 event_w[4];
  247. __le64 event_sel_w;
  248. };
  249. };
  250. struct arm_cmn_dtm {
  251. void __iomem *base;
  252. u32 pmu_config_low;
  253. union {
  254. u8 input_sel[4];
  255. __le32 pmu_config_high;
  256. };
  257. s8 wp_event[4];
  258. };
  259. struct arm_cmn_dtc {
  260. void __iomem *base;
  261. int irq;
  262. int irq_friend;
  263. bool cc_active;
  264. struct perf_event *counters[CMN_DT_NUM_COUNTERS];
  265. struct perf_event *cycles;
  266. };
  267. #define CMN_STATE_DISABLED BIT(0)
  268. #define CMN_STATE_TXN BIT(1)
  269. struct arm_cmn {
  270. struct device *dev;
  271. void __iomem *base;
  272. unsigned int state;
  273. enum cmn_revision rev;
  274. enum cmn_part part;
  275. u8 mesh_x;
  276. u8 mesh_y;
  277. u16 num_xps;
  278. u16 num_dns;
  279. bool multi_dtm;
  280. u8 ports_used;
  281. struct {
  282. unsigned int rsp_vc_num : 2;
  283. unsigned int dat_vc_num : 2;
  284. unsigned int snp_vc_num : 2;
  285. unsigned int req_vc_num : 2;
  286. };
  287. struct arm_cmn_node *xps;
  288. struct arm_cmn_node *dns;
  289. struct arm_cmn_dtm *dtms;
  290. struct arm_cmn_dtc *dtc;
  291. unsigned int num_dtcs;
  292. int cpu;
  293. struct hlist_node cpuhp_node;
  294. struct pmu pmu;
  295. struct dentry *debug;
  296. };
  297. #define to_cmn(p) container_of(p, struct arm_cmn, pmu)
  298. static int arm_cmn_hp_state;
  299. struct arm_cmn_nodeid {
  300. u8 x;
  301. u8 y;
  302. u8 port;
  303. u8 dev;
  304. };
  305. static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
  306. {
  307. return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1) | 2);
  308. }
  309. static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id)
  310. {
  311. struct arm_cmn_nodeid nid;
  312. if (cmn->num_xps == 1) {
  313. nid.x = 0;
  314. nid.y = 0;
  315. nid.port = CMN_NODEID_1x1_PID(id);
  316. nid.dev = CMN_NODEID_DEVID(id);
  317. } else {
  318. int bits = arm_cmn_xyidbits(cmn);
  319. nid.x = CMN_NODEID_X(id, bits);
  320. nid.y = CMN_NODEID_Y(id, bits);
  321. if (cmn->ports_used & 0xc) {
  322. nid.port = CMN_NODEID_EXT_PID(id);
  323. nid.dev = CMN_NODEID_EXT_DEVID(id);
  324. } else {
  325. nid.port = CMN_NODEID_PID(id);
  326. nid.dev = CMN_NODEID_DEVID(id);
  327. }
  328. }
  329. return nid;
  330. }
  331. static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn,
  332. const struct arm_cmn_node *dn)
  333. {
  334. struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
  335. int xp_idx = cmn->mesh_x * nid.y + nid.x;
  336. return cmn->xps + xp_idx;
  337. }
  338. static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
  339. enum cmn_node_type type)
  340. {
  341. struct arm_cmn_node *dn;
  342. for (dn = cmn->dns; dn->type; dn++)
  343. if (dn->type == type)
  344. return dn;
  345. return NULL;
  346. }
  347. static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn)
  348. {
  349. switch (cmn->part) {
  350. case PART_CMN600:
  351. return CMN600;
  352. case PART_CMN650:
  353. return CMN650;
  354. case PART_CMN700:
  355. return CMN700;
  356. case PART_CI700:
  357. return CI700;
  358. default:
  359. return 0;
  360. };
  361. }
  362. static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn,
  363. const struct arm_cmn_node *xp, int port)
  364. {
  365. int offset = CMN_MXP__CONNECT_INFO(port);
  366. if (port >= 2) {
  367. if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650)
  368. return 0;
  369. /*
  370. * CI-700 may have extra ports, but still has the
  371. * mesh_port_connect_info registers in the way.
  372. */
  373. if (cmn->part == PART_CI700)
  374. offset += CI700_CONNECT_INFO_P2_5_OFFSET;
  375. }
  376. return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset);
  377. }
  378. static struct dentry *arm_cmn_debugfs;
  379. #ifdef CONFIG_DEBUG_FS
  380. static const char *arm_cmn_device_type(u8 type)
  381. {
  382. switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) {
  383. case 0x00: return " |";
  384. case 0x01: return " RN-I |";
  385. case 0x02: return " RN-D |";
  386. case 0x04: return " RN-F_B |";
  387. case 0x05: return "RN-F_B_E|";
  388. case 0x06: return " RN-F_A |";
  389. case 0x07: return "RN-F_A_E|";
  390. case 0x08: return " HN-T |";
  391. case 0x09: return " HN-I |";
  392. case 0x0a: return " HN-D |";
  393. case 0x0b: return " HN-P |";
  394. case 0x0c: return " SN-F |";
  395. case 0x0d: return " SBSX |";
  396. case 0x0e: return " HN-F |";
  397. case 0x0f: return " SN-F_E |";
  398. case 0x10: return " SN-F_D |";
  399. case 0x11: return " CXHA |";
  400. case 0x12: return " CXRA |";
  401. case 0x13: return " CXRH |";
  402. case 0x14: return " RN-F_D |";
  403. case 0x15: return "RN-F_D_E|";
  404. case 0x16: return " RN-F_C |";
  405. case 0x17: return "RN-F_C_E|";
  406. case 0x18: return " RN-F_E |";
  407. case 0x19: return "RN-F_E_E|";
  408. case 0x1c: return " MTSX |";
  409. case 0x1d: return " HN-V |";
  410. case 0x1e: return " CCG |";
  411. default: return " ???? |";
  412. }
  413. }
  414. static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d)
  415. {
  416. struct arm_cmn *cmn = s->private;
  417. struct arm_cmn_node *dn;
  418. for (dn = cmn->dns; dn->type; dn++) {
  419. struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
  420. if (dn->type == CMN_TYPE_XP)
  421. continue;
  422. /* Ignore the extra components that will overlap on some ports */
  423. if (dn->type < CMN_TYPE_HNI)
  424. continue;
  425. if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d)
  426. continue;
  427. seq_printf(s, " #%-2d |", dn->logid);
  428. return;
  429. }
  430. seq_puts(s, " |");
  431. }
  432. static int arm_cmn_map_show(struct seq_file *s, void *data)
  433. {
  434. struct arm_cmn *cmn = s->private;
  435. int x, y, p, pmax = fls(cmn->ports_used);
  436. seq_puts(s, " X");
  437. for (x = 0; x < cmn->mesh_x; x++)
  438. seq_printf(s, " %d ", x);
  439. seq_puts(s, "\nY P D+");
  440. y = cmn->mesh_y;
  441. while (y--) {
  442. int xp_base = cmn->mesh_x * y;
  443. u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION];
  444. for (x = 0; x < cmn->mesh_x; x++)
  445. seq_puts(s, "--------+");
  446. seq_printf(s, "\n%d |", y);
  447. for (x = 0; x < cmn->mesh_x; x++) {
  448. struct arm_cmn_node *xp = cmn->xps + xp_base + x;
  449. for (p = 0; p < CMN_MAX_PORTS; p++)
  450. port[p][x] = arm_cmn_device_connect_info(cmn, xp, p);
  451. seq_printf(s, " XP #%-2d |", xp_base + x);
  452. }
  453. seq_puts(s, "\n |");
  454. for (x = 0; x < cmn->mesh_x; x++) {
  455. u8 dtc = cmn->xps[xp_base + x].dtc;
  456. if (dtc & (dtc - 1))
  457. seq_puts(s, " DTC ?? |");
  458. else
  459. seq_printf(s, " DTC %ld |", __ffs(dtc));
  460. }
  461. seq_puts(s, "\n |");
  462. for (x = 0; x < cmn->mesh_x; x++)
  463. seq_puts(s, "........|");
  464. for (p = 0; p < pmax; p++) {
  465. seq_printf(s, "\n %d |", p);
  466. for (x = 0; x < cmn->mesh_x; x++)
  467. seq_puts(s, arm_cmn_device_type(port[p][x]));
  468. seq_puts(s, "\n 0|");
  469. for (x = 0; x < cmn->mesh_x; x++)
  470. arm_cmn_show_logid(s, x, y, p, 0);
  471. seq_puts(s, "\n 1|");
  472. for (x = 0; x < cmn->mesh_x; x++)
  473. arm_cmn_show_logid(s, x, y, p, 1);
  474. }
  475. seq_puts(s, "\n-----+");
  476. }
  477. for (x = 0; x < cmn->mesh_x; x++)
  478. seq_puts(s, "--------+");
  479. seq_puts(s, "\n");
  480. return 0;
  481. }
  482. DEFINE_SHOW_ATTRIBUTE(arm_cmn_map);
  483. static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id)
  484. {
  485. const char *name = "map";
  486. if (id > 0)
  487. name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id);
  488. if (!name)
  489. return;
  490. cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops);
  491. }
  492. #else
  493. static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {}
  494. #endif
  495. struct arm_cmn_hw_event {
  496. struct arm_cmn_node *dn;
  497. u64 dtm_idx[4];
  498. unsigned int dtc_idx;
  499. u8 dtcs_used;
  500. u8 num_dns;
  501. u8 dtm_offset;
  502. bool wide_sel;
  503. enum cmn_filter_select filter_sel;
  504. };
  505. #define for_each_hw_dn(hw, dn, i) \
  506. for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
  507. static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
  508. {
  509. BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target));
  510. return (struct arm_cmn_hw_event *)&event->hw;
  511. }
  512. static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
  513. {
  514. x[pos / 32] |= (u64)val << ((pos % 32) * 2);
  515. }
  516. static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
  517. {
  518. return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
  519. }
  520. struct arm_cmn_event_attr {
  521. struct device_attribute attr;
  522. enum cmn_model model;
  523. enum cmn_node_type type;
  524. enum cmn_filter_select fsel;
  525. u16 eventid;
  526. u8 occupid;
  527. };
  528. struct arm_cmn_format_attr {
  529. struct device_attribute attr;
  530. u64 field;
  531. int config;
  532. };
  533. #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\
  534. (&((struct arm_cmn_event_attr[]) {{ \
  535. .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \
  536. .model = _model, \
  537. .type = _type, \
  538. .eventid = _eventid, \
  539. .occupid = _occupid, \
  540. .fsel = _fsel, \
  541. }})[0].attr.attr)
  542. #define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \
  543. _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE)
  544. static ssize_t arm_cmn_event_show(struct device *dev,
  545. struct device_attribute *attr, char *buf)
  546. {
  547. struct arm_cmn_event_attr *eattr;
  548. eattr = container_of(attr, typeof(*eattr), attr);
  549. if (eattr->type == CMN_TYPE_DTC)
  550. return sysfs_emit(buf, "type=0x%x\n", eattr->type);
  551. if (eattr->type == CMN_TYPE_WP)
  552. return sysfs_emit(buf,
  553. "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
  554. eattr->type, eattr->eventid);
  555. if (eattr->fsel > SEL_NONE)
  556. return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
  557. eattr->type, eattr->eventid, eattr->occupid);
  558. return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type,
  559. eattr->eventid);
  560. }
  561. static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
  562. struct attribute *attr,
  563. int unused)
  564. {
  565. struct device *dev = kobj_to_dev(kobj);
  566. struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
  567. struct arm_cmn_event_attr *eattr;
  568. enum cmn_node_type type;
  569. u16 eventid;
  570. eattr = container_of(attr, typeof(*eattr), attr.attr);
  571. if (!(eattr->model & arm_cmn_model(cmn)))
  572. return 0;
  573. type = eattr->type;
  574. eventid = eattr->eventid;
  575. /* Watchpoints aren't nodes, so avoid confusion */
  576. if (type == CMN_TYPE_WP)
  577. return attr->mode;
  578. /* Hide XP events for unused interfaces/channels */
  579. if (type == CMN_TYPE_XP) {
  580. unsigned int intf = (eventid >> 2) & 7;
  581. unsigned int chan = eventid >> 5;
  582. if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3)))
  583. return 0;
  584. if (chan == 4 && cmn->part == PART_CMN600)
  585. return 0;
  586. if ((chan == 5 && cmn->rsp_vc_num < 2) ||
  587. (chan == 6 && cmn->dat_vc_num < 2) ||
  588. (chan == 7 && cmn->snp_vc_num < 2) ||
  589. (chan == 8 && cmn->req_vc_num < 2))
  590. return 0;
  591. }
  592. /* Revision-specific differences */
  593. if (cmn->part == PART_CMN600) {
  594. if (cmn->rev < REV_CMN600_R1P3) {
  595. if (type == CMN_TYPE_CXRA && eventid > 0x10)
  596. return 0;
  597. }
  598. if (cmn->rev < REV_CMN600_R1P2) {
  599. if (type == CMN_TYPE_HNF && eventid == 0x1b)
  600. return 0;
  601. if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA)
  602. return 0;
  603. }
  604. } else if (cmn->part == PART_CMN650) {
  605. if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) {
  606. if (type == CMN_TYPE_HNF && eventid > 0x22)
  607. return 0;
  608. if (type == CMN_TYPE_SBSX && eventid == 0x17)
  609. return 0;
  610. if (type == CMN_TYPE_RNI && eventid > 0x10)
  611. return 0;
  612. }
  613. } else if (cmn->part == PART_CMN700) {
  614. if (cmn->rev < REV_CMN700_R2P0) {
  615. if (type == CMN_TYPE_HNF && eventid > 0x2c)
  616. return 0;
  617. if (type == CMN_TYPE_CCHA && eventid > 0x74)
  618. return 0;
  619. if (type == CMN_TYPE_CCLA && eventid > 0x27)
  620. return 0;
  621. }
  622. if (cmn->rev < REV_CMN700_R1P0) {
  623. if (type == CMN_TYPE_HNF && eventid > 0x2b)
  624. return 0;
  625. }
  626. }
  627. if (!arm_cmn_node(cmn, type))
  628. return 0;
  629. return attr->mode;
  630. }
  631. #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \
  632. _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel)
  633. #define CMN_EVENT_DTC(_name) \
  634. CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0)
  635. #define _CMN_EVENT_HNF(_model, _name, _event, _occup, _fsel) \
  636. _CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event, _occup, _fsel)
  637. #define CMN_EVENT_HNI(_name, _event) \
  638. CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event)
  639. #define CMN_EVENT_HNP(_name, _event) \
  640. CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event)
  641. #define __CMN_EVENT_XP(_name, _event) \
  642. CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event)
  643. #define CMN_EVENT_SBSX(_model, _name, _event) \
  644. CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event)
  645. #define CMN_EVENT_RNID(_model, _name, _event) \
  646. CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event)
  647. #define CMN_EVENT_MTSX(_name, _event) \
  648. CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event)
  649. #define CMN_EVENT_CXRA(_model, _name, _event) \
  650. CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event)
  651. #define CMN_EVENT_CXHA(_name, _event) \
  652. CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event)
  653. #define CMN_EVENT_CCRA(_name, _event) \
  654. CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event)
  655. #define CMN_EVENT_CCHA(_name, _event) \
  656. CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event)
  657. #define CMN_EVENT_CCLA(_name, _event) \
  658. CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event)
  659. #define CMN_EVENT_CCLA_RNI(_name, _event) \
  660. CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event)
  661. #define CMN_EVENT_DVM(_model, _name, _event) \
  662. _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE)
  663. #define CMN_EVENT_DVM_OCC(_model, _name, _event) \
  664. _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID), \
  665. _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \
  666. _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID)
  667. #define CMN_EVENT_HNF(_model, _name, _event) \
  668. _CMN_EVENT_HNF(_model, _name, _event, 0, SEL_NONE)
  669. #define CMN_EVENT_HNF_CLS(_model, _name, _event) \
  670. _CMN_EVENT_HNF(_model, _name##_class0, _event, 0, SEL_CLASS_OCCUP_ID), \
  671. _CMN_EVENT_HNF(_model, _name##_class1, _event, 1, SEL_CLASS_OCCUP_ID), \
  672. _CMN_EVENT_HNF(_model, _name##_class2, _event, 2, SEL_CLASS_OCCUP_ID), \
  673. _CMN_EVENT_HNF(_model, _name##_class3, _event, 3, SEL_CLASS_OCCUP_ID)
  674. #define CMN_EVENT_HNF_SNT(_model, _name, _event) \
  675. _CMN_EVENT_HNF(_model, _name##_all, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \
  676. _CMN_EVENT_HNF(_model, _name##_group0_read, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \
  677. _CMN_EVENT_HNF(_model, _name##_group0_write, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \
  678. _CMN_EVENT_HNF(_model, _name##_group1_read, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \
  679. _CMN_EVENT_HNF(_model, _name##_group1_write, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \
  680. _CMN_EVENT_HNF(_model, _name##_read, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \
  681. _CMN_EVENT_HNF(_model, _name##_write, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL)
  682. #define _CMN_EVENT_XP(_name, _event) \
  683. __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \
  684. __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \
  685. __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \
  686. __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)), \
  687. __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \
  688. __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \
  689. __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \
  690. __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2))
  691. /* Good thing there are only 3 fundamental XP events... */
  692. #define CMN_EVENT_XP(_name, _event) \
  693. _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \
  694. _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \
  695. _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \
  696. _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \
  697. _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \
  698. _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \
  699. _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \
  700. _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)), \
  701. _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5))
  702. static struct attribute *arm_cmn_event_attrs[] = {
  703. CMN_EVENT_DTC(cycles),
  704. /*
  705. * DVM node events conflict with HN-I events in the equivalent PMU
  706. * slot, but our lazy short-cut of using the DTM counter index for
  707. * the PMU index as well happens to avoid that by construction.
  708. */
  709. CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01),
  710. CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02),
  711. CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03),
  712. CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04),
  713. CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05),
  714. CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01),
  715. CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02),
  716. CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03),
  717. CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04),
  718. CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05),
  719. CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06),
  720. CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07),
  721. CMN_EVENT_DVM(NOT_CMN600, retry, 0x08),
  722. CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09),
  723. CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a),
  724. CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b),
  725. CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c),
  726. CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha, 0x0d),
  727. CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn, 0x0e),
  728. CMN_EVENT_DVM(CMN700, trk_alloc, 0x0f),
  729. CMN_EVENT_DVM(CMN700, trk_cxha_alloc, 0x10),
  730. CMN_EVENT_DVM(CMN700, trk_pdn_alloc, 0x11),
  731. CMN_EVENT_DVM(CMN700, txsnp_stall_limit, 0x12),
  732. CMN_EVENT_DVM(CMN700, rxsnp_stall_starv, 0x13),
  733. CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op, 0x14),
  734. CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01),
  735. CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02),
  736. CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03),
  737. CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04),
  738. CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05),
  739. CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06),
  740. CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07),
  741. CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08),
  742. CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09),
  743. CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a),
  744. CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b),
  745. CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c),
  746. CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d),
  747. CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e),
  748. _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_all, 0x0f, 0, SEL_OCCUP1ID),
  749. _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_read, 0x0f, 1, SEL_OCCUP1ID),
  750. _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_write, 0x0f, 2, SEL_OCCUP1ID),
  751. _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_atomic, 0x0f, 3, SEL_OCCUP1ID),
  752. _CMN_EVENT_HNF(CMN_ANY, qos_pocq_occupancy_stash, 0x0f, 4, SEL_OCCUP1ID),
  753. CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10),
  754. CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11),
  755. CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12),
  756. CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13),
  757. CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14),
  758. CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15),
  759. CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16),
  760. CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17),
  761. CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18),
  762. CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19),
  763. CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a),
  764. CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b),
  765. CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c),
  766. CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d),
  767. CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e),
  768. CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f),
  769. CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20),
  770. CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21),
  771. CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22),
  772. CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23),
  773. CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24),
  774. CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25),
  775. CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26),
  776. CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27),
  777. CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28),
  778. CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29),
  779. CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a),
  780. CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b),
  781. CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c),
  782. CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d),
  783. CMN_EVENT_HNF(CMN700, nc_excl, 0x2e),
  784. CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f),
  785. CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20),
  786. CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21),
  787. CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22),
  788. CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23),
  789. CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24),
  790. CMN_EVENT_HNI(rrt_rd_alloc, 0x25),
  791. CMN_EVENT_HNI(rrt_wr_alloc, 0x26),
  792. CMN_EVENT_HNI(rdt_rd_alloc, 0x27),
  793. CMN_EVENT_HNI(rdt_wr_alloc, 0x28),
  794. CMN_EVENT_HNI(wdb_alloc, 0x29),
  795. CMN_EVENT_HNI(txrsp_retryack, 0x2a),
  796. CMN_EVENT_HNI(arvalid_no_arready, 0x2b),
  797. CMN_EVENT_HNI(arready_no_arvalid, 0x2c),
  798. CMN_EVENT_HNI(awvalid_no_awready, 0x2d),
  799. CMN_EVENT_HNI(awready_no_awvalid, 0x2e),
  800. CMN_EVENT_HNI(wvalid_no_wready, 0x2f),
  801. CMN_EVENT_HNI(txdat_stall, 0x30),
  802. CMN_EVENT_HNI(nonpcie_serialization, 0x31),
  803. CMN_EVENT_HNI(pcie_serialization, 0x32),
  804. /*
  805. * HN-P events squat on top of the HN-I similarly to DVM events, except
  806. * for being crammed into the same physical node as well. And of course
  807. * where would the fun be if the same events were in the same order...
  808. */
  809. CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01),
  810. CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02),
  811. CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03),
  812. CMN_EVENT_HNP(rrt_wr_alloc, 0x04),
  813. CMN_EVENT_HNP(rdt_wr_alloc, 0x05),
  814. CMN_EVENT_HNP(wdb_alloc, 0x06),
  815. CMN_EVENT_HNP(awvalid_no_awready, 0x07),
  816. CMN_EVENT_HNP(awready_no_awvalid, 0x08),
  817. CMN_EVENT_HNP(wvalid_no_wready, 0x09),
  818. CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11),
  819. CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12),
  820. CMN_EVENT_HNP(rrt_rd_alloc, 0x13),
  821. CMN_EVENT_HNP(rdt_rd_alloc, 0x14),
  822. CMN_EVENT_HNP(arvalid_no_arready, 0x15),
  823. CMN_EVENT_HNP(arready_no_arvalid, 0x16),
  824. CMN_EVENT_XP(txflit_valid, 0x01),
  825. CMN_EVENT_XP(txflit_stall, 0x02),
  826. CMN_EVENT_XP(partial_dat_flit, 0x03),
  827. /* We treat watchpoints as a special made-up class of XP events */
  828. CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP),
  829. CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN),
  830. CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01),
  831. CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02),
  832. CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03),
  833. CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04),
  834. CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05),
  835. CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06),
  836. CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11),
  837. CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12),
  838. CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13),
  839. CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14),
  840. CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15),
  841. CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16),
  842. CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17),
  843. CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21),
  844. CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22),
  845. CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23),
  846. CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24),
  847. CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25),
  848. CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01),
  849. CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02),
  850. CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03),
  851. CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04),
  852. CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05),
  853. CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06),
  854. CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07),
  855. CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08),
  856. CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09),
  857. CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a),
  858. CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b),
  859. CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c),
  860. CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d),
  861. CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e),
  862. CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f),
  863. CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10),
  864. CMN_EVENT_RNID(CMN600, rdb_unord, 0x11),
  865. CMN_EVENT_RNID(CMN600, rdb_replay, 0x12),
  866. CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13),
  867. CMN_EVENT_RNID(CMN600, rdb_ord, 0x14),
  868. CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11),
  869. CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12),
  870. CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13),
  871. CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14),
  872. CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15),
  873. CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16),
  874. CMN_EVENT_RNID(CMN700, ldb_full, 0x17),
  875. CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18),
  876. CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19),
  877. CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a),
  878. CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b),
  879. CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c),
  880. CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d),
  881. CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e),
  882. CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f),
  883. CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20),
  884. CMN_EVENT_RNID(CMN700, awid_hash, 0x21),
  885. CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22),
  886. CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23),
  887. CMN_EVENT_MTSX(tc_lookup, 0x01),
  888. CMN_EVENT_MTSX(tc_fill, 0x02),
  889. CMN_EVENT_MTSX(tc_miss, 0x03),
  890. CMN_EVENT_MTSX(tdb_forward, 0x04),
  891. CMN_EVENT_MTSX(tcq_hazard, 0x05),
  892. CMN_EVENT_MTSX(tcq_rd_alloc, 0x06),
  893. CMN_EVENT_MTSX(tcq_wr_alloc, 0x07),
  894. CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08),
  895. CMN_EVENT_MTSX(axi_rd_req, 0x09),
  896. CMN_EVENT_MTSX(axi_wr_req, 0x0a),
  897. CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b),
  898. CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c),
  899. CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01),
  900. CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02),
  901. CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03),
  902. CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04),
  903. CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05),
  904. CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06),
  905. CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07),
  906. CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08),
  907. CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09),
  908. CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a),
  909. CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b),
  910. CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c),
  911. CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d),
  912. CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e),
  913. CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f),
  914. CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10),
  915. CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11),
  916. CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12),
  917. CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13),
  918. CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14),
  919. CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15),
  920. CMN_EVENT_CXHA(rddatbyp, 0x21),
  921. CMN_EVENT_CXHA(chirsp_up_stall, 0x22),
  922. CMN_EVENT_CXHA(chidat_up_stall, 0x23),
  923. CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24),
  924. CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25),
  925. CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26),
  926. CMN_EVENT_CXHA(reqtrk_occ, 0x27),
  927. CMN_EVENT_CXHA(rdb_occ, 0x28),
  928. CMN_EVENT_CXHA(rdbyp_occ, 0x29),
  929. CMN_EVENT_CXHA(wdb_occ, 0x2a),
  930. CMN_EVENT_CXHA(snptrk_occ, 0x2b),
  931. CMN_EVENT_CXHA(sdb_occ, 0x2c),
  932. CMN_EVENT_CXHA(snphaz_occ, 0x2d),
  933. CMN_EVENT_CCRA(rht_occ, 0x41),
  934. CMN_EVENT_CCRA(sht_occ, 0x42),
  935. CMN_EVENT_CCRA(rdb_occ, 0x43),
  936. CMN_EVENT_CCRA(wdb_occ, 0x44),
  937. CMN_EVENT_CCRA(ssb_occ, 0x45),
  938. CMN_EVENT_CCRA(snp_bcasts, 0x46),
  939. CMN_EVENT_CCRA(req_chains, 0x47),
  940. CMN_EVENT_CCRA(req_chain_avglen, 0x48),
  941. CMN_EVENT_CCRA(chirsp_stalls, 0x49),
  942. CMN_EVENT_CCRA(chidat_stalls, 0x4a),
  943. CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b),
  944. CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c),
  945. CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d),
  946. CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e),
  947. CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f),
  948. CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50),
  949. CMN_EVENT_CCRA(external_chirsp_stalls, 0x51),
  950. CMN_EVENT_CCRA(external_chidat_stalls, 0x52),
  951. CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53),
  952. CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54),
  953. CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55),
  954. CMN_EVENT_CCRA(rht_alloc, 0x56),
  955. CMN_EVENT_CCRA(sht_alloc, 0x57),
  956. CMN_EVENT_CCRA(rdb_alloc, 0x58),
  957. CMN_EVENT_CCRA(wdb_alloc, 0x59),
  958. CMN_EVENT_CCRA(ssb_alloc, 0x5a),
  959. CMN_EVENT_CCHA(rddatbyp, 0x61),
  960. CMN_EVENT_CCHA(chirsp_up_stall, 0x62),
  961. CMN_EVENT_CCHA(chidat_up_stall, 0x63),
  962. CMN_EVENT_CCHA(snppcrd_link0_stall, 0x64),
  963. CMN_EVENT_CCHA(snppcrd_link1_stall, 0x65),
  964. CMN_EVENT_CCHA(snppcrd_link2_stall, 0x66),
  965. CMN_EVENT_CCHA(reqtrk_occ, 0x67),
  966. CMN_EVENT_CCHA(rdb_occ, 0x68),
  967. CMN_EVENT_CCHA(rdbyp_occ, 0x69),
  968. CMN_EVENT_CCHA(wdb_occ, 0x6a),
  969. CMN_EVENT_CCHA(snptrk_occ, 0x6b),
  970. CMN_EVENT_CCHA(sdb_occ, 0x6c),
  971. CMN_EVENT_CCHA(snphaz_occ, 0x6d),
  972. CMN_EVENT_CCHA(reqtrk_alloc, 0x6e),
  973. CMN_EVENT_CCHA(rdb_alloc, 0x6f),
  974. CMN_EVENT_CCHA(rdbyp_alloc, 0x70),
  975. CMN_EVENT_CCHA(wdb_alloc, 0x71),
  976. CMN_EVENT_CCHA(snptrk_alloc, 0x72),
  977. CMN_EVENT_CCHA(sdb_alloc, 0x73),
  978. CMN_EVENT_CCHA(snphaz_alloc, 0x74),
  979. CMN_EVENT_CCHA(pb_rhu_req_occ, 0x75),
  980. CMN_EVENT_CCHA(pb_rhu_req_alloc, 0x76),
  981. CMN_EVENT_CCHA(pb_rhu_pcie_req_occ, 0x77),
  982. CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc, 0x78),
  983. CMN_EVENT_CCHA(pb_pcie_wr_req_occ, 0x79),
  984. CMN_EVENT_CCHA(pb_pcie_wr_req_alloc, 0x7a),
  985. CMN_EVENT_CCHA(pb_pcie_reg_req_occ, 0x7b),
  986. CMN_EVENT_CCHA(pb_pcie_reg_req_alloc, 0x7c),
  987. CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ, 0x7d),
  988. CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc, 0x7e),
  989. CMN_EVENT_CCHA(pb_rhu_dat_occ, 0x7f),
  990. CMN_EVENT_CCHA(pb_rhu_dat_alloc, 0x80),
  991. CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ, 0x81),
  992. CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc, 0x82),
  993. CMN_EVENT_CCHA(pb_pcie_wr_dat_occ, 0x83),
  994. CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc, 0x84),
  995. CMN_EVENT_CCLA(rx_cxs, 0x21),
  996. CMN_EVENT_CCLA(tx_cxs, 0x22),
  997. CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23),
  998. CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24),
  999. CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25),
  1000. CMN_EVENT_CCLA(link_crdbuf_occ, 0x26),
  1001. CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27),
  1002. CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28),
  1003. CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29),
  1004. CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a),
  1005. CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b),
  1006. NULL
  1007. };
  1008. static const struct attribute_group arm_cmn_event_attrs_group = {
  1009. .name = "events",
  1010. .attrs = arm_cmn_event_attrs,
  1011. .is_visible = arm_cmn_event_attr_is_visible,
  1012. };
  1013. static ssize_t arm_cmn_format_show(struct device *dev,
  1014. struct device_attribute *attr, char *buf)
  1015. {
  1016. struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
  1017. int lo = __ffs(fmt->field), hi = __fls(fmt->field);
  1018. if (lo == hi)
  1019. return sysfs_emit(buf, "config:%d\n", lo);
  1020. if (!fmt->config)
  1021. return sysfs_emit(buf, "config:%d-%d\n", lo, hi);
  1022. return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi);
  1023. }
  1024. #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \
  1025. (&((struct arm_cmn_format_attr[]) {{ \
  1026. .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
  1027. .config = _cfg, \
  1028. .field = _fld, \
  1029. }})[0].attr.attr)
  1030. #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld)
  1031. static struct attribute *arm_cmn_format_attrs[] = {
  1032. CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
  1033. CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
  1034. CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
  1035. CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
  1036. CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
  1037. CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
  1038. CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
  1039. CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
  1040. CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
  1041. CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
  1042. _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
  1043. _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
  1044. NULL
  1045. };
  1046. static const struct attribute_group arm_cmn_format_attrs_group = {
  1047. .name = "format",
  1048. .attrs = arm_cmn_format_attrs,
  1049. };
  1050. static ssize_t arm_cmn_cpumask_show(struct device *dev,
  1051. struct device_attribute *attr, char *buf)
  1052. {
  1053. struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
  1054. return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
  1055. }
  1056. static struct device_attribute arm_cmn_cpumask_attr =
  1057. __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
  1058. static struct attribute *arm_cmn_cpumask_attrs[] = {
  1059. &arm_cmn_cpumask_attr.attr,
  1060. NULL,
  1061. };
  1062. static const struct attribute_group arm_cmn_cpumask_attr_group = {
  1063. .attrs = arm_cmn_cpumask_attrs,
  1064. };
  1065. static const struct attribute_group *arm_cmn_attr_groups[] = {
  1066. &arm_cmn_event_attrs_group,
  1067. &arm_cmn_format_attrs_group,
  1068. &arm_cmn_cpumask_attr_group,
  1069. NULL
  1070. };
  1071. static int arm_cmn_wp_idx(struct perf_event *event)
  1072. {
  1073. return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event);
  1074. }
  1075. static u32 arm_cmn_wp_config(struct perf_event *event)
  1076. {
  1077. u32 config;
  1078. u32 dev = CMN_EVENT_WP_DEV_SEL(event);
  1079. u32 chn = CMN_EVENT_WP_CHN_SEL(event);
  1080. u32 grp = CMN_EVENT_WP_GRP(event);
  1081. u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
  1082. u32 combine = CMN_EVENT_WP_COMBINE(event);
  1083. bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600;
  1084. config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
  1085. FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
  1086. FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
  1087. FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
  1088. if (exc)
  1089. config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
  1090. CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
  1091. if (combine && !grp)
  1092. config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
  1093. CMN_DTM_WPn_CONFIG_WP_COMBINE;
  1094. return config;
  1095. }
  1096. static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
  1097. {
  1098. if (!cmn->state)
  1099. writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
  1100. cmn->state |= state;
  1101. }
  1102. static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
  1103. {
  1104. cmn->state &= ~state;
  1105. if (!cmn->state)
  1106. writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
  1107. cmn->dtc[0].base + CMN_DT_PMCR);
  1108. }
  1109. static void arm_cmn_pmu_enable(struct pmu *pmu)
  1110. {
  1111. arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
  1112. }
  1113. static void arm_cmn_pmu_disable(struct pmu *pmu)
  1114. {
  1115. arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
  1116. }
  1117. static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
  1118. bool snapshot)
  1119. {
  1120. struct arm_cmn_dtm *dtm = NULL;
  1121. struct arm_cmn_node *dn;
  1122. unsigned int i, offset, dtm_idx;
  1123. u64 reg, count = 0;
  1124. offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
  1125. for_each_hw_dn(hw, dn, i) {
  1126. if (dtm != &cmn->dtms[dn->dtm]) {
  1127. dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
  1128. reg = readq_relaxed(dtm->base + offset);
  1129. }
  1130. dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  1131. count += (u16)(reg >> (dtm_idx * 16));
  1132. }
  1133. return count;
  1134. }
  1135. static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
  1136. {
  1137. u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
  1138. writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
  1139. return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
  1140. }
  1141. static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
  1142. {
  1143. u32 val, pmevcnt = CMN_DT_PMEVCNT(idx);
  1144. val = readl_relaxed(dtc->base + pmevcnt);
  1145. writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
  1146. return val - CMN_COUNTER_INIT;
  1147. }
  1148. static void arm_cmn_init_counter(struct perf_event *event)
  1149. {
  1150. struct arm_cmn *cmn = to_cmn(event->pmu);
  1151. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1152. unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx);
  1153. u64 count;
  1154. for (i = 0; hw->dtcs_used & (1U << i); i++) {
  1155. writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt);
  1156. cmn->dtc[i].counters[hw->dtc_idx] = event;
  1157. }
  1158. count = arm_cmn_read_dtm(cmn, hw, false);
  1159. local64_set(&event->hw.prev_count, count);
  1160. }
  1161. static void arm_cmn_event_read(struct perf_event *event)
  1162. {
  1163. struct arm_cmn *cmn = to_cmn(event->pmu);
  1164. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1165. u64 delta, new, prev;
  1166. unsigned long flags;
  1167. unsigned int i;
  1168. if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) {
  1169. i = __ffs(hw->dtcs_used);
  1170. delta = arm_cmn_read_cc(cmn->dtc + i);
  1171. local64_add(delta, &event->count);
  1172. return;
  1173. }
  1174. new = arm_cmn_read_dtm(cmn, hw, false);
  1175. prev = local64_xchg(&event->hw.prev_count, new);
  1176. delta = new - prev;
  1177. local_irq_save(flags);
  1178. for (i = 0; hw->dtcs_used & (1U << i); i++) {
  1179. new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx);
  1180. delta += new << 16;
  1181. }
  1182. local_irq_restore(flags);
  1183. local64_add(delta, &event->count);
  1184. }
  1185. static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn,
  1186. enum cmn_filter_select fsel, u8 occupid)
  1187. {
  1188. u64 reg;
  1189. if (fsel == SEL_NONE)
  1190. return 0;
  1191. if (!dn->occupid[fsel].count) {
  1192. dn->occupid[fsel].val = occupid;
  1193. reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL,
  1194. dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) |
  1195. FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID,
  1196. dn->occupid[SEL_CLASS_OCCUP_ID].val) |
  1197. FIELD_PREP(CMN__PMU_OCCUP1_ID,
  1198. dn->occupid[SEL_OCCUP1ID].val);
  1199. writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
  1200. } else if (dn->occupid[fsel].val != occupid) {
  1201. return -EBUSY;
  1202. }
  1203. dn->occupid[fsel].count++;
  1204. return 0;
  1205. }
  1206. static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx,
  1207. int eventid, bool wide_sel)
  1208. {
  1209. if (wide_sel) {
  1210. dn->event_w[dtm_idx] = eventid;
  1211. writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);
  1212. } else {
  1213. dn->event[dtm_idx] = eventid;
  1214. writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
  1215. }
  1216. }
  1217. static void arm_cmn_event_start(struct perf_event *event, int flags)
  1218. {
  1219. struct arm_cmn *cmn = to_cmn(event->pmu);
  1220. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1221. struct arm_cmn_node *dn;
  1222. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  1223. int i;
  1224. if (type == CMN_TYPE_DTC) {
  1225. i = __ffs(hw->dtcs_used);
  1226. writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
  1227. cmn->dtc[i].cc_active = true;
  1228. } else if (type == CMN_TYPE_WP) {
  1229. int wp_idx = arm_cmn_wp_idx(event);
  1230. u64 val = CMN_EVENT_WP_VAL(event);
  1231. u64 mask = CMN_EVENT_WP_MASK(event);
  1232. for_each_hw_dn(hw, dn, i) {
  1233. void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
  1234. writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
  1235. writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
  1236. }
  1237. } else for_each_hw_dn(hw, dn, i) {
  1238. int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  1239. arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event),
  1240. hw->wide_sel);
  1241. }
  1242. }
  1243. static void arm_cmn_event_stop(struct perf_event *event, int flags)
  1244. {
  1245. struct arm_cmn *cmn = to_cmn(event->pmu);
  1246. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1247. struct arm_cmn_node *dn;
  1248. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  1249. int i;
  1250. if (type == CMN_TYPE_DTC) {
  1251. i = __ffs(hw->dtcs_used);
  1252. cmn->dtc[i].cc_active = false;
  1253. } else if (type == CMN_TYPE_WP) {
  1254. int wp_idx = arm_cmn_wp_idx(event);
  1255. for_each_hw_dn(hw, dn, i) {
  1256. void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
  1257. writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
  1258. writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
  1259. }
  1260. } else for_each_hw_dn(hw, dn, i) {
  1261. int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  1262. arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel);
  1263. }
  1264. arm_cmn_event_read(event);
  1265. }
  1266. struct arm_cmn_val {
  1267. u8 dtm_count[CMN_MAX_DTMS];
  1268. u8 occupid[CMN_MAX_DTMS][SEL_MAX];
  1269. u8 wp[CMN_MAX_DTMS][4];
  1270. int dtc_count;
  1271. bool cycles;
  1272. };
  1273. static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val,
  1274. struct perf_event *event)
  1275. {
  1276. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1277. struct arm_cmn_node *dn;
  1278. enum cmn_node_type type;
  1279. int i;
  1280. if (is_software_event(event))
  1281. return;
  1282. type = CMN_EVENT_TYPE(event);
  1283. if (type == CMN_TYPE_DTC) {
  1284. val->cycles = true;
  1285. return;
  1286. }
  1287. val->dtc_count++;
  1288. for_each_hw_dn(hw, dn, i) {
  1289. int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
  1290. val->dtm_count[dtm]++;
  1291. if (sel > SEL_NONE)
  1292. val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1;
  1293. if (type != CMN_TYPE_WP)
  1294. continue;
  1295. wp_idx = arm_cmn_wp_idx(event);
  1296. val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
  1297. }
  1298. }
  1299. static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event)
  1300. {
  1301. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1302. struct arm_cmn_node *dn;
  1303. struct perf_event *sibling, *leader = event->group_leader;
  1304. enum cmn_node_type type;
  1305. struct arm_cmn_val *val;
  1306. int i, ret = -EINVAL;
  1307. if (leader == event)
  1308. return 0;
  1309. if (event->pmu != leader->pmu && !is_software_event(leader))
  1310. return -EINVAL;
  1311. val = kzalloc(sizeof(*val), GFP_KERNEL);
  1312. if (!val)
  1313. return -ENOMEM;
  1314. arm_cmn_val_add_event(cmn, val, leader);
  1315. for_each_sibling_event(sibling, leader)
  1316. arm_cmn_val_add_event(cmn, val, sibling);
  1317. type = CMN_EVENT_TYPE(event);
  1318. if (type == CMN_TYPE_DTC) {
  1319. ret = val->cycles ? -EINVAL : 0;
  1320. goto done;
  1321. }
  1322. if (val->dtc_count == CMN_DT_NUM_COUNTERS)
  1323. goto done;
  1324. for_each_hw_dn(hw, dn, i) {
  1325. int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel;
  1326. if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)
  1327. goto done;
  1328. if (sel > SEL_NONE && val->occupid[dtm][sel] &&
  1329. val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1)
  1330. goto done;
  1331. if (type != CMN_TYPE_WP)
  1332. continue;
  1333. wp_idx = arm_cmn_wp_idx(event);
  1334. if (val->wp[dtm][wp_idx])
  1335. goto done;
  1336. wp_cmb = val->wp[dtm][wp_idx ^ 1];
  1337. if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1)
  1338. goto done;
  1339. }
  1340. ret = 0;
  1341. done:
  1342. kfree(val);
  1343. return ret;
  1344. }
  1345. static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn,
  1346. enum cmn_node_type type,
  1347. unsigned int eventid)
  1348. {
  1349. struct arm_cmn_event_attr *e;
  1350. enum cmn_model model = arm_cmn_model(cmn);
  1351. for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) {
  1352. e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr);
  1353. if (e->model & model && e->type == type && e->eventid == eventid)
  1354. return e->fsel;
  1355. }
  1356. return SEL_NONE;
  1357. }
  1358. static int arm_cmn_event_init(struct perf_event *event)
  1359. {
  1360. struct arm_cmn *cmn = to_cmn(event->pmu);
  1361. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1362. struct arm_cmn_node *dn;
  1363. enum cmn_node_type type;
  1364. bool bynodeid;
  1365. u16 nodeid, eventid;
  1366. if (event->attr.type != event->pmu->type)
  1367. return -ENOENT;
  1368. if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
  1369. return -EINVAL;
  1370. event->cpu = cmn->cpu;
  1371. if (event->cpu < 0)
  1372. return -EINVAL;
  1373. type = CMN_EVENT_TYPE(event);
  1374. /* DTC events (i.e. cycles) already have everything they need */
  1375. if (type == CMN_TYPE_DTC)
  1376. return 0;
  1377. eventid = CMN_EVENT_EVENTID(event);
  1378. /* For watchpoints we need the actual XP node here */
  1379. if (type == CMN_TYPE_WP) {
  1380. type = CMN_TYPE_XP;
  1381. /* ...and we need a "real" direction */
  1382. if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
  1383. return -EINVAL;
  1384. /* ...but the DTM may depend on which port we're watching */
  1385. if (cmn->multi_dtm)
  1386. hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2;
  1387. } else if (type == CMN_TYPE_XP && cmn->part == PART_CMN700) {
  1388. hw->wide_sel = true;
  1389. }
  1390. /* This is sufficiently annoying to recalculate, so cache it */
  1391. hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid);
  1392. bynodeid = CMN_EVENT_BYNODEID(event);
  1393. nodeid = CMN_EVENT_NODEID(event);
  1394. hw->dn = arm_cmn_node(cmn, type);
  1395. if (!hw->dn)
  1396. return -EINVAL;
  1397. for (dn = hw->dn; dn->type == type; dn++) {
  1398. if (bynodeid && dn->id != nodeid) {
  1399. hw->dn++;
  1400. continue;
  1401. }
  1402. hw->num_dns++;
  1403. if (bynodeid)
  1404. break;
  1405. }
  1406. if (!hw->num_dns) {
  1407. struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid);
  1408. dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n",
  1409. nodeid, nid.x, nid.y, nid.port, nid.dev, type);
  1410. return -EINVAL;
  1411. }
  1412. /*
  1413. * Keep assuming non-cycles events count in all DTC domains; turns out
  1414. * it's hard to make a worthwhile optimisation around this, short of
  1415. * going all-in with domain-local counter allocation as well.
  1416. */
  1417. hw->dtcs_used = (1U << cmn->num_dtcs) - 1;
  1418. return arm_cmn_validate_group(cmn, event);
  1419. }
  1420. static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
  1421. int i)
  1422. {
  1423. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1424. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  1425. while (i--) {
  1426. struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;
  1427. unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
  1428. if (type == CMN_TYPE_WP)
  1429. dtm->wp_event[arm_cmn_wp_idx(event)] = -1;
  1430. if (hw->filter_sel > SEL_NONE)
  1431. hw->dn[i].occupid[hw->filter_sel].count--;
  1432. dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
  1433. writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
  1434. }
  1435. memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
  1436. for (i = 0; hw->dtcs_used & (1U << i); i++)
  1437. cmn->dtc[i].counters[hw->dtc_idx] = NULL;
  1438. }
  1439. static int arm_cmn_event_add(struct perf_event *event, int flags)
  1440. {
  1441. struct arm_cmn *cmn = to_cmn(event->pmu);
  1442. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1443. struct arm_cmn_dtc *dtc = &cmn->dtc[0];
  1444. struct arm_cmn_node *dn;
  1445. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  1446. unsigned int i, dtc_idx, input_sel;
  1447. if (type == CMN_TYPE_DTC) {
  1448. i = 0;
  1449. while (cmn->dtc[i].cycles)
  1450. if (++i == cmn->num_dtcs)
  1451. return -ENOSPC;
  1452. cmn->dtc[i].cycles = event;
  1453. hw->dtc_idx = CMN_DT_NUM_COUNTERS;
  1454. hw->dtcs_used = 1U << i;
  1455. if (flags & PERF_EF_START)
  1456. arm_cmn_event_start(event, 0);
  1457. return 0;
  1458. }
  1459. /* Grab a free global counter first... */
  1460. dtc_idx = 0;
  1461. while (dtc->counters[dtc_idx])
  1462. if (++dtc_idx == CMN_DT_NUM_COUNTERS)
  1463. return -ENOSPC;
  1464. hw->dtc_idx = dtc_idx;
  1465. /* ...then the local counters to feed it. */
  1466. for_each_hw_dn(hw, dn, i) {
  1467. struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
  1468. unsigned int dtm_idx, shift;
  1469. u64 reg;
  1470. dtm_idx = 0;
  1471. while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
  1472. if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
  1473. goto free_dtms;
  1474. if (type == CMN_TYPE_XP) {
  1475. input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
  1476. } else if (type == CMN_TYPE_WP) {
  1477. int tmp, wp_idx = arm_cmn_wp_idx(event);
  1478. u32 cfg = arm_cmn_wp_config(event);
  1479. if (dtm->wp_event[wp_idx] >= 0)
  1480. goto free_dtms;
  1481. tmp = dtm->wp_event[wp_idx ^ 1];
  1482. if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
  1483. CMN_EVENT_WP_COMBINE(dtc->counters[tmp]))
  1484. goto free_dtms;
  1485. input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
  1486. dtm->wp_event[wp_idx] = dtc_idx;
  1487. writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
  1488. } else {
  1489. struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
  1490. if (cmn->multi_dtm)
  1491. nid.port %= 2;
  1492. input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
  1493. (nid.port << 4) + (nid.dev << 2);
  1494. if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))
  1495. goto free_dtms;
  1496. }
  1497. arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
  1498. dtm->input_sel[dtm_idx] = input_sel;
  1499. shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
  1500. dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
  1501. dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;
  1502. dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
  1503. reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;
  1504. writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
  1505. }
  1506. /* Go go go! */
  1507. arm_cmn_init_counter(event);
  1508. if (flags & PERF_EF_START)
  1509. arm_cmn_event_start(event, 0);
  1510. return 0;
  1511. free_dtms:
  1512. arm_cmn_event_clear(cmn, event, i);
  1513. return -ENOSPC;
  1514. }
  1515. static void arm_cmn_event_del(struct perf_event *event, int flags)
  1516. {
  1517. struct arm_cmn *cmn = to_cmn(event->pmu);
  1518. struct arm_cmn_hw_event *hw = to_cmn_hw(event);
  1519. enum cmn_node_type type = CMN_EVENT_TYPE(event);
  1520. arm_cmn_event_stop(event, PERF_EF_UPDATE);
  1521. if (type == CMN_TYPE_DTC)
  1522. cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL;
  1523. else
  1524. arm_cmn_event_clear(cmn, event, hw->num_dns);
  1525. }
  1526. /*
  1527. * We stop the PMU for both add and read, to avoid skew across DTM counters.
  1528. * In theory we could use snapshots to read without stopping, but then it
  1529. * becomes a lot trickier to deal with overlow and racing against interrupts,
  1530. * plus it seems they don't work properly on some hardware anyway :(
  1531. */
  1532. static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
  1533. {
  1534. arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
  1535. }
  1536. static void arm_cmn_end_txn(struct pmu *pmu)
  1537. {
  1538. arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
  1539. }
  1540. static int arm_cmn_commit_txn(struct pmu *pmu)
  1541. {
  1542. arm_cmn_end_txn(pmu);
  1543. return 0;
  1544. }
  1545. static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu)
  1546. {
  1547. unsigned int i;
  1548. perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu);
  1549. for (i = 0; i < cmn->num_dtcs; i++)
  1550. irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));
  1551. cmn->cpu = cpu;
  1552. }
  1553. static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
  1554. {
  1555. struct arm_cmn *cmn;
  1556. int node;
  1557. cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
  1558. node = dev_to_node(cmn->dev);
  1559. if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node)
  1560. arm_cmn_migrate(cmn, cpu);
  1561. return 0;
  1562. }
  1563. static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
  1564. {
  1565. struct arm_cmn *cmn;
  1566. unsigned int target;
  1567. int node;
  1568. cpumask_t mask;
  1569. cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
  1570. if (cpu != cmn->cpu)
  1571. return 0;
  1572. node = dev_to_node(cmn->dev);
  1573. if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) &&
  1574. cpumask_andnot(&mask, &mask, cpumask_of(cpu)))
  1575. target = cpumask_any(&mask);
  1576. else
  1577. target = cpumask_any_but(cpu_online_mask, cpu);
  1578. if (target < nr_cpu_ids)
  1579. arm_cmn_migrate(cmn, target);
  1580. return 0;
  1581. }
  1582. static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
  1583. {
  1584. struct arm_cmn_dtc *dtc = dev_id;
  1585. irqreturn_t ret = IRQ_NONE;
  1586. for (;;) {
  1587. u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
  1588. u64 delta;
  1589. int i;
  1590. for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) {
  1591. if (status & (1U << i)) {
  1592. ret = IRQ_HANDLED;
  1593. if (WARN_ON(!dtc->counters[i]))
  1594. continue;
  1595. delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
  1596. local64_add(delta, &dtc->counters[i]->count);
  1597. }
  1598. }
  1599. if (status & (1U << CMN_DT_NUM_COUNTERS)) {
  1600. ret = IRQ_HANDLED;
  1601. if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
  1602. delta = arm_cmn_read_cc(dtc);
  1603. local64_add(delta, &dtc->cycles->count);
  1604. }
  1605. }
  1606. writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
  1607. if (!dtc->irq_friend)
  1608. return ret;
  1609. dtc += dtc->irq_friend;
  1610. }
  1611. }
  1612. /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
  1613. static int arm_cmn_init_irqs(struct arm_cmn *cmn)
  1614. {
  1615. int i, j, irq, err;
  1616. for (i = 0; i < cmn->num_dtcs; i++) {
  1617. irq = cmn->dtc[i].irq;
  1618. for (j = i; j--; ) {
  1619. if (cmn->dtc[j].irq == irq) {
  1620. cmn->dtc[j].irq_friend = i - j;
  1621. goto next;
  1622. }
  1623. }
  1624. err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
  1625. IRQF_NOBALANCING | IRQF_NO_THREAD,
  1626. dev_name(cmn->dev), &cmn->dtc[i]);
  1627. if (err)
  1628. return err;
  1629. err = irq_set_affinity(irq, cpumask_of(cmn->cpu));
  1630. if (err)
  1631. return err;
  1632. next:
  1633. ; /* isn't C great? */
  1634. }
  1635. return 0;
  1636. }
  1637. static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)
  1638. {
  1639. int i;
  1640. dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);
  1641. dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
  1642. for (i = 0; i < 4; i++) {
  1643. dtm->wp_event[i] = -1;
  1644. writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));
  1645. writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));
  1646. }
  1647. }
  1648. static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
  1649. {
  1650. struct arm_cmn_dtc *dtc = cmn->dtc + idx;
  1651. dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
  1652. dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
  1653. if (dtc->irq < 0)
  1654. return dtc->irq;
  1655. writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
  1656. writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
  1657. writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR);
  1658. writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
  1659. return 0;
  1660. }
  1661. static int arm_cmn_node_cmp(const void *a, const void *b)
  1662. {
  1663. const struct arm_cmn_node *dna = a, *dnb = b;
  1664. int cmp;
  1665. cmp = dna->type - dnb->type;
  1666. if (!cmp)
  1667. cmp = dna->logid - dnb->logid;
  1668. return cmp;
  1669. }
  1670. static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
  1671. {
  1672. struct arm_cmn_node *dn, *xp;
  1673. int dtc_idx = 0;
  1674. u8 dtcs_present = (1 << cmn->num_dtcs) - 1;
  1675. cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
  1676. if (!cmn->dtc)
  1677. return -ENOMEM;
  1678. sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
  1679. cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
  1680. for (dn = cmn->dns; dn->type; dn++) {
  1681. if (dn->type == CMN_TYPE_XP) {
  1682. dn->dtc &= dtcs_present;
  1683. continue;
  1684. }
  1685. xp = arm_cmn_node_to_xp(cmn, dn);
  1686. dn->dtm = xp->dtm;
  1687. if (cmn->multi_dtm)
  1688. dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2;
  1689. if (dn->type == CMN_TYPE_DTC) {
  1690. int err;
  1691. /* We do at least know that a DTC's XP must be in that DTC's domain */
  1692. if (xp->dtc == 0xf)
  1693. xp->dtc = 1 << dtc_idx;
  1694. err = arm_cmn_init_dtc(cmn, dn, dtc_idx++);
  1695. if (err)
  1696. return err;
  1697. }
  1698. /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
  1699. if (dn->type == CMN_TYPE_RND)
  1700. dn->type = CMN_TYPE_RNI;
  1701. /* We split the RN-I off already, so let the CCLA part match CCLA events */
  1702. if (dn->type == CMN_TYPE_CCLA_RNI)
  1703. dn->type = CMN_TYPE_CCLA;
  1704. }
  1705. arm_cmn_set_state(cmn, CMN_STATE_DISABLED);
  1706. return 0;
  1707. }
  1708. static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region)
  1709. {
  1710. int offset = CMN_DTM_UNIT_INFO;
  1711. if (cmn->part == PART_CMN650 || cmn->part == PART_CI700)
  1712. offset = CMN650_DTM_UNIT_INFO;
  1713. return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset));
  1714. }
  1715. static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
  1716. {
  1717. int level;
  1718. u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
  1719. node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
  1720. node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
  1721. node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
  1722. node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
  1723. if (node->type == CMN_TYPE_CFG)
  1724. level = 0;
  1725. else if (node->type == CMN_TYPE_XP)
  1726. level = 1;
  1727. else
  1728. level = 2;
  1729. dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
  1730. (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
  1731. node->type, node->logid, offset);
  1732. }
  1733. static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type)
  1734. {
  1735. switch (type) {
  1736. case CMN_TYPE_HNP:
  1737. return CMN_TYPE_HNI;
  1738. case CMN_TYPE_CCLA_RNI:
  1739. return CMN_TYPE_RNI;
  1740. default:
  1741. return CMN_TYPE_INVALID;
  1742. }
  1743. }
  1744. static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
  1745. {
  1746. void __iomem *cfg_region;
  1747. struct arm_cmn_node cfg, *dn;
  1748. struct arm_cmn_dtm *dtm;
  1749. enum cmn_part part;
  1750. u16 child_count, child_poff;
  1751. u32 xp_offset[CMN_MAX_XPS];
  1752. u64 reg;
  1753. int i, j;
  1754. size_t sz;
  1755. arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
  1756. if (cfg.type != CMN_TYPE_CFG)
  1757. return -ENODEV;
  1758. cfg_region = cmn->base + rgn_offset;
  1759. reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
  1760. part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg);
  1761. part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8;
  1762. if (cmn->part && cmn->part != part)
  1763. dev_warn(cmn->dev,
  1764. "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n",
  1765. cmn->part, part);
  1766. cmn->part = part;
  1767. if (!arm_cmn_model(cmn))
  1768. dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part);
  1769. reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23);
  1770. cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
  1771. reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);
  1772. cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN;
  1773. cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg);
  1774. cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg);
  1775. reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);
  1776. cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg);
  1777. cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg);
  1778. reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
  1779. child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
  1780. child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
  1781. cmn->num_xps = child_count;
  1782. cmn->num_dns = cmn->num_xps;
  1783. /* Pass 1: visit the XPs, enumerate their children */
  1784. for (i = 0; i < cmn->num_xps; i++) {
  1785. reg = readq_relaxed(cfg_region + child_poff + i * 8);
  1786. xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
  1787. reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
  1788. cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
  1789. }
  1790. /*
  1791. * Some nodes effectively have two separate types, which we'll handle
  1792. * by creating one of each internally. For a (very) safe initial upper
  1793. * bound, account for double the number of non-XP nodes.
  1794. */
  1795. dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps,
  1796. sizeof(*dn), GFP_KERNEL);
  1797. if (!dn)
  1798. return -ENOMEM;
  1799. /* Initial safe upper bound on DTMs for any possible mesh layout */
  1800. i = cmn->num_xps;
  1801. if (cmn->multi_dtm)
  1802. i += cmn->num_xps + 1;
  1803. dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);
  1804. if (!dtm)
  1805. return -ENOMEM;
  1806. /* Pass 2: now we can actually populate the nodes */
  1807. cmn->dns = dn;
  1808. cmn->dtms = dtm;
  1809. for (i = 0; i < cmn->num_xps; i++) {
  1810. void __iomem *xp_region = cmn->base + xp_offset[i];
  1811. struct arm_cmn_node *xp = dn++;
  1812. unsigned int xp_ports = 0;
  1813. arm_cmn_init_node_info(cmn, xp_offset[i], xp);
  1814. /*
  1815. * Thanks to the order in which XP logical IDs seem to be
  1816. * assigned, we can handily infer the mesh X dimension by
  1817. * looking out for the XP at (0,1) without needing to know
  1818. * the exact node ID format, which we can later derive.
  1819. */
  1820. if (xp->id == (1 << 3))
  1821. cmn->mesh_x = xp->logid;
  1822. if (cmn->part == PART_CMN600)
  1823. xp->dtc = 0xf;
  1824. else
  1825. xp->dtc = 1 << arm_cmn_dtc_domain(cmn, xp_region);
  1826. xp->dtm = dtm - cmn->dtms;
  1827. arm_cmn_init_dtm(dtm++, xp, 0);
  1828. /*
  1829. * Keeping track of connected ports will let us filter out
  1830. * unnecessary XP events easily. We can also reliably infer the
  1831. * "extra device ports" configuration for the node ID format
  1832. * from this, since in that case we will see at least one XP
  1833. * with port 2 connected, for the HN-D.
  1834. */
  1835. for (int p = 0; p < CMN_MAX_PORTS; p++)
  1836. if (arm_cmn_device_connect_info(cmn, xp, p))
  1837. xp_ports |= BIT(p);
  1838. if (cmn->multi_dtm && (xp_ports & 0xc))
  1839. arm_cmn_init_dtm(dtm++, xp, 1);
  1840. if (cmn->multi_dtm && (xp_ports & 0x30))
  1841. arm_cmn_init_dtm(dtm++, xp, 2);
  1842. cmn->ports_used |= xp_ports;
  1843. reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
  1844. child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
  1845. child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
  1846. for (j = 0; j < child_count; j++) {
  1847. reg = readq_relaxed(xp_region + child_poff + j * 8);
  1848. /*
  1849. * Don't even try to touch anything external, since in general
  1850. * we haven't a clue how to power up arbitrary CHI requesters.
  1851. * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
  1852. * neither of which have any PMU events anyway.
  1853. * (Actually, CXLAs do seem to have grown some events in r1p2,
  1854. * but they don't go to regular XP DTMs, and they depend on
  1855. * secure configuration which we can't easily deal with)
  1856. */
  1857. if (reg & CMN_CHILD_NODE_EXTERNAL) {
  1858. dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
  1859. continue;
  1860. }
  1861. arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
  1862. switch (dn->type) {
  1863. case CMN_TYPE_DTC:
  1864. cmn->num_dtcs++;
  1865. dn++;
  1866. break;
  1867. /* These guys have PMU events */
  1868. case CMN_TYPE_DVM:
  1869. case CMN_TYPE_HNI:
  1870. case CMN_TYPE_HNF:
  1871. case CMN_TYPE_SBSX:
  1872. case CMN_TYPE_RNI:
  1873. case CMN_TYPE_RND:
  1874. case CMN_TYPE_MTSX:
  1875. case CMN_TYPE_CXRA:
  1876. case CMN_TYPE_CXHA:
  1877. case CMN_TYPE_CCRA:
  1878. case CMN_TYPE_CCHA:
  1879. case CMN_TYPE_CCLA:
  1880. dn++;
  1881. break;
  1882. /* Nothing to see here */
  1883. case CMN_TYPE_MPAM_S:
  1884. case CMN_TYPE_MPAM_NS:
  1885. case CMN_TYPE_RNSAM:
  1886. case CMN_TYPE_CXLA:
  1887. break;
  1888. /*
  1889. * Split "optimised" combination nodes into separate
  1890. * types for the different event sets. Offsetting the
  1891. * base address lets us handle the second pmu_event_sel
  1892. * register via the normal mechanism later.
  1893. */
  1894. case CMN_TYPE_HNP:
  1895. case CMN_TYPE_CCLA_RNI:
  1896. dn[1] = dn[0];
  1897. dn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL;
  1898. dn[1].type = arm_cmn_subtype(dn->type);
  1899. dn += 2;
  1900. break;
  1901. /* Something has gone horribly wrong */
  1902. default:
  1903. dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
  1904. return -ENODEV;
  1905. }
  1906. }
  1907. }
  1908. /* Correct for any nodes we added or skipped */
  1909. cmn->num_dns = dn - cmn->dns;
  1910. /* Cheeky +1 to help terminate pointer-based iteration later */
  1911. sz = (void *)(dn + 1) - (void *)cmn->dns;
  1912. dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL);
  1913. if (dn)
  1914. cmn->dns = dn;
  1915. sz = (void *)dtm - (void *)cmn->dtms;
  1916. dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);
  1917. if (dtm)
  1918. cmn->dtms = dtm;
  1919. /*
  1920. * If mesh_x wasn't set during discovery then we never saw
  1921. * an XP at (0,1), thus we must have an Nx1 configuration.
  1922. */
  1923. if (!cmn->mesh_x)
  1924. cmn->mesh_x = cmn->num_xps;
  1925. cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
  1926. /* 1x1 config plays havoc with XP event encodings */
  1927. if (cmn->num_xps == 1)
  1928. dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n");
  1929. dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev);
  1930. reg = cmn->ports_used;
  1931. dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n",
  1932. cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), &reg,
  1933. cmn->multi_dtm ? ", multi-DTM" : "");
  1934. return 0;
  1935. }
  1936. static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
  1937. {
  1938. struct resource *cfg, *root;
  1939. cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1940. if (!cfg)
  1941. return -EINVAL;
  1942. root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1943. if (!root)
  1944. return -EINVAL;
  1945. if (!resource_contains(cfg, root))
  1946. swap(cfg, root);
  1947. /*
  1948. * Note that devm_ioremap_resource() is dumb and won't let the platform
  1949. * device claim cfg when the ACPI companion device has already claimed
  1950. * root within it. But since they *are* already both claimed in the
  1951. * appropriate name, we don't really need to do it again here anyway.
  1952. */
  1953. cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
  1954. if (!cmn->base)
  1955. return -ENOMEM;
  1956. return root->start - cfg->start;
  1957. }
  1958. static int arm_cmn600_of_probe(struct device_node *np)
  1959. {
  1960. u32 rootnode;
  1961. return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode;
  1962. }
  1963. static int arm_cmn_probe(struct platform_device *pdev)
  1964. {
  1965. struct arm_cmn *cmn;
  1966. const char *name;
  1967. static atomic_t id;
  1968. int err, rootnode, this_id;
  1969. cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
  1970. if (!cmn)
  1971. return -ENOMEM;
  1972. cmn->dev = &pdev->dev;
  1973. cmn->part = (unsigned long)device_get_match_data(cmn->dev);
  1974. platform_set_drvdata(pdev, cmn);
  1975. if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) {
  1976. rootnode = arm_cmn600_acpi_probe(pdev, cmn);
  1977. } else {
  1978. rootnode = 0;
  1979. cmn->base = devm_platform_ioremap_resource(pdev, 0);
  1980. if (IS_ERR(cmn->base))
  1981. return PTR_ERR(cmn->base);
  1982. if (cmn->part == PART_CMN600)
  1983. rootnode = arm_cmn600_of_probe(pdev->dev.of_node);
  1984. }
  1985. if (rootnode < 0)
  1986. return rootnode;
  1987. err = arm_cmn_discover(cmn, rootnode);
  1988. if (err)
  1989. return err;
  1990. err = arm_cmn_init_dtcs(cmn);
  1991. if (err)
  1992. return err;
  1993. err = arm_cmn_init_irqs(cmn);
  1994. if (err)
  1995. return err;
  1996. cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev));
  1997. cmn->pmu = (struct pmu) {
  1998. .module = THIS_MODULE,
  1999. .attr_groups = arm_cmn_attr_groups,
  2000. .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
  2001. .task_ctx_nr = perf_invalid_context,
  2002. .pmu_enable = arm_cmn_pmu_enable,
  2003. .pmu_disable = arm_cmn_pmu_disable,
  2004. .event_init = arm_cmn_event_init,
  2005. .add = arm_cmn_event_add,
  2006. .del = arm_cmn_event_del,
  2007. .start = arm_cmn_event_start,
  2008. .stop = arm_cmn_event_stop,
  2009. .read = arm_cmn_event_read,
  2010. .start_txn = arm_cmn_start_txn,
  2011. .commit_txn = arm_cmn_commit_txn,
  2012. .cancel_txn = arm_cmn_end_txn,
  2013. };
  2014. this_id = atomic_fetch_inc(&id);
  2015. name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id);
  2016. if (!name)
  2017. return -ENOMEM;
  2018. err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
  2019. if (err)
  2020. return err;
  2021. err = perf_pmu_register(&cmn->pmu, name, -1);
  2022. if (err)
  2023. cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
  2024. else
  2025. arm_cmn_debugfs_init(cmn, this_id);
  2026. return err;
  2027. }
  2028. static int arm_cmn_remove(struct platform_device *pdev)
  2029. {
  2030. struct arm_cmn *cmn = platform_get_drvdata(pdev);
  2031. writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
  2032. perf_pmu_unregister(&cmn->pmu);
  2033. cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
  2034. debugfs_remove(cmn->debug);
  2035. return 0;
  2036. }
  2037. #ifdef CONFIG_OF
  2038. static const struct of_device_id arm_cmn_of_match[] = {
  2039. { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 },
  2040. { .compatible = "arm,cmn-650" },
  2041. { .compatible = "arm,cmn-700" },
  2042. { .compatible = "arm,ci-700" },
  2043. {}
  2044. };
  2045. MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
  2046. #endif
  2047. #ifdef CONFIG_ACPI
  2048. static const struct acpi_device_id arm_cmn_acpi_match[] = {
  2049. { "ARMHC600", PART_CMN600 },
  2050. { "ARMHC650" },
  2051. { "ARMHC700" },
  2052. {}
  2053. };
  2054. MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
  2055. #endif
  2056. static struct platform_driver arm_cmn_driver = {
  2057. .driver = {
  2058. .name = "arm-cmn",
  2059. .of_match_table = of_match_ptr(arm_cmn_of_match),
  2060. .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
  2061. },
  2062. .probe = arm_cmn_probe,
  2063. .remove = arm_cmn_remove,
  2064. };
  2065. static int __init arm_cmn_init(void)
  2066. {
  2067. int ret;
  2068. ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
  2069. "perf/arm/cmn:online",
  2070. arm_cmn_pmu_online_cpu,
  2071. arm_cmn_pmu_offline_cpu);
  2072. if (ret < 0)
  2073. return ret;
  2074. arm_cmn_hp_state = ret;
  2075. arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL);
  2076. ret = platform_driver_register(&arm_cmn_driver);
  2077. if (ret) {
  2078. cpuhp_remove_multi_state(arm_cmn_hp_state);
  2079. debugfs_remove(arm_cmn_debugfs);
  2080. }
  2081. return ret;
  2082. }
  2083. static void __exit arm_cmn_exit(void)
  2084. {
  2085. platform_driver_unregister(&arm_cmn_driver);
  2086. cpuhp_remove_multi_state(arm_cmn_hp_state);
  2087. debugfs_remove(arm_cmn_debugfs);
  2088. }
  2089. module_init(arm_cmn_init);
  2090. module_exit(arm_cmn_exit);
  2091. MODULE_AUTHOR("Robin Murphy <[email protected]>");
  2092. MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
  2093. MODULE_LICENSE("GPL v2");