Kconfig 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211
  1. # SPDX-License-Identifier: GPL-2.0-only
  2. #
  3. # Performance Monitor Drivers
  4. #
  5. menu "Performance monitor support"
  6. depends on PERF_EVENTS
  7. config ARM_CCI_PMU
  8. tristate "ARM CCI PMU driver"
  9. depends on (ARM && CPU_V7) || ARM64
  10. select ARM_CCI
  11. help
  12. Support for PMU events monitoring on the ARM CCI (Cache Coherent
  13. Interconnect) family of products.
  14. If compiled as a module, it will be called arm-cci.
  15. config ARM_CCI400_PMU
  16. bool "support CCI-400"
  17. default y
  18. depends on ARM_CCI_PMU
  19. select ARM_CCI400_COMMON
  20. help
  21. CCI-400 provides 4 independent event counters counting events related
  22. to the connected slave/master interfaces, plus a cycle counter.
  23. config ARM_CCI5xx_PMU
  24. bool "support CCI-500/CCI-550"
  25. default y
  26. depends on ARM_CCI_PMU
  27. help
  28. CCI-500/CCI-550 both provide 8 independent event counters, which can
  29. count events pertaining to the slave/master interfaces as well as the
  30. internal events to the CCI.
  31. config ARM_CCN
  32. tristate "ARM CCN driver support"
  33. depends on ARM || ARM64 || COMPILE_TEST
  34. help
  35. PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
  36. interconnect.
  37. config ARM_CMN
  38. tristate "Arm CMN-600 PMU support"
  39. depends on ARM64 || COMPILE_TEST
  40. help
  41. Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
  42. Network interconnect.
  43. config ARM_PMU
  44. depends on ARM || ARM64
  45. bool "ARM PMU framework"
  46. default y
  47. help
  48. Say y if you want to use CPU performance monitors on ARM-based
  49. systems.
  50. config RISCV_PMU
  51. depends on RISCV
  52. bool "RISC-V PMU framework"
  53. default y
  54. help
  55. Say y if you want to use CPU performance monitors on RISCV-based
  56. systems. This provides the core PMU framework that abstracts common
  57. PMU functionalities in a core library so that different PMU drivers
  58. can reuse it.
  59. config RISCV_PMU_LEGACY
  60. depends on RISCV_PMU
  61. bool "RISC-V legacy PMU implementation"
  62. default y
  63. help
  64. Say y if you want to use the legacy CPU performance monitor
  65. implementation on RISC-V based systems. This only allows counting
  66. of cycle/instruction counter and doesn't support counter overflow,
  67. or programmable counters. It will be removed in future.
  68. config RISCV_PMU_SBI
  69. depends on RISCV_PMU && RISCV_SBI
  70. bool "RISC-V PMU based on SBI PMU extension"
  71. default y
  72. help
  73. Say y if you want to use the CPU performance monitor
  74. using SBI PMU extension on RISC-V based systems. This option provides
  75. full perf feature support i.e. counter overflow, privilege mode
  76. filtering, counter configuration.
  77. config ARM_PMU_ACPI
  78. depends on ARM_PMU && ACPI
  79. def_bool y
  80. config ARM_SMMU_V3_PMU
  81. tristate "ARM SMMUv3 Performance Monitors Extension"
  82. depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
  83. depends on GENERIC_MSI_IRQ_DOMAIN
  84. help
  85. Provides support for the ARM SMMUv3 Performance Monitor Counter
  86. Groups (PMCG), which provide monitoring of transactions passing
  87. through the SMMU and allow the resulting information to be filtered
  88. based on the Stream ID of the corresponding master.
  89. config ARM_DSU_PMU
  90. tristate "ARM DynamIQ Shared Unit (DSU) PMU"
  91. depends on ARM64
  92. help
  93. Provides support for performance monitor unit in ARM DynamIQ Shared
  94. Unit (DSU). The DSU integrates one or more cores with an L3 memory
  95. system, control logic. The PMU allows counting various events related
  96. to DSU.
  97. config FSL_IMX8_DDR_PMU
  98. tristate "Freescale i.MX8 DDR perf monitor"
  99. depends on ARCH_MXC || COMPILE_TEST
  100. help
  101. Provides support for the DDR performance monitor in i.MX8, which
  102. can give information about memory throughput and other related
  103. events.
  104. config QCOM_L2_PMU
  105. bool "Qualcomm Technologies L2-cache PMU"
  106. depends on ARCH_QCOM && ARM64 && ACPI
  107. select QCOM_KRYO_L2_ACCESSORS
  108. help
  109. Provides support for the L2 cache performance monitor unit (PMU)
  110. in Qualcomm Technologies processors.
  111. Adds the L2 cache PMU into the perf events subsystem for
  112. monitoring L2 cache events.
  113. config QCOM_L3_PMU
  114. bool "Qualcomm Technologies L3-cache PMU"
  115. depends on ARCH_QCOM && ARM64 && ACPI
  116. select QCOM_IRQ_COMBINER
  117. help
  118. Provides support for the L3 cache performance monitor unit (PMU)
  119. in Qualcomm Technologies processors.
  120. Adds the L3 cache PMU into the perf events subsystem for
  121. monitoring L3 cache events.
  122. config QCOM_LLCC_PMU
  123. tristate "Qualcomm Technologies LLCC PMU"
  124. depends on ARCH_QCOM && ARM64
  125. help
  126. Provides support for the LLCC performance monitor unit (PMU) in
  127. Qualcomm Technologies processors.
  128. Adds the LLCC PMU into the perf events subsystem for monitoring
  129. LLCC miss events.
  130. config THUNDERX2_PMU
  131. tristate "Cavium ThunderX2 SoC PMU UNCORE"
  132. depends on ARCH_THUNDER2 || COMPILE_TEST
  133. depends on NUMA && ACPI
  134. default m
  135. help
  136. Provides support for ThunderX2 UNCORE events.
  137. The SoC has PMU support in its L3 cache controller (L3C) and
  138. in the DDR4 Memory Controller (DMC).
  139. config XGENE_PMU
  140. depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
  141. bool "APM X-Gene SoC PMU"
  142. default n
  143. help
  144. Say y if you want to use APM X-Gene SoC performance monitors.
  145. config ARM_SPE_PMU
  146. tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
  147. depends on ARM64
  148. help
  149. Enable perf support for the ARMv8.2 Statistical Profiling
  150. Extension, which provides periodic sampling of operations in
  151. the CPU pipeline and reports this via the perf AUX interface.
  152. config ARM_DMC620_PMU
  153. tristate "Enable PMU support for the ARM DMC-620 memory controller"
  154. depends on (ARM64 && ACPI) || COMPILE_TEST
  155. help
  156. Support for PMU events monitoring on the ARM DMC-620 memory
  157. controller.
  158. config MARVELL_CN10K_TAD_PMU
  159. tristate "Marvell CN10K LLC-TAD PMU"
  160. depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
  161. help
  162. Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
  163. performance monitors on CN10K family silicons.
  164. config APPLE_M1_CPU_PMU
  165. bool "Apple M1 CPU PMU support"
  166. depends on ARM_PMU && ARCH_APPLE
  167. help
  168. Provides support for the non-architectural CPU PMUs present on
  169. the Apple M1 SoCs and derivatives.
  170. config ALIBABA_UNCORE_DRW_PMU
  171. tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
  172. depends on (ARM64 && ACPI) || COMPILE_TEST
  173. help
  174. Support for Driveway PMU events monitoring on Yitian 710 DDR
  175. Sub-system.
  176. source "drivers/perf/hisilicon/Kconfig"
  177. config MARVELL_CN10K_DDR_PMU
  178. tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
  179. depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
  180. help
  181. Enable perf support for Marvell DDR Performance monitoring
  182. event on CN10K platform.
  183. endmenu