pxa2xx_base.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*======================================================================
  3. Device driver for the PCMCIA control functionality of PXA2xx
  4. microprocessors.
  5. (c) Ian Molton ([email protected]) 2003
  6. (c) Stefan Eletzhofer ([email protected]) 2003,4
  7. derived from sa11xx_base.c
  8. Portions created by John G. Dorsey are
  9. Copyright (C) 1999 John G. Dorsey.
  10. ======================================================================*/
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/init.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/ioport.h>
  16. #include <linux/kernel.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/soc/pxa/cpu.h>
  20. #include <linux/soc/pxa/smemc.h>
  21. #include <asm/io.h>
  22. #include <asm/irq.h>
  23. #include <asm/mach-types.h>
  24. #include <pcmcia/ss.h>
  25. #include <pcmcia/cistpl.h>
  26. #include "soc_common.h"
  27. #include "pxa2xx_base.h"
  28. /*
  29. * Personal Computer Memory Card International Association (PCMCIA) sockets
  30. */
  31. #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
  32. #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
  33. #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
  34. #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
  35. #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
  36. #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
  37. #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
  38. #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
  39. #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
  40. #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
  41. #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
  42. #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
  43. #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
  44. #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
  45. (0x20000000 + (Nb) * PCMCIASp)
  46. #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
  47. #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
  48. (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
  49. #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
  50. (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
  51. #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
  52. #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
  53. #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
  54. #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
  55. #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
  56. #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
  57. #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
  58. #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
  59. #define MCXX_SETUP_MASK (0x7f)
  60. #define MCXX_ASST_MASK (0x1f)
  61. #define MCXX_HOLD_MASK (0x3f)
  62. #define MCXX_SETUP_SHIFT (0)
  63. #define MCXX_ASST_SHIFT (7)
  64. #define MCXX_HOLD_SHIFT (14)
  65. static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
  66. u_int mem_clk_10khz)
  67. {
  68. u_int code = pcmcia_cycle_ns * mem_clk_10khz;
  69. return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
  70. }
  71. static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
  72. u_int mem_clk_10khz)
  73. {
  74. u_int code = pcmcia_cycle_ns * mem_clk_10khz;
  75. return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
  76. }
  77. static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
  78. u_int mem_clk_10khz)
  79. {
  80. u_int code = pcmcia_cycle_ns * mem_clk_10khz;
  81. return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
  82. }
  83. /* This function returns the (approximate) command assertion period, in
  84. * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
  85. */
  86. static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
  87. u_int pcmcia_mcxx_asst)
  88. {
  89. return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
  90. }
  91. static uint32_t pxa2xx_pcmcia_mcmem(int sock, int speed, int clock)
  92. {
  93. uint32_t val;
  94. val = ((pxa2xx_mcxx_setup(speed, clock)
  95. & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
  96. | ((pxa2xx_mcxx_asst(speed, clock)
  97. & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
  98. | ((pxa2xx_mcxx_hold(speed, clock)
  99. & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
  100. return val;
  101. }
  102. static int pxa2xx_pcmcia_mcio(int sock, int speed, int clock)
  103. {
  104. uint32_t val;
  105. val = ((pxa2xx_mcxx_setup(speed, clock)
  106. & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
  107. | ((pxa2xx_mcxx_asst(speed, clock)
  108. & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
  109. | ((pxa2xx_mcxx_hold(speed, clock)
  110. & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
  111. return val;
  112. }
  113. static int pxa2xx_pcmcia_mcatt(int sock, int speed, int clock)
  114. {
  115. uint32_t val;
  116. val = ((pxa2xx_mcxx_setup(speed, clock)
  117. & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
  118. | ((pxa2xx_mcxx_asst(speed, clock)
  119. & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
  120. | ((pxa2xx_mcxx_hold(speed, clock)
  121. & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
  122. return val;
  123. }
  124. static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
  125. {
  126. unsigned long clk = clk_get_rate(skt->clk) / 10000;
  127. struct soc_pcmcia_timing timing;
  128. int sock = skt->nr;
  129. soc_common_pcmcia_get_timing(skt, &timing);
  130. pxa_smemc_set_pcmcia_timing(sock,
  131. pxa2xx_pcmcia_mcmem(sock, timing.mem, clk),
  132. pxa2xx_pcmcia_mcatt(sock, timing.attr, clk),
  133. pxa2xx_pcmcia_mcio(sock, timing.io, clk));
  134. return 0;
  135. }
  136. #ifdef CONFIG_CPU_FREQ
  137. static int
  138. pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
  139. unsigned long val,
  140. struct cpufreq_freqs *freqs)
  141. {
  142. switch (val) {
  143. case CPUFREQ_PRECHANGE:
  144. if (freqs->new > freqs->old) {
  145. debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
  146. "pre-updating\n",
  147. freqs->new / 1000, (freqs->new / 100) % 10,
  148. freqs->old / 1000, (freqs->old / 100) % 10);
  149. pxa2xx_pcmcia_set_timing(skt);
  150. }
  151. break;
  152. case CPUFREQ_POSTCHANGE:
  153. if (freqs->new < freqs->old) {
  154. debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
  155. "post-updating\n",
  156. freqs->new / 1000, (freqs->new / 100) % 10,
  157. freqs->old / 1000, (freqs->old / 100) % 10);
  158. pxa2xx_pcmcia_set_timing(skt);
  159. }
  160. break;
  161. }
  162. return 0;
  163. }
  164. #endif
  165. void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
  166. {
  167. int nr = 1;
  168. if ((ops->first + ops->nr) > 1 ||
  169. machine_is_viper() || machine_is_arcom_zeus())
  170. nr = 2;
  171. pxa_smemc_set_pcmcia_socket(nr);
  172. }
  173. EXPORT_SYMBOL(pxa2xx_configure_sockets);
  174. static const char *skt_names[] = {
  175. "PCMCIA socket 0",
  176. "PCMCIA socket 1",
  177. };
  178. #define SKT_DEV_INFO_SIZE(n) \
  179. (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
  180. int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
  181. {
  182. skt->res_skt.start = _PCMCIA(skt->nr);
  183. skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
  184. skt->res_skt.name = skt_names[skt->nr];
  185. skt->res_skt.flags = IORESOURCE_MEM;
  186. skt->res_io.start = _PCMCIAIO(skt->nr);
  187. skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
  188. skt->res_io.name = "io";
  189. skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  190. skt->res_mem.start = _PCMCIAMem(skt->nr);
  191. skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
  192. skt->res_mem.name = "memory";
  193. skt->res_mem.flags = IORESOURCE_MEM;
  194. skt->res_attr.start = _PCMCIAAttr(skt->nr);
  195. skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
  196. skt->res_attr.name = "attribute";
  197. skt->res_attr.flags = IORESOURCE_MEM;
  198. return soc_pcmcia_add_one(skt);
  199. }
  200. EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
  201. void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
  202. {
  203. /* Provide our PXA2xx specific timing routines. */
  204. ops->set_timing = pxa2xx_pcmcia_set_timing;
  205. #ifdef CONFIG_CPU_FREQ
  206. ops->frequency_change = pxa2xx_pcmcia_frequency_change;
  207. #endif
  208. }
  209. EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
  210. static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
  211. {
  212. int i, ret = 0;
  213. struct pcmcia_low_level *ops;
  214. struct skt_dev_info *sinfo;
  215. struct soc_pcmcia_socket *skt;
  216. struct clk *clk;
  217. ops = (struct pcmcia_low_level *)dev->dev.platform_data;
  218. if (!ops) {
  219. ret = -ENODEV;
  220. goto err0;
  221. }
  222. if (cpu_is_pxa320() && ops->nr > 1) {
  223. dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
  224. ret = -EINVAL;
  225. goto err0;
  226. }
  227. clk = devm_clk_get(&dev->dev, NULL);
  228. if (IS_ERR(clk))
  229. return -ENODEV;
  230. pxa2xx_drv_pcmcia_ops(ops);
  231. sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
  232. GFP_KERNEL);
  233. if (!sinfo)
  234. return -ENOMEM;
  235. sinfo->nskt = ops->nr;
  236. /* Initialize processor specific parameters */
  237. for (i = 0; i < ops->nr; i++) {
  238. skt = &sinfo->skt[i];
  239. skt->nr = ops->first + i;
  240. skt->clk = clk;
  241. soc_pcmcia_init_one(skt, ops, &dev->dev);
  242. ret = pxa2xx_drv_pcmcia_add_one(skt);
  243. if (ret)
  244. goto err1;
  245. }
  246. pxa2xx_configure_sockets(&dev->dev, ops);
  247. dev_set_drvdata(&dev->dev, sinfo);
  248. return 0;
  249. err1:
  250. while (--i >= 0)
  251. soc_pcmcia_remove_one(&sinfo->skt[i]);
  252. err0:
  253. return ret;
  254. }
  255. static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
  256. {
  257. struct skt_dev_info *sinfo = platform_get_drvdata(dev);
  258. int i;
  259. for (i = 0; i < sinfo->nskt; i++)
  260. soc_pcmcia_remove_one(&sinfo->skt[i]);
  261. return 0;
  262. }
  263. static int pxa2xx_drv_pcmcia_resume(struct device *dev)
  264. {
  265. struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;
  266. pxa2xx_configure_sockets(dev, ops);
  267. return 0;
  268. }
  269. static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
  270. .resume = pxa2xx_drv_pcmcia_resume,
  271. };
  272. static struct platform_driver pxa2xx_pcmcia_driver = {
  273. .probe = pxa2xx_drv_pcmcia_probe,
  274. .remove = pxa2xx_drv_pcmcia_remove,
  275. .driver = {
  276. .name = "pxa2xx-pcmcia",
  277. .pm = &pxa2xx_drv_pcmcia_pm_ops,
  278. },
  279. };
  280. static int __init pxa2xx_pcmcia_init(void)
  281. {
  282. return platform_driver_register(&pxa2xx_pcmcia_driver);
  283. }
  284. static void __exit pxa2xx_pcmcia_exit(void)
  285. {
  286. platform_driver_unregister(&pxa2xx_pcmcia_driver);
  287. }
  288. fs_initcall(pxa2xx_pcmcia_init);
  289. module_exit(pxa2xx_pcmcia_exit);
  290. MODULE_AUTHOR("Stefan Eletzhofer <[email protected]> and Ian Molton <[email protected]>");
  291. MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
  292. MODULE_LICENSE("GPL");
  293. MODULE_ALIAS("platform:pxa2xx-pcmcia");