rt2500usb.c 60 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Copyright (C) 2004 - 2009 Ivo van Doorn <[email protected]>
  4. <http://rt2x00.serialmonkey.com>
  5. */
  6. /*
  7. Module: rt2500usb
  8. Abstract: rt2500usb device specific routines.
  9. Supported chipsets: RT2570.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/slab.h>
  16. #include <linux/usb.h>
  17. #include "rt2x00.h"
  18. #include "rt2x00usb.h"
  19. #include "rt2500usb.h"
  20. /*
  21. * Allow hardware encryption to be disabled.
  22. */
  23. static bool modparam_nohwcrypt;
  24. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
  25. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  26. /*
  27. * Register access.
  28. * All access to the CSR registers will go through the methods
  29. * rt2500usb_register_read and rt2500usb_register_write.
  30. * BBP and RF register require indirect register access,
  31. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  32. * These indirect registers work with busy bits,
  33. * and we will try maximal REGISTER_USB_BUSY_COUNT times to access
  34. * the register while taking a REGISTER_BUSY_DELAY us delay
  35. * between each attampt. When the busy bit is still set at that time,
  36. * the access attempt is considered to have failed,
  37. * and we will print an error.
  38. * If the csr_mutex is already held then the _lock variants must
  39. * be used instead.
  40. */
  41. static u16 rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
  42. const unsigned int offset)
  43. {
  44. __le16 reg;
  45. rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  46. USB_VENDOR_REQUEST_IN, offset,
  47. &reg, sizeof(reg));
  48. return le16_to_cpu(reg);
  49. }
  50. static u16 rt2500usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
  51. const unsigned int offset)
  52. {
  53. __le16 reg;
  54. rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
  55. USB_VENDOR_REQUEST_IN, offset,
  56. &reg, sizeof(reg), REGISTER_TIMEOUT);
  57. return le16_to_cpu(reg);
  58. }
  59. static void rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
  60. const unsigned int offset,
  61. u16 value)
  62. {
  63. __le16 reg = cpu_to_le16(value);
  64. rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  65. USB_VENDOR_REQUEST_OUT, offset,
  66. &reg, sizeof(reg));
  67. }
  68. static void rt2500usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
  69. const unsigned int offset,
  70. u16 value)
  71. {
  72. __le16 reg = cpu_to_le16(value);
  73. rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
  74. USB_VENDOR_REQUEST_OUT, offset,
  75. &reg, sizeof(reg), REGISTER_TIMEOUT);
  76. }
  77. static void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
  78. const unsigned int offset,
  79. void *value, const u16 length)
  80. {
  81. rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  82. USB_VENDOR_REQUEST_OUT, offset,
  83. value, length);
  84. }
  85. static int rt2500usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
  86. const unsigned int offset,
  87. struct rt2x00_field16 field,
  88. u16 *reg)
  89. {
  90. unsigned int i;
  91. for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) {
  92. *reg = rt2500usb_register_read_lock(rt2x00dev, offset);
  93. if (!rt2x00_get_field16(*reg, field))
  94. return 1;
  95. udelay(REGISTER_BUSY_DELAY);
  96. }
  97. rt2x00_err(rt2x00dev, "Indirect register access failed: offset=0x%.08x, value=0x%.08x\n",
  98. offset, *reg);
  99. *reg = ~0;
  100. return 0;
  101. }
  102. #define WAIT_FOR_BBP(__dev, __reg) \
  103. rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
  104. #define WAIT_FOR_RF(__dev, __reg) \
  105. rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
  106. static void rt2500usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  107. const unsigned int word, const u8 value)
  108. {
  109. u16 reg;
  110. mutex_lock(&rt2x00dev->csr_mutex);
  111. /*
  112. * Wait until the BBP becomes available, afterwards we
  113. * can safely write the new data into the register.
  114. */
  115. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  116. reg = 0;
  117. rt2x00_set_field16(&reg, PHY_CSR7_DATA, value);
  118. rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
  119. rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0);
  120. rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
  121. }
  122. mutex_unlock(&rt2x00dev->csr_mutex);
  123. }
  124. static u8 rt2500usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  125. const unsigned int word)
  126. {
  127. u16 reg;
  128. u8 value;
  129. mutex_lock(&rt2x00dev->csr_mutex);
  130. /*
  131. * Wait until the BBP becomes available, afterwards we
  132. * can safely write the read request into the register.
  133. * After the data has been written, we wait until hardware
  134. * returns the correct value, if at any time the register
  135. * doesn't become available in time, reg will be 0xffffffff
  136. * which means we return 0xff to the caller.
  137. */
  138. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  139. reg = 0;
  140. rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
  141. rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1);
  142. rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
  143. if (WAIT_FOR_BBP(rt2x00dev, &reg))
  144. reg = rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7);
  145. }
  146. value = rt2x00_get_field16(reg, PHY_CSR7_DATA);
  147. mutex_unlock(&rt2x00dev->csr_mutex);
  148. return value;
  149. }
  150. static void rt2500usb_rf_write(struct rt2x00_dev *rt2x00dev,
  151. const unsigned int word, const u32 value)
  152. {
  153. u16 reg;
  154. mutex_lock(&rt2x00dev->csr_mutex);
  155. /*
  156. * Wait until the RF becomes available, afterwards we
  157. * can safely write the new data into the register.
  158. */
  159. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  160. reg = 0;
  161. rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
  162. rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg);
  163. reg = 0;
  164. rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16);
  165. rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
  166. rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0);
  167. rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1);
  168. rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg);
  169. rt2x00_rf_write(rt2x00dev, word, value);
  170. }
  171. mutex_unlock(&rt2x00dev->csr_mutex);
  172. }
  173. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  174. static u32 _rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
  175. const unsigned int offset)
  176. {
  177. return rt2500usb_register_read(rt2x00dev, offset);
  178. }
  179. static void _rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
  180. const unsigned int offset,
  181. u32 value)
  182. {
  183. rt2500usb_register_write(rt2x00dev, offset, value);
  184. }
  185. static const struct rt2x00debug rt2500usb_rt2x00debug = {
  186. .owner = THIS_MODULE,
  187. .csr = {
  188. .read = _rt2500usb_register_read,
  189. .write = _rt2500usb_register_write,
  190. .flags = RT2X00DEBUGFS_OFFSET,
  191. .word_base = CSR_REG_BASE,
  192. .word_size = sizeof(u16),
  193. .word_count = CSR_REG_SIZE / sizeof(u16),
  194. },
  195. .eeprom = {
  196. .read = rt2x00_eeprom_read,
  197. .write = rt2x00_eeprom_write,
  198. .word_base = EEPROM_BASE,
  199. .word_size = sizeof(u16),
  200. .word_count = EEPROM_SIZE / sizeof(u16),
  201. },
  202. .bbp = {
  203. .read = rt2500usb_bbp_read,
  204. .write = rt2500usb_bbp_write,
  205. .word_base = BBP_BASE,
  206. .word_size = sizeof(u8),
  207. .word_count = BBP_SIZE / sizeof(u8),
  208. },
  209. .rf = {
  210. .read = rt2x00_rf_read,
  211. .write = rt2500usb_rf_write,
  212. .word_base = RF_BASE,
  213. .word_size = sizeof(u32),
  214. .word_count = RF_SIZE / sizeof(u32),
  215. },
  216. };
  217. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  218. static int rt2500usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  219. {
  220. u16 reg;
  221. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR19);
  222. return rt2x00_get_field16(reg, MAC_CSR19_VAL7);
  223. }
  224. #ifdef CONFIG_RT2X00_LIB_LEDS
  225. static void rt2500usb_brightness_set(struct led_classdev *led_cdev,
  226. enum led_brightness brightness)
  227. {
  228. struct rt2x00_led *led =
  229. container_of(led_cdev, struct rt2x00_led, led_dev);
  230. unsigned int enabled = brightness != LED_OFF;
  231. u16 reg;
  232. reg = rt2500usb_register_read(led->rt2x00dev, MAC_CSR20);
  233. if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
  234. rt2x00_set_field16(&reg, MAC_CSR20_LINK, enabled);
  235. else if (led->type == LED_TYPE_ACTIVITY)
  236. rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, enabled);
  237. rt2500usb_register_write(led->rt2x00dev, MAC_CSR20, reg);
  238. }
  239. static int rt2500usb_blink_set(struct led_classdev *led_cdev,
  240. unsigned long *delay_on,
  241. unsigned long *delay_off)
  242. {
  243. struct rt2x00_led *led =
  244. container_of(led_cdev, struct rt2x00_led, led_dev);
  245. u16 reg;
  246. reg = rt2500usb_register_read(led->rt2x00dev, MAC_CSR21);
  247. rt2x00_set_field16(&reg, MAC_CSR21_ON_PERIOD, *delay_on);
  248. rt2x00_set_field16(&reg, MAC_CSR21_OFF_PERIOD, *delay_off);
  249. rt2500usb_register_write(led->rt2x00dev, MAC_CSR21, reg);
  250. return 0;
  251. }
  252. static void rt2500usb_init_led(struct rt2x00_dev *rt2x00dev,
  253. struct rt2x00_led *led,
  254. enum led_type type)
  255. {
  256. led->rt2x00dev = rt2x00dev;
  257. led->type = type;
  258. led->led_dev.brightness_set = rt2500usb_brightness_set;
  259. led->led_dev.blink_set = rt2500usb_blink_set;
  260. led->flags = LED_INITIALIZED;
  261. }
  262. #endif /* CONFIG_RT2X00_LIB_LEDS */
  263. /*
  264. * Configuration handlers.
  265. */
  266. /*
  267. * rt2500usb does not differentiate between shared and pairwise
  268. * keys, so we should use the same function for both key types.
  269. */
  270. static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
  271. struct rt2x00lib_crypto *crypto,
  272. struct ieee80211_key_conf *key)
  273. {
  274. u32 mask;
  275. u16 reg;
  276. enum cipher curr_cipher;
  277. if (crypto->cmd == SET_KEY) {
  278. /*
  279. * Disallow to set WEP key other than with index 0,
  280. * it is known that not work at least on some hardware.
  281. * SW crypto will be used in that case.
  282. */
  283. if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  284. key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
  285. key->keyidx != 0)
  286. return -EOPNOTSUPP;
  287. /*
  288. * Pairwise key will always be entry 0, but this
  289. * could collide with a shared key on the same
  290. * position...
  291. */
  292. mask = TXRX_CSR0_KEY_ID.bit_mask;
  293. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR0);
  294. curr_cipher = rt2x00_get_field16(reg, TXRX_CSR0_ALGORITHM);
  295. reg &= mask;
  296. if (reg && reg == mask)
  297. return -ENOSPC;
  298. reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
  299. key->hw_key_idx += reg ? ffz(reg) : 0;
  300. /*
  301. * Hardware requires that all keys use the same cipher
  302. * (e.g. TKIP-only, AES-only, but not TKIP+AES).
  303. * If this is not the first key, compare the cipher with the
  304. * first one and fall back to SW crypto if not the same.
  305. */
  306. if (key->hw_key_idx > 0 && crypto->cipher != curr_cipher)
  307. return -EOPNOTSUPP;
  308. rt2500usb_register_multiwrite(rt2x00dev, KEY_ENTRY(key->hw_key_idx),
  309. crypto->key, sizeof(crypto->key));
  310. /*
  311. * The driver does not support the IV/EIV generation
  312. * in hardware. However it demands the data to be provided
  313. * both separately as well as inside the frame.
  314. * We already provided the CONFIG_CRYPTO_COPY_IV to rt2x00lib
  315. * to ensure rt2x00lib will not strip the data from the
  316. * frame after the copy, now we must tell mac80211
  317. * to generate the IV/EIV data.
  318. */
  319. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  320. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  321. }
  322. /*
  323. * TXRX_CSR0_KEY_ID contains only single-bit fields to indicate
  324. * a particular key is valid.
  325. */
  326. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR0);
  327. rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher);
  328. rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
  329. mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
  330. if (crypto->cmd == SET_KEY)
  331. mask |= 1 << key->hw_key_idx;
  332. else if (crypto->cmd == DISABLE_KEY)
  333. mask &= ~(1 << key->hw_key_idx);
  334. rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask);
  335. rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
  336. return 0;
  337. }
  338. static void rt2500usb_config_filter(struct rt2x00_dev *rt2x00dev,
  339. const unsigned int filter_flags)
  340. {
  341. u16 reg;
  342. /*
  343. * Start configuration steps.
  344. * Note that the version error will always be dropped
  345. * and broadcast frames will always be accepted since
  346. * there is no filter for it at this time.
  347. */
  348. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2);
  349. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CRC,
  350. !(filter_flags & FIF_FCSFAIL));
  351. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_PHYSICAL,
  352. !(filter_flags & FIF_PLCPFAIL));
  353. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CONTROL,
  354. !(filter_flags & FIF_CONTROL));
  355. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_NOT_TO_ME,
  356. !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
  357. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_TODS,
  358. !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
  359. !rt2x00dev->intf_ap_count);
  360. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_VERSION_ERROR, 1);
  361. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_MULTICAST,
  362. !(filter_flags & FIF_ALLMULTI));
  363. rt2x00_set_field16(&reg, TXRX_CSR2_DROP_BROADCAST, 0);
  364. rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
  365. }
  366. static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev,
  367. struct rt2x00_intf *intf,
  368. struct rt2x00intf_conf *conf,
  369. const unsigned int flags)
  370. {
  371. unsigned int bcn_preload;
  372. u16 reg;
  373. if (flags & CONFIG_UPDATE_TYPE) {
  374. /*
  375. * Enable beacon config
  376. */
  377. bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
  378. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR20);
  379. rt2x00_set_field16(&reg, TXRX_CSR20_OFFSET, bcn_preload >> 6);
  380. rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW,
  381. 2 * (conf->type != NL80211_IFTYPE_STATION));
  382. rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg);
  383. /*
  384. * Enable synchronisation.
  385. */
  386. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR18);
  387. rt2x00_set_field16(&reg, TXRX_CSR18_OFFSET, 0);
  388. rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
  389. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19);
  390. rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync);
  391. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  392. }
  393. if (flags & CONFIG_UPDATE_MAC)
  394. rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR2, conf->mac,
  395. (3 * sizeof(__le16)));
  396. if (flags & CONFIG_UPDATE_BSSID)
  397. rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR5, conf->bssid,
  398. (3 * sizeof(__le16)));
  399. }
  400. static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev,
  401. struct rt2x00lib_erp *erp,
  402. u32 changed)
  403. {
  404. u16 reg;
  405. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  406. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR10);
  407. rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,
  408. !!erp->short_preamble);
  409. rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);
  410. }
  411. if (changed & BSS_CHANGED_BASIC_RATES)
  412. rt2500usb_register_write(rt2x00dev, TXRX_CSR11,
  413. erp->basic_rates);
  414. if (changed & BSS_CHANGED_BEACON_INT) {
  415. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR18);
  416. rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL,
  417. erp->beacon_int * 4);
  418. rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
  419. }
  420. if (changed & BSS_CHANGED_ERP_SLOT) {
  421. rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time);
  422. rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs);
  423. rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs);
  424. }
  425. }
  426. static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,
  427. struct antenna_setup *ant)
  428. {
  429. u8 r2;
  430. u8 r14;
  431. u16 csr5;
  432. u16 csr6;
  433. /*
  434. * We should never come here because rt2x00lib is supposed
  435. * to catch this and send us the correct antenna explicitely.
  436. */
  437. BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
  438. ant->tx == ANTENNA_SW_DIVERSITY);
  439. r2 = rt2500usb_bbp_read(rt2x00dev, 2);
  440. r14 = rt2500usb_bbp_read(rt2x00dev, 14);
  441. csr5 = rt2500usb_register_read(rt2x00dev, PHY_CSR5);
  442. csr6 = rt2500usb_register_read(rt2x00dev, PHY_CSR6);
  443. /*
  444. * Configure the TX antenna.
  445. */
  446. switch (ant->tx) {
  447. case ANTENNA_HW_DIVERSITY:
  448. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 1);
  449. rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 1);
  450. rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 1);
  451. break;
  452. case ANTENNA_A:
  453. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
  454. rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 0);
  455. rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 0);
  456. break;
  457. case ANTENNA_B:
  458. default:
  459. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
  460. rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 2);
  461. rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 2);
  462. break;
  463. }
  464. /*
  465. * Configure the RX antenna.
  466. */
  467. switch (ant->rx) {
  468. case ANTENNA_HW_DIVERSITY:
  469. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 1);
  470. break;
  471. case ANTENNA_A:
  472. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
  473. break;
  474. case ANTENNA_B:
  475. default:
  476. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
  477. break;
  478. }
  479. /*
  480. * RT2525E and RT5222 need to flip TX I/Q
  481. */
  482. if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
  483. rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
  484. rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
  485. rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
  486. /*
  487. * RT2525E does not need RX I/Q Flip.
  488. */
  489. if (rt2x00_rf(rt2x00dev, RF2525E))
  490. rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
  491. } else {
  492. rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
  493. rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 0);
  494. }
  495. rt2500usb_bbp_write(rt2x00dev, 2, r2);
  496. rt2500usb_bbp_write(rt2x00dev, 14, r14);
  497. rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5);
  498. rt2500usb_register_write(rt2x00dev, PHY_CSR6, csr6);
  499. }
  500. static void rt2500usb_config_channel(struct rt2x00_dev *rt2x00dev,
  501. struct rf_channel *rf, const int txpower)
  502. {
  503. /*
  504. * Set TXpower.
  505. */
  506. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  507. /*
  508. * For RT2525E we should first set the channel to half band higher.
  509. */
  510. if (rt2x00_rf(rt2x00dev, RF2525E)) {
  511. static const u32 vals[] = {
  512. 0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2,
  513. 0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba,
  514. 0x000008ba, 0x000008be, 0x000008b7, 0x00000902,
  515. 0x00000902, 0x00000906
  516. };
  517. rt2500usb_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
  518. if (rf->rf4)
  519. rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
  520. }
  521. rt2500usb_rf_write(rt2x00dev, 1, rf->rf1);
  522. rt2500usb_rf_write(rt2x00dev, 2, rf->rf2);
  523. rt2500usb_rf_write(rt2x00dev, 3, rf->rf3);
  524. if (rf->rf4)
  525. rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
  526. }
  527. static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev,
  528. const int txpower)
  529. {
  530. u32 rf3;
  531. rf3 = rt2x00_rf_read(rt2x00dev, 3);
  532. rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  533. rt2500usb_rf_write(rt2x00dev, 3, rf3);
  534. }
  535. static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
  536. struct rt2x00lib_conf *libconf)
  537. {
  538. enum dev_state state =
  539. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  540. STATE_SLEEP : STATE_AWAKE;
  541. u16 reg;
  542. if (state == STATE_SLEEP) {
  543. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR18);
  544. rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON,
  545. rt2x00dev->beacon_int - 20);
  546. rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP,
  547. libconf->conf->listen_interval - 1);
  548. /* We must first disable autowake before it can be enabled */
  549. rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
  550. rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
  551. rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1);
  552. rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
  553. } else {
  554. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR18);
  555. rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
  556. rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
  557. }
  558. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  559. }
  560. static void rt2500usb_config(struct rt2x00_dev *rt2x00dev,
  561. struct rt2x00lib_conf *libconf,
  562. const unsigned int flags)
  563. {
  564. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  565. rt2500usb_config_channel(rt2x00dev, &libconf->rf,
  566. libconf->conf->power_level);
  567. if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
  568. !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
  569. rt2500usb_config_txpower(rt2x00dev,
  570. libconf->conf->power_level);
  571. if (flags & IEEE80211_CONF_CHANGE_PS)
  572. rt2500usb_config_ps(rt2x00dev, libconf);
  573. }
  574. /*
  575. * Link tuning
  576. */
  577. static void rt2500usb_link_stats(struct rt2x00_dev *rt2x00dev,
  578. struct link_qual *qual)
  579. {
  580. u16 reg;
  581. /*
  582. * Update FCS error count from register.
  583. */
  584. reg = rt2500usb_register_read(rt2x00dev, STA_CSR0);
  585. qual->rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR);
  586. /*
  587. * Update False CCA count from register.
  588. */
  589. reg = rt2500usb_register_read(rt2x00dev, STA_CSR3);
  590. qual->false_cca = rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR);
  591. }
  592. static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
  593. struct link_qual *qual)
  594. {
  595. u16 eeprom;
  596. u16 value;
  597. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24);
  598. value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R24_LOW);
  599. rt2500usb_bbp_write(rt2x00dev, 24, value);
  600. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25);
  601. value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R25_LOW);
  602. rt2500usb_bbp_write(rt2x00dev, 25, value);
  603. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61);
  604. value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R61_LOW);
  605. rt2500usb_bbp_write(rt2x00dev, 61, value);
  606. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC);
  607. value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_VGCUPPER);
  608. rt2500usb_bbp_write(rt2x00dev, 17, value);
  609. qual->vgc_level = value;
  610. }
  611. /*
  612. * Queue handlers.
  613. */
  614. static void rt2500usb_start_queue(struct data_queue *queue)
  615. {
  616. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  617. u16 reg;
  618. switch (queue->qid) {
  619. case QID_RX:
  620. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2);
  621. rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 0);
  622. rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
  623. break;
  624. case QID_BEACON:
  625. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19);
  626. rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
  627. rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
  628. rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
  629. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  630. break;
  631. default:
  632. break;
  633. }
  634. }
  635. static void rt2500usb_stop_queue(struct data_queue *queue)
  636. {
  637. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  638. u16 reg;
  639. switch (queue->qid) {
  640. case QID_RX:
  641. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2);
  642. rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
  643. rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
  644. break;
  645. case QID_BEACON:
  646. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19);
  647. rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
  648. rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
  649. rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
  650. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  651. break;
  652. default:
  653. break;
  654. }
  655. }
  656. /*
  657. * Initialization functions.
  658. */
  659. static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
  660. {
  661. u16 reg;
  662. rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0x0001,
  663. USB_MODE_TEST, REGISTER_TIMEOUT);
  664. rt2x00usb_vendor_request_sw(rt2x00dev, USB_SINGLE_WRITE, 0x0308,
  665. 0x00f0, REGISTER_TIMEOUT);
  666. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2);
  667. rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
  668. rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
  669. rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x1111);
  670. rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x1e11);
  671. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR1);
  672. rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 1);
  673. rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 1);
  674. rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
  675. rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
  676. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR1);
  677. rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
  678. rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
  679. rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
  680. rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
  681. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR5);
  682. rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0, 13);
  683. rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0_VALID, 1);
  684. rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1, 12);
  685. rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1_VALID, 1);
  686. rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg);
  687. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR6);
  688. rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0, 10);
  689. rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0_VALID, 1);
  690. rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1, 11);
  691. rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1_VALID, 1);
  692. rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg);
  693. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR7);
  694. rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0, 7);
  695. rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0_VALID, 1);
  696. rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1, 6);
  697. rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1_VALID, 1);
  698. rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg);
  699. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR8);
  700. rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0, 5);
  701. rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0_VALID, 1);
  702. rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1, 0);
  703. rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1_VALID, 0);
  704. rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg);
  705. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19);
  706. rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
  707. rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, 0);
  708. rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
  709. rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
  710. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  711. rt2500usb_register_write(rt2x00dev, TXRX_CSR21, 0xe78f);
  712. rt2500usb_register_write(rt2x00dev, MAC_CSR9, 0xff1d);
  713. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  714. return -EBUSY;
  715. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR1);
  716. rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
  717. rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
  718. rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1);
  719. rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
  720. if (rt2x00_rev(rt2x00dev) >= RT2570_VERSION_C) {
  721. reg = rt2500usb_register_read(rt2x00dev, PHY_CSR2);
  722. rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0);
  723. } else {
  724. reg = 0;
  725. rt2x00_set_field16(&reg, PHY_CSR2_LNA, 1);
  726. rt2x00_set_field16(&reg, PHY_CSR2_LNA_MODE, 3);
  727. }
  728. rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg);
  729. rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0002);
  730. rt2500usb_register_write(rt2x00dev, MAC_CSR22, 0x0053);
  731. rt2500usb_register_write(rt2x00dev, MAC_CSR15, 0x01ee);
  732. rt2500usb_register_write(rt2x00dev, MAC_CSR16, 0x0000);
  733. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR8);
  734. rt2x00_set_field16(&reg, MAC_CSR8_MAX_FRAME_UNIT,
  735. rt2x00dev->rx->data_size);
  736. rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg);
  737. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR0);
  738. rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, CIPHER_NONE);
  739. rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
  740. rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0);
  741. rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
  742. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR18);
  743. rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 90);
  744. rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
  745. reg = rt2500usb_register_read(rt2x00dev, PHY_CSR4);
  746. rt2x00_set_field16(&reg, PHY_CSR4_LOW_RF_LE, 1);
  747. rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg);
  748. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR1);
  749. rt2x00_set_field16(&reg, TXRX_CSR1_AUTO_SEQUENCE, 1);
  750. rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
  751. return 0;
  752. }
  753. static int rt2500usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  754. {
  755. unsigned int i;
  756. u8 value;
  757. for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) {
  758. value = rt2500usb_bbp_read(rt2x00dev, 0);
  759. if ((value != 0xff) && (value != 0x00))
  760. return 0;
  761. udelay(REGISTER_BUSY_DELAY);
  762. }
  763. rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
  764. return -EACCES;
  765. }
  766. static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
  767. {
  768. unsigned int i;
  769. u16 eeprom;
  770. u8 value;
  771. u8 reg_id;
  772. if (unlikely(rt2500usb_wait_bbp_ready(rt2x00dev)))
  773. return -EACCES;
  774. rt2500usb_bbp_write(rt2x00dev, 3, 0x02);
  775. rt2500usb_bbp_write(rt2x00dev, 4, 0x19);
  776. rt2500usb_bbp_write(rt2x00dev, 14, 0x1c);
  777. rt2500usb_bbp_write(rt2x00dev, 15, 0x30);
  778. rt2500usb_bbp_write(rt2x00dev, 16, 0xac);
  779. rt2500usb_bbp_write(rt2x00dev, 18, 0x18);
  780. rt2500usb_bbp_write(rt2x00dev, 19, 0xff);
  781. rt2500usb_bbp_write(rt2x00dev, 20, 0x1e);
  782. rt2500usb_bbp_write(rt2x00dev, 21, 0x08);
  783. rt2500usb_bbp_write(rt2x00dev, 22, 0x08);
  784. rt2500usb_bbp_write(rt2x00dev, 23, 0x08);
  785. rt2500usb_bbp_write(rt2x00dev, 24, 0x80);
  786. rt2500usb_bbp_write(rt2x00dev, 25, 0x50);
  787. rt2500usb_bbp_write(rt2x00dev, 26, 0x08);
  788. rt2500usb_bbp_write(rt2x00dev, 27, 0x23);
  789. rt2500usb_bbp_write(rt2x00dev, 30, 0x10);
  790. rt2500usb_bbp_write(rt2x00dev, 31, 0x2b);
  791. rt2500usb_bbp_write(rt2x00dev, 32, 0xb9);
  792. rt2500usb_bbp_write(rt2x00dev, 34, 0x12);
  793. rt2500usb_bbp_write(rt2x00dev, 35, 0x50);
  794. rt2500usb_bbp_write(rt2x00dev, 39, 0xc4);
  795. rt2500usb_bbp_write(rt2x00dev, 40, 0x02);
  796. rt2500usb_bbp_write(rt2x00dev, 41, 0x60);
  797. rt2500usb_bbp_write(rt2x00dev, 53, 0x10);
  798. rt2500usb_bbp_write(rt2x00dev, 54, 0x18);
  799. rt2500usb_bbp_write(rt2x00dev, 56, 0x08);
  800. rt2500usb_bbp_write(rt2x00dev, 57, 0x10);
  801. rt2500usb_bbp_write(rt2x00dev, 58, 0x08);
  802. rt2500usb_bbp_write(rt2x00dev, 61, 0x60);
  803. rt2500usb_bbp_write(rt2x00dev, 62, 0x10);
  804. rt2500usb_bbp_write(rt2x00dev, 75, 0xff);
  805. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  806. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
  807. if (eeprom != 0xffff && eeprom != 0x0000) {
  808. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  809. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  810. rt2500usb_bbp_write(rt2x00dev, reg_id, value);
  811. }
  812. }
  813. return 0;
  814. }
  815. /*
  816. * Device state switch handlers.
  817. */
  818. static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
  819. {
  820. /*
  821. * Initialize all registers.
  822. */
  823. if (unlikely(rt2500usb_init_registers(rt2x00dev) ||
  824. rt2500usb_init_bbp(rt2x00dev)))
  825. return -EIO;
  826. return 0;
  827. }
  828. static void rt2500usb_disable_radio(struct rt2x00_dev *rt2x00dev)
  829. {
  830. rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x2121);
  831. rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x2121);
  832. /*
  833. * Disable synchronisation.
  834. */
  835. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
  836. rt2x00usb_disable_radio(rt2x00dev);
  837. }
  838. static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev,
  839. enum dev_state state)
  840. {
  841. u16 reg;
  842. u16 reg2;
  843. unsigned int i;
  844. bool put_to_sleep;
  845. u8 bbp_state;
  846. u8 rf_state;
  847. put_to_sleep = (state != STATE_AWAKE);
  848. reg = 0;
  849. rt2x00_set_field16(&reg, MAC_CSR17_BBP_DESIRE_STATE, state);
  850. rt2x00_set_field16(&reg, MAC_CSR17_RF_DESIRE_STATE, state);
  851. rt2x00_set_field16(&reg, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep);
  852. rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
  853. rt2x00_set_field16(&reg, MAC_CSR17_SET_STATE, 1);
  854. rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
  855. /*
  856. * Device is not guaranteed to be in the requested state yet.
  857. * We must wait until the register indicates that the
  858. * device has entered the correct state.
  859. */
  860. for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) {
  861. reg2 = rt2500usb_register_read(rt2x00dev, MAC_CSR17);
  862. bbp_state = rt2x00_get_field16(reg2, MAC_CSR17_BBP_CURR_STATE);
  863. rf_state = rt2x00_get_field16(reg2, MAC_CSR17_RF_CURR_STATE);
  864. if (bbp_state == state && rf_state == state)
  865. return 0;
  866. rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
  867. msleep(30);
  868. }
  869. return -EBUSY;
  870. }
  871. static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
  872. enum dev_state state)
  873. {
  874. int retval = 0;
  875. switch (state) {
  876. case STATE_RADIO_ON:
  877. retval = rt2500usb_enable_radio(rt2x00dev);
  878. break;
  879. case STATE_RADIO_OFF:
  880. rt2500usb_disable_radio(rt2x00dev);
  881. break;
  882. case STATE_RADIO_IRQ_ON:
  883. case STATE_RADIO_IRQ_OFF:
  884. /* No support, but no error either */
  885. break;
  886. case STATE_DEEP_SLEEP:
  887. case STATE_SLEEP:
  888. case STATE_STANDBY:
  889. case STATE_AWAKE:
  890. retval = rt2500usb_set_state(rt2x00dev, state);
  891. break;
  892. default:
  893. retval = -ENOTSUPP;
  894. break;
  895. }
  896. if (unlikely(retval))
  897. rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
  898. state, retval);
  899. return retval;
  900. }
  901. /*
  902. * TX descriptor initialization
  903. */
  904. static void rt2500usb_write_tx_desc(struct queue_entry *entry,
  905. struct txentry_desc *txdesc)
  906. {
  907. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  908. __le32 *txd = (__le32 *) entry->skb->data;
  909. u32 word;
  910. /*
  911. * Start writing the descriptor words.
  912. */
  913. word = rt2x00_desc_read(txd, 0);
  914. rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
  915. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  916. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  917. rt2x00_set_field32(&word, TXD_W0_ACK,
  918. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  919. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  920. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  921. rt2x00_set_field32(&word, TXD_W0_OFDM,
  922. (txdesc->rate_mode == RATE_MODE_OFDM));
  923. rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
  924. test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
  925. rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
  926. rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
  927. rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
  928. rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
  929. rt2x00_desc_write(txd, 0, word);
  930. word = rt2x00_desc_read(txd, 1);
  931. rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
  932. rt2x00_set_field32(&word, TXD_W1_AIFS, entry->queue->aifs);
  933. rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
  934. rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
  935. rt2x00_desc_write(txd, 1, word);
  936. word = rt2x00_desc_read(txd, 2);
  937. rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
  938. rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
  939. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
  940. txdesc->u.plcp.length_low);
  941. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
  942. txdesc->u.plcp.length_high);
  943. rt2x00_desc_write(txd, 2, word);
  944. if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
  945. _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
  946. _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
  947. }
  948. /*
  949. * Register descriptor details in skb frame descriptor.
  950. */
  951. skbdesc->flags |= SKBDESC_DESC_IN_SKB;
  952. skbdesc->desc = txd;
  953. skbdesc->desc_len = TXD_DESC_SIZE;
  954. }
  955. /*
  956. * TX data initialization
  957. */
  958. static void rt2500usb_beacondone(struct urb *urb);
  959. static void rt2500usb_write_beacon(struct queue_entry *entry,
  960. struct txentry_desc *txdesc)
  961. {
  962. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  963. struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
  964. struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
  965. int pipe = usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint);
  966. int length;
  967. u16 reg, reg0;
  968. /*
  969. * Disable beaconing while we are reloading the beacon data,
  970. * otherwise we might be sending out invalid data.
  971. */
  972. reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19);
  973. rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
  974. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  975. /*
  976. * Add space for the descriptor in front of the skb.
  977. */
  978. skb_push(entry->skb, TXD_DESC_SIZE);
  979. memset(entry->skb->data, 0, TXD_DESC_SIZE);
  980. /*
  981. * Write the TX descriptor for the beacon.
  982. */
  983. rt2500usb_write_tx_desc(entry, txdesc);
  984. /*
  985. * Dump beacon to userspace through debugfs.
  986. */
  987. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
  988. /*
  989. * USB devices cannot blindly pass the skb->len as the
  990. * length of the data to usb_fill_bulk_urb. Pass the skb
  991. * to the driver to determine what the length should be.
  992. */
  993. length = rt2x00dev->ops->lib->get_tx_data_len(entry);
  994. usb_fill_bulk_urb(bcn_priv->urb, usb_dev, pipe,
  995. entry->skb->data, length, rt2500usb_beacondone,
  996. entry);
  997. /*
  998. * Second we need to create the guardian byte.
  999. * We only need a single byte, so lets recycle
  1000. * the 'flags' field we are not using for beacons.
  1001. */
  1002. bcn_priv->guardian_data = 0;
  1003. usb_fill_bulk_urb(bcn_priv->guardian_urb, usb_dev, pipe,
  1004. &bcn_priv->guardian_data, 1, rt2500usb_beacondone,
  1005. entry);
  1006. /*
  1007. * Send out the guardian byte.
  1008. */
  1009. usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC);
  1010. /*
  1011. * Enable beaconing again.
  1012. */
  1013. rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
  1014. rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
  1015. reg0 = reg;
  1016. rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
  1017. /*
  1018. * Beacon generation will fail initially.
  1019. * To prevent this we need to change the TXRX_CSR19
  1020. * register several times (reg0 is the same as reg
  1021. * except for TXRX_CSR19_BEACON_GEN, which is 0 in reg0
  1022. * and 1 in reg).
  1023. */
  1024. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  1025. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
  1026. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  1027. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
  1028. rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
  1029. }
  1030. static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
  1031. {
  1032. int length;
  1033. /*
  1034. * The length _must_ be a multiple of 2,
  1035. * but it must _not_ be a multiple of the USB packet size.
  1036. */
  1037. length = roundup(entry->skb->len, 2);
  1038. length += (2 * !(length % entry->queue->usb_maxpacket));
  1039. return length;
  1040. }
  1041. /*
  1042. * RX control handlers
  1043. */
  1044. static void rt2500usb_fill_rxdone(struct queue_entry *entry,
  1045. struct rxdone_entry_desc *rxdesc)
  1046. {
  1047. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1048. struct queue_entry_priv_usb *entry_priv = entry->priv_data;
  1049. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  1050. __le32 *rxd =
  1051. (__le32 *)(entry->skb->data +
  1052. (entry_priv->urb->actual_length -
  1053. entry->queue->desc_size));
  1054. u32 word0;
  1055. u32 word1;
  1056. /*
  1057. * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
  1058. * frame data in rt2x00usb.
  1059. */
  1060. memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
  1061. rxd = (__le32 *)skbdesc->desc;
  1062. /*
  1063. * It is now safe to read the descriptor on all architectures.
  1064. */
  1065. word0 = rt2x00_desc_read(rxd, 0);
  1066. word1 = rt2x00_desc_read(rxd, 1);
  1067. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1068. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1069. if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
  1070. rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
  1071. rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER);
  1072. if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
  1073. rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
  1074. if (rxdesc->cipher != CIPHER_NONE) {
  1075. rxdesc->iv[0] = _rt2x00_desc_read(rxd, 2);
  1076. rxdesc->iv[1] = _rt2x00_desc_read(rxd, 3);
  1077. rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
  1078. /* ICV is located at the end of frame */
  1079. rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
  1080. if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
  1081. rxdesc->flags |= RX_FLAG_DECRYPTED;
  1082. else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
  1083. rxdesc->flags |= RX_FLAG_MMIC_ERROR;
  1084. }
  1085. /*
  1086. * Obtain the status about this packet.
  1087. * When frame was received with an OFDM bitrate,
  1088. * the signal is the PLCP value. If it was received with
  1089. * a CCK bitrate the signal is the rate in 100kbit/s.
  1090. */
  1091. rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
  1092. rxdesc->rssi =
  1093. rt2x00_get_field32(word1, RXD_W1_RSSI) - rt2x00dev->rssi_offset;
  1094. rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1095. if (rt2x00_get_field32(word0, RXD_W0_OFDM))
  1096. rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
  1097. else
  1098. rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
  1099. if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
  1100. rxdesc->dev_flags |= RXDONE_MY_BSS;
  1101. /*
  1102. * Adjust the skb memory window to the frame boundaries.
  1103. */
  1104. skb_trim(entry->skb, rxdesc->size);
  1105. }
  1106. /*
  1107. * Interrupt functions.
  1108. */
  1109. static void rt2500usb_beacondone(struct urb *urb)
  1110. {
  1111. struct queue_entry *entry = (struct queue_entry *)urb->context;
  1112. struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
  1113. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &entry->queue->rt2x00dev->flags))
  1114. return;
  1115. /*
  1116. * Check if this was the guardian beacon,
  1117. * if that was the case we need to send the real beacon now.
  1118. * Otherwise we should free the sk_buffer, the device
  1119. * should be doing the rest of the work now.
  1120. */
  1121. if (bcn_priv->guardian_urb == urb) {
  1122. usb_submit_urb(bcn_priv->urb, GFP_ATOMIC);
  1123. } else if (bcn_priv->urb == urb) {
  1124. dev_kfree_skb(entry->skb);
  1125. entry->skb = NULL;
  1126. }
  1127. }
  1128. /*
  1129. * Device probe functions.
  1130. */
  1131. static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1132. {
  1133. u16 word;
  1134. u8 *mac;
  1135. u8 bbp;
  1136. rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
  1137. /*
  1138. * Start validation of the data that has been read.
  1139. */
  1140. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1141. rt2x00lib_set_mac_address(rt2x00dev, mac);
  1142. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
  1143. if (word == 0xffff) {
  1144. rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
  1145. rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
  1146. ANTENNA_SW_DIVERSITY);
  1147. rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
  1148. ANTENNA_SW_DIVERSITY);
  1149. rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
  1150. LED_MODE_DEFAULT);
  1151. rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
  1152. rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
  1153. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
  1154. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1155. rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
  1156. }
  1157. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
  1158. if (word == 0xffff) {
  1159. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1160. rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
  1161. rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
  1162. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1163. rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
  1164. }
  1165. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET);
  1166. if (word == 0xffff) {
  1167. rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
  1168. DEFAULT_RSSI_OFFSET);
  1169. rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
  1170. rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n",
  1171. word);
  1172. }
  1173. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE);
  1174. if (word == 0xffff) {
  1175. rt2x00_set_field16(&word, EEPROM_BBPTUNE_THRESHOLD, 45);
  1176. rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE, word);
  1177. rt2x00_eeprom_dbg(rt2x00dev, "BBPtune: 0x%04x\n", word);
  1178. }
  1179. /*
  1180. * Switch lower vgc bound to current BBP R17 value,
  1181. * lower the value a bit for better quality.
  1182. */
  1183. bbp = rt2500usb_bbp_read(rt2x00dev, 17);
  1184. bbp -= 6;
  1185. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC);
  1186. if (word == 0xffff) {
  1187. rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCUPPER, 0x40);
  1188. rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
  1189. rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
  1190. rt2x00_eeprom_dbg(rt2x00dev, "BBPtune vgc: 0x%04x\n", word);
  1191. } else {
  1192. rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
  1193. rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
  1194. }
  1195. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17);
  1196. if (word == 0xffff) {
  1197. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_LOW, 0x48);
  1198. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41);
  1199. rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word);
  1200. rt2x00_eeprom_dbg(rt2x00dev, "BBPtune r17: 0x%04x\n", word);
  1201. }
  1202. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24);
  1203. if (word == 0xffff) {
  1204. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_LOW, 0x40);
  1205. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_HIGH, 0x80);
  1206. rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R24, word);
  1207. rt2x00_eeprom_dbg(rt2x00dev, "BBPtune r24: 0x%04x\n", word);
  1208. }
  1209. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25);
  1210. if (word == 0xffff) {
  1211. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_LOW, 0x40);
  1212. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_HIGH, 0x50);
  1213. rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R25, word);
  1214. rt2x00_eeprom_dbg(rt2x00dev, "BBPtune r25: 0x%04x\n", word);
  1215. }
  1216. word = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61);
  1217. if (word == 0xffff) {
  1218. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_LOW, 0x60);
  1219. rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_HIGH, 0x6d);
  1220. rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R61, word);
  1221. rt2x00_eeprom_dbg(rt2x00dev, "BBPtune r61: 0x%04x\n", word);
  1222. }
  1223. return 0;
  1224. }
  1225. static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1226. {
  1227. u16 reg;
  1228. u16 value;
  1229. u16 eeprom;
  1230. /*
  1231. * Read EEPROM word for configuration.
  1232. */
  1233. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
  1234. /*
  1235. * Identify RF chipset.
  1236. */
  1237. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1238. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR0);
  1239. rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
  1240. if (((reg & 0xfff0) != 0) || ((reg & 0x0000000f) == 0)) {
  1241. rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n");
  1242. return -ENODEV;
  1243. }
  1244. if (!rt2x00_rf(rt2x00dev, RF2522) &&
  1245. !rt2x00_rf(rt2x00dev, RF2523) &&
  1246. !rt2x00_rf(rt2x00dev, RF2524) &&
  1247. !rt2x00_rf(rt2x00dev, RF2525) &&
  1248. !rt2x00_rf(rt2x00dev, RF2525E) &&
  1249. !rt2x00_rf(rt2x00dev, RF5222)) {
  1250. rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
  1251. return -ENODEV;
  1252. }
  1253. /*
  1254. * Identify default antenna configuration.
  1255. */
  1256. rt2x00dev->default_ant.tx =
  1257. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1258. rt2x00dev->default_ant.rx =
  1259. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1260. /*
  1261. * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
  1262. * I am not 100% sure about this, but the legacy drivers do not
  1263. * indicate antenna swapping in software is required when
  1264. * diversity is enabled.
  1265. */
  1266. if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
  1267. rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
  1268. if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
  1269. rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
  1270. /*
  1271. * Store led mode, for correct led behaviour.
  1272. */
  1273. #ifdef CONFIG_RT2X00_LIB_LEDS
  1274. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
  1275. rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  1276. if (value == LED_MODE_TXRX_ACTIVITY ||
  1277. value == LED_MODE_DEFAULT ||
  1278. value == LED_MODE_ASUS)
  1279. rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
  1280. LED_TYPE_ACTIVITY);
  1281. #endif /* CONFIG_RT2X00_LIB_LEDS */
  1282. /*
  1283. * Detect if this device has an hardware controlled radio.
  1284. */
  1285. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1286. __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
  1287. /*
  1288. * Read the RSSI <-> dBm offset information.
  1289. */
  1290. eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET);
  1291. rt2x00dev->rssi_offset =
  1292. rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
  1293. return 0;
  1294. }
  1295. /*
  1296. * RF value list for RF2522
  1297. * Supports: 2.4 GHz
  1298. */
  1299. static const struct rf_channel rf_vals_bg_2522[] = {
  1300. { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
  1301. { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
  1302. { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
  1303. { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
  1304. { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
  1305. { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
  1306. { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
  1307. { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
  1308. { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
  1309. { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
  1310. { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
  1311. { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
  1312. { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
  1313. { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
  1314. };
  1315. /*
  1316. * RF value list for RF2523
  1317. * Supports: 2.4 GHz
  1318. */
  1319. static const struct rf_channel rf_vals_bg_2523[] = {
  1320. { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
  1321. { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
  1322. { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
  1323. { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
  1324. { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
  1325. { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
  1326. { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
  1327. { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
  1328. { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
  1329. { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
  1330. { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
  1331. { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
  1332. { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
  1333. { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
  1334. };
  1335. /*
  1336. * RF value list for RF2524
  1337. * Supports: 2.4 GHz
  1338. */
  1339. static const struct rf_channel rf_vals_bg_2524[] = {
  1340. { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
  1341. { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
  1342. { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
  1343. { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
  1344. { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
  1345. { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
  1346. { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
  1347. { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
  1348. { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
  1349. { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
  1350. { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
  1351. { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
  1352. { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
  1353. { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
  1354. };
  1355. /*
  1356. * RF value list for RF2525
  1357. * Supports: 2.4 GHz
  1358. */
  1359. static const struct rf_channel rf_vals_bg_2525[] = {
  1360. { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
  1361. { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
  1362. { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
  1363. { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
  1364. { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
  1365. { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
  1366. { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
  1367. { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
  1368. { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
  1369. { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
  1370. { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
  1371. { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
  1372. { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
  1373. { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
  1374. };
  1375. /*
  1376. * RF value list for RF2525e
  1377. * Supports: 2.4 GHz
  1378. */
  1379. static const struct rf_channel rf_vals_bg_2525e[] = {
  1380. { 1, 0x00022010, 0x0000089a, 0x00060111, 0x00000e1b },
  1381. { 2, 0x00022010, 0x0000089e, 0x00060111, 0x00000e07 },
  1382. { 3, 0x00022010, 0x0000089e, 0x00060111, 0x00000e1b },
  1383. { 4, 0x00022010, 0x000008a2, 0x00060111, 0x00000e07 },
  1384. { 5, 0x00022010, 0x000008a2, 0x00060111, 0x00000e1b },
  1385. { 6, 0x00022010, 0x000008a6, 0x00060111, 0x00000e07 },
  1386. { 7, 0x00022010, 0x000008a6, 0x00060111, 0x00000e1b },
  1387. { 8, 0x00022010, 0x000008aa, 0x00060111, 0x00000e07 },
  1388. { 9, 0x00022010, 0x000008aa, 0x00060111, 0x00000e1b },
  1389. { 10, 0x00022010, 0x000008ae, 0x00060111, 0x00000e07 },
  1390. { 11, 0x00022010, 0x000008ae, 0x00060111, 0x00000e1b },
  1391. { 12, 0x00022010, 0x000008b2, 0x00060111, 0x00000e07 },
  1392. { 13, 0x00022010, 0x000008b2, 0x00060111, 0x00000e1b },
  1393. { 14, 0x00022010, 0x000008b6, 0x00060111, 0x00000e23 },
  1394. };
  1395. /*
  1396. * RF value list for RF5222
  1397. * Supports: 2.4 GHz & 5.2 GHz
  1398. */
  1399. static const struct rf_channel rf_vals_5222[] = {
  1400. { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
  1401. { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
  1402. { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
  1403. { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
  1404. { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
  1405. { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
  1406. { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
  1407. { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
  1408. { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
  1409. { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
  1410. { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
  1411. { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
  1412. { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
  1413. { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
  1414. /* 802.11 UNI / HyperLan 2 */
  1415. { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
  1416. { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
  1417. { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
  1418. { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
  1419. { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
  1420. { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
  1421. { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
  1422. { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
  1423. /* 802.11 HyperLan 2 */
  1424. { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
  1425. { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
  1426. { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
  1427. { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
  1428. { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
  1429. { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
  1430. { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
  1431. { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
  1432. { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
  1433. { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
  1434. /* 802.11 UNII */
  1435. { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
  1436. { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
  1437. { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
  1438. { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
  1439. { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
  1440. };
  1441. static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1442. {
  1443. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1444. struct channel_info *info;
  1445. u8 *tx_power;
  1446. unsigned int i;
  1447. /*
  1448. * Initialize all hw fields.
  1449. *
  1450. * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
  1451. * capable of sending the buffered frames out after the DTIM
  1452. * transmission using rt2x00lib_beacondone. This will send out
  1453. * multicast and broadcast traffic immediately instead of buffering it
  1454. * infinitly and thus dropping it after some time.
  1455. */
  1456. ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
  1457. ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
  1458. ieee80211_hw_set(rt2x00dev->hw, RX_INCLUDES_FCS);
  1459. ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
  1460. /*
  1461. * Disable powersaving as default.
  1462. */
  1463. rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  1464. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  1465. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1466. rt2x00_eeprom_addr(rt2x00dev,
  1467. EEPROM_MAC_ADDR_0));
  1468. /*
  1469. * Initialize hw_mode information.
  1470. */
  1471. spec->supported_bands = SUPPORT_BAND_2GHZ;
  1472. spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
  1473. if (rt2x00_rf(rt2x00dev, RF2522)) {
  1474. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
  1475. spec->channels = rf_vals_bg_2522;
  1476. } else if (rt2x00_rf(rt2x00dev, RF2523)) {
  1477. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
  1478. spec->channels = rf_vals_bg_2523;
  1479. } else if (rt2x00_rf(rt2x00dev, RF2524)) {
  1480. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
  1481. spec->channels = rf_vals_bg_2524;
  1482. } else if (rt2x00_rf(rt2x00dev, RF2525)) {
  1483. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
  1484. spec->channels = rf_vals_bg_2525;
  1485. } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
  1486. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
  1487. spec->channels = rf_vals_bg_2525e;
  1488. } else if (rt2x00_rf(rt2x00dev, RF5222)) {
  1489. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  1490. spec->num_channels = ARRAY_SIZE(rf_vals_5222);
  1491. spec->channels = rf_vals_5222;
  1492. }
  1493. /*
  1494. * Create channel information array
  1495. */
  1496. info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
  1497. if (!info)
  1498. return -ENOMEM;
  1499. spec->channels_info = info;
  1500. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
  1501. for (i = 0; i < 14; i++) {
  1502. info[i].max_power = MAX_TXPOWER;
  1503. info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  1504. }
  1505. if (spec->num_channels > 14) {
  1506. for (i = 14; i < spec->num_channels; i++) {
  1507. info[i].max_power = MAX_TXPOWER;
  1508. info[i].default_power1 = DEFAULT_TXPOWER;
  1509. }
  1510. }
  1511. return 0;
  1512. }
  1513. static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
  1514. {
  1515. int retval;
  1516. u16 reg;
  1517. /*
  1518. * Allocate eeprom data.
  1519. */
  1520. retval = rt2500usb_validate_eeprom(rt2x00dev);
  1521. if (retval)
  1522. return retval;
  1523. retval = rt2500usb_init_eeprom(rt2x00dev);
  1524. if (retval)
  1525. return retval;
  1526. /*
  1527. * Enable rfkill polling by setting GPIO direction of the
  1528. * rfkill switch GPIO pin correctly.
  1529. */
  1530. reg = rt2500usb_register_read(rt2x00dev, MAC_CSR19);
  1531. rt2x00_set_field16(&reg, MAC_CSR19_DIR0, 0);
  1532. rt2500usb_register_write(rt2x00dev, MAC_CSR19, reg);
  1533. /*
  1534. * Initialize hw specifications.
  1535. */
  1536. retval = rt2500usb_probe_hw_mode(rt2x00dev);
  1537. if (retval)
  1538. return retval;
  1539. /*
  1540. * This device requires the atim queue
  1541. */
  1542. __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
  1543. __set_bit(REQUIRE_BEACON_GUARD, &rt2x00dev->cap_flags);
  1544. if (!modparam_nohwcrypt) {
  1545. __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
  1546. __set_bit(REQUIRE_COPY_IV, &rt2x00dev->cap_flags);
  1547. }
  1548. __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
  1549. __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
  1550. /*
  1551. * Set the rssi offset.
  1552. */
  1553. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1554. return 0;
  1555. }
  1556. static const struct ieee80211_ops rt2500usb_mac80211_ops = {
  1557. .tx = rt2x00mac_tx,
  1558. .start = rt2x00mac_start,
  1559. .stop = rt2x00mac_stop,
  1560. .add_interface = rt2x00mac_add_interface,
  1561. .remove_interface = rt2x00mac_remove_interface,
  1562. .config = rt2x00mac_config,
  1563. .configure_filter = rt2x00mac_configure_filter,
  1564. .set_tim = rt2x00mac_set_tim,
  1565. .set_key = rt2x00mac_set_key,
  1566. .sw_scan_start = rt2x00mac_sw_scan_start,
  1567. .sw_scan_complete = rt2x00mac_sw_scan_complete,
  1568. .get_stats = rt2x00mac_get_stats,
  1569. .bss_info_changed = rt2x00mac_bss_info_changed,
  1570. .conf_tx = rt2x00mac_conf_tx,
  1571. .rfkill_poll = rt2x00mac_rfkill_poll,
  1572. .flush = rt2x00mac_flush,
  1573. .set_antenna = rt2x00mac_set_antenna,
  1574. .get_antenna = rt2x00mac_get_antenna,
  1575. .get_ringparam = rt2x00mac_get_ringparam,
  1576. .tx_frames_pending = rt2x00mac_tx_frames_pending,
  1577. };
  1578. static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
  1579. .probe_hw = rt2500usb_probe_hw,
  1580. .initialize = rt2x00usb_initialize,
  1581. .uninitialize = rt2x00usb_uninitialize,
  1582. .clear_entry = rt2x00usb_clear_entry,
  1583. .set_device_state = rt2500usb_set_device_state,
  1584. .rfkill_poll = rt2500usb_rfkill_poll,
  1585. .link_stats = rt2500usb_link_stats,
  1586. .reset_tuner = rt2500usb_reset_tuner,
  1587. .watchdog = rt2x00usb_watchdog,
  1588. .start_queue = rt2500usb_start_queue,
  1589. .kick_queue = rt2x00usb_kick_queue,
  1590. .stop_queue = rt2500usb_stop_queue,
  1591. .flush_queue = rt2x00usb_flush_queue,
  1592. .write_tx_desc = rt2500usb_write_tx_desc,
  1593. .write_beacon = rt2500usb_write_beacon,
  1594. .get_tx_data_len = rt2500usb_get_tx_data_len,
  1595. .fill_rxdone = rt2500usb_fill_rxdone,
  1596. .config_shared_key = rt2500usb_config_key,
  1597. .config_pairwise_key = rt2500usb_config_key,
  1598. .config_filter = rt2500usb_config_filter,
  1599. .config_intf = rt2500usb_config_intf,
  1600. .config_erp = rt2500usb_config_erp,
  1601. .config_ant = rt2500usb_config_ant,
  1602. .config = rt2500usb_config,
  1603. };
  1604. static void rt2500usb_queue_init(struct data_queue *queue)
  1605. {
  1606. switch (queue->qid) {
  1607. case QID_RX:
  1608. queue->limit = 32;
  1609. queue->data_size = DATA_FRAME_SIZE;
  1610. queue->desc_size = RXD_DESC_SIZE;
  1611. queue->priv_size = sizeof(struct queue_entry_priv_usb);
  1612. break;
  1613. case QID_AC_VO:
  1614. case QID_AC_VI:
  1615. case QID_AC_BE:
  1616. case QID_AC_BK:
  1617. queue->limit = 32;
  1618. queue->data_size = DATA_FRAME_SIZE;
  1619. queue->desc_size = TXD_DESC_SIZE;
  1620. queue->priv_size = sizeof(struct queue_entry_priv_usb);
  1621. break;
  1622. case QID_BEACON:
  1623. queue->limit = 1;
  1624. queue->data_size = MGMT_FRAME_SIZE;
  1625. queue->desc_size = TXD_DESC_SIZE;
  1626. queue->priv_size = sizeof(struct queue_entry_priv_usb_bcn);
  1627. break;
  1628. case QID_ATIM:
  1629. queue->limit = 8;
  1630. queue->data_size = DATA_FRAME_SIZE;
  1631. queue->desc_size = TXD_DESC_SIZE;
  1632. queue->priv_size = sizeof(struct queue_entry_priv_usb);
  1633. break;
  1634. default:
  1635. BUG();
  1636. break;
  1637. }
  1638. }
  1639. static const struct rt2x00_ops rt2500usb_ops = {
  1640. .name = KBUILD_MODNAME,
  1641. .max_ap_intf = 1,
  1642. .eeprom_size = EEPROM_SIZE,
  1643. .rf_size = RF_SIZE,
  1644. .tx_queues = NUM_TX_QUEUES,
  1645. .queue_init = rt2500usb_queue_init,
  1646. .lib = &rt2500usb_rt2x00_ops,
  1647. .hw = &rt2500usb_mac80211_ops,
  1648. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  1649. .debugfs = &rt2500usb_rt2x00debug,
  1650. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  1651. };
  1652. /*
  1653. * rt2500usb module information.
  1654. */
  1655. static const struct usb_device_id rt2500usb_device_table[] = {
  1656. /* ASUS */
  1657. { USB_DEVICE(0x0b05, 0x1706) },
  1658. { USB_DEVICE(0x0b05, 0x1707) },
  1659. /* Belkin */
  1660. { USB_DEVICE(0x050d, 0x7050) }, /* FCC ID: K7SF5D7050A ver. 2.x */
  1661. { USB_DEVICE(0x050d, 0x7051) },
  1662. /* Cisco Systems */
  1663. { USB_DEVICE(0x13b1, 0x000d) },
  1664. { USB_DEVICE(0x13b1, 0x0011) },
  1665. { USB_DEVICE(0x13b1, 0x001a) },
  1666. /* Conceptronic */
  1667. { USB_DEVICE(0x14b2, 0x3c02) },
  1668. /* D-LINK */
  1669. { USB_DEVICE(0x2001, 0x3c00) },
  1670. /* Gigabyte */
  1671. { USB_DEVICE(0x1044, 0x8001) },
  1672. { USB_DEVICE(0x1044, 0x8007) },
  1673. /* Hercules */
  1674. { USB_DEVICE(0x06f8, 0xe000) },
  1675. /* Melco */
  1676. { USB_DEVICE(0x0411, 0x005e) },
  1677. { USB_DEVICE(0x0411, 0x0066) },
  1678. { USB_DEVICE(0x0411, 0x0067) },
  1679. { USB_DEVICE(0x0411, 0x008b) },
  1680. { USB_DEVICE(0x0411, 0x0097) },
  1681. /* MSI */
  1682. { USB_DEVICE(0x0db0, 0x6861) },
  1683. { USB_DEVICE(0x0db0, 0x6865) },
  1684. { USB_DEVICE(0x0db0, 0x6869) },
  1685. /* Ralink */
  1686. { USB_DEVICE(0x148f, 0x1706) },
  1687. { USB_DEVICE(0x148f, 0x2570) },
  1688. { USB_DEVICE(0x148f, 0x9020) },
  1689. /* Sagem */
  1690. { USB_DEVICE(0x079b, 0x004b) },
  1691. /* Siemens */
  1692. { USB_DEVICE(0x0681, 0x3c06) },
  1693. /* SMC */
  1694. { USB_DEVICE(0x0707, 0xee13) },
  1695. /* Spairon */
  1696. { USB_DEVICE(0x114b, 0x0110) },
  1697. /* SURECOM */
  1698. { USB_DEVICE(0x0769, 0x11f3) },
  1699. /* Trust */
  1700. { USB_DEVICE(0x0eb0, 0x9020) },
  1701. /* VTech */
  1702. { USB_DEVICE(0x0f88, 0x3012) },
  1703. /* Zinwell */
  1704. { USB_DEVICE(0x5a57, 0x0260) },
  1705. { 0, }
  1706. };
  1707. MODULE_AUTHOR(DRV_PROJECT);
  1708. MODULE_VERSION(DRV_VERSION);
  1709. MODULE_DESCRIPTION("Ralink RT2500 USB Wireless LAN driver.");
  1710. MODULE_DEVICE_TABLE(usb, rt2500usb_device_table);
  1711. MODULE_LICENSE("GPL");
  1712. static int rt2500usb_probe(struct usb_interface *usb_intf,
  1713. const struct usb_device_id *id)
  1714. {
  1715. return rt2x00usb_probe(usb_intf, &rt2500usb_ops);
  1716. }
  1717. static struct usb_driver rt2500usb_driver = {
  1718. .name = KBUILD_MODNAME,
  1719. .id_table = rt2500usb_device_table,
  1720. .probe = rt2500usb_probe,
  1721. .disconnect = rt2x00usb_disconnect,
  1722. .suspend = rt2x00usb_suspend,
  1723. .resume = rt2x00usb_resume,
  1724. .reset_resume = rt2x00usb_resume,
  1725. .disable_hub_initiated_lpm = 1,
  1726. };
  1727. module_usb_driver(rt2500usb_driver);