mmio.c 2.3 KB

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  1. // SPDX-License-Identifier: ISC
  2. /*
  3. * Copyright (C) 2016 Felix Fietkau <[email protected]>
  4. */
  5. #include "mt76.h"
  6. #include "trace.h"
  7. static u32 mt76_mmio_rr(struct mt76_dev *dev, u32 offset)
  8. {
  9. u32 val;
  10. val = readl(dev->mmio.regs + offset);
  11. trace_reg_rr(dev, offset, val);
  12. return val;
  13. }
  14. static void mt76_mmio_wr(struct mt76_dev *dev, u32 offset, u32 val)
  15. {
  16. trace_reg_wr(dev, offset, val);
  17. writel(val, dev->mmio.regs + offset);
  18. }
  19. static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
  20. {
  21. val |= mt76_mmio_rr(dev, offset) & ~mask;
  22. mt76_mmio_wr(dev, offset, val);
  23. return val;
  24. }
  25. static void mt76_mmio_write_copy(struct mt76_dev *dev, u32 offset,
  26. const void *data, int len)
  27. {
  28. __iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4));
  29. }
  30. static void mt76_mmio_read_copy(struct mt76_dev *dev, u32 offset,
  31. void *data, int len)
  32. {
  33. __ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4));
  34. }
  35. static int mt76_mmio_wr_rp(struct mt76_dev *dev, u32 base,
  36. const struct mt76_reg_pair *data, int len)
  37. {
  38. while (len > 0) {
  39. mt76_mmio_wr(dev, data->reg, data->value);
  40. data++;
  41. len--;
  42. }
  43. return 0;
  44. }
  45. static int mt76_mmio_rd_rp(struct mt76_dev *dev, u32 base,
  46. struct mt76_reg_pair *data, int len)
  47. {
  48. while (len > 0) {
  49. data->value = mt76_mmio_rr(dev, data->reg);
  50. data++;
  51. len--;
  52. }
  53. return 0;
  54. }
  55. void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr,
  56. u32 clear, u32 set)
  57. {
  58. unsigned long flags;
  59. spin_lock_irqsave(&dev->mmio.irq_lock, flags);
  60. dev->mmio.irqmask &= ~clear;
  61. dev->mmio.irqmask |= set;
  62. if (addr) {
  63. if (mtk_wed_device_active(&dev->mmio.wed))
  64. mtk_wed_device_irq_set_mask(&dev->mmio.wed,
  65. dev->mmio.irqmask);
  66. else
  67. mt76_mmio_wr(dev, addr, dev->mmio.irqmask);
  68. }
  69. spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);
  70. }
  71. EXPORT_SYMBOL_GPL(mt76_set_irq_mask);
  72. void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs)
  73. {
  74. static const struct mt76_bus_ops mt76_mmio_ops = {
  75. .rr = mt76_mmio_rr,
  76. .rmw = mt76_mmio_rmw,
  77. .wr = mt76_mmio_wr,
  78. .write_copy = mt76_mmio_write_copy,
  79. .read_copy = mt76_mmio_read_copy,
  80. .wr_rp = mt76_mmio_wr_rp,
  81. .rd_rp = mt76_mmio_rd_rp,
  82. .type = MT76_BUS_MMIO,
  83. };
  84. dev->bus = &mt76_mmio_ops;
  85. dev->mmio.regs = regs;
  86. spin_lock_init(&dev->mmio.irq_lock);
  87. }
  88. EXPORT_SYMBOL_GPL(mt76_mmio_init);