p54spi.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2008 Christian Lamparter <[email protected]>
  4. *
  5. * This driver is a port from stlc45xx:
  6. * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
  7. */
  8. #ifndef P54SPI_H
  9. #define P54SPI_H
  10. #include <linux/mutex.h>
  11. #include <linux/list.h>
  12. #include <net/mac80211.h>
  13. #include "p54.h"
  14. /* Bit 15 is read/write bit; ON = READ, OFF = WRITE */
  15. #define SPI_ADRS_READ_BIT_15 0x8000
  16. #define SPI_ADRS_ARM_INTERRUPTS 0x00
  17. #define SPI_ADRS_ARM_INT_EN 0x04
  18. #define SPI_ADRS_HOST_INTERRUPTS 0x08
  19. #define SPI_ADRS_HOST_INT_EN 0x0c
  20. #define SPI_ADRS_HOST_INT_ACK 0x10
  21. #define SPI_ADRS_GEN_PURP_1 0x14
  22. #define SPI_ADRS_GEN_PURP_2 0x18
  23. #define SPI_ADRS_DEV_CTRL_STAT 0x26 /* high word */
  24. #define SPI_ADRS_DMA_DATA 0x28
  25. #define SPI_ADRS_DMA_WRITE_CTRL 0x2c
  26. #define SPI_ADRS_DMA_WRITE_LEN 0x2e
  27. #define SPI_ADRS_DMA_WRITE_BASE 0x30
  28. #define SPI_ADRS_DMA_READ_CTRL 0x34
  29. #define SPI_ADRS_DMA_READ_LEN 0x36
  30. #define SPI_ADRS_DMA_READ_BASE 0x38
  31. #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000
  32. #define SPI_CTRL_STAT_START_HALTED 0x4000
  33. #define SPI_CTRL_STAT_RAM_BOOT 0x2000
  34. #define SPI_CTRL_STAT_HOST_RESET 0x1000
  35. #define SPI_CTRL_STAT_HOST_CPU_EN 0x0800
  36. #define SPI_DMA_WRITE_CTRL_ENABLE 0x0001
  37. #define SPI_DMA_READ_CTRL_ENABLE 0x0001
  38. #define HOST_ALLOWED (1 << 7)
  39. #define SPI_TIMEOUT 100 /* msec */
  40. #define SPI_MAX_TX_PACKETS 32
  41. #define SPI_MAX_PACKET_SIZE 32767
  42. #define SPI_TARGET_INT_WAKEUP 0x00000001
  43. #define SPI_TARGET_INT_SLEEP 0x00000002
  44. #define SPI_TARGET_INT_RDDONE 0x00000004
  45. #define SPI_TARGET_INT_CTS 0x00004000
  46. #define SPI_TARGET_INT_DR 0x00008000
  47. #define SPI_HOST_INT_READY 0x00000001
  48. #define SPI_HOST_INT_WR_READY 0x00000002
  49. #define SPI_HOST_INT_SW_UPDATE 0x00000004
  50. #define SPI_HOST_INT_UPDATE 0x10000000
  51. /* clear to send */
  52. #define SPI_HOST_INT_CR 0x00004000
  53. /* data ready */
  54. #define SPI_HOST_INT_DR 0x00008000
  55. #define SPI_HOST_INTS_DEFAULT \
  56. (SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)
  57. #define TARGET_BOOT_SLEEP 50
  58. struct p54s_dma_regs {
  59. __le16 cmd;
  60. __le16 len;
  61. __le32 addr;
  62. } __packed;
  63. struct p54s_tx_info {
  64. struct list_head tx_list;
  65. };
  66. struct p54s_priv {
  67. /* p54_common has to be the first entry */
  68. struct p54_common common;
  69. struct ieee80211_hw *hw;
  70. struct spi_device *spi;
  71. struct work_struct work;
  72. struct mutex mutex;
  73. struct completion fw_comp;
  74. spinlock_t tx_lock;
  75. /* protected by tx_lock */
  76. struct list_head tx_pending;
  77. enum fw_state fw_state;
  78. const struct firmware *firmware;
  79. };
  80. #endif /* P54SPI_H */