iwl-eeprom-parse.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2005-2014, 2018-2020 Intel Corporation
  4. * Copyright (C) 2015 Intel Mobile Communications GmbH
  5. */
  6. #include <linux/types.h>
  7. #include <linux/slab.h>
  8. #include <linux/export.h>
  9. #include "iwl-drv.h"
  10. #include "iwl-modparams.h"
  11. #include "iwl-eeprom-parse.h"
  12. #if IS_ENABLED(CONFIG_IWLDVM)
  13. /* EEPROM offset definitions */
  14. /* indirect access definitions */
  15. #define ADDRESS_MSK 0x0000FFFF
  16. #define INDIRECT_TYPE_MSK 0x000F0000
  17. #define INDIRECT_HOST 0x00010000
  18. #define INDIRECT_GENERAL 0x00020000
  19. #define INDIRECT_REGULATORY 0x00030000
  20. #define INDIRECT_CALIBRATION 0x00040000
  21. #define INDIRECT_PROCESS_ADJST 0x00050000
  22. #define INDIRECT_OTHERS 0x00060000
  23. #define INDIRECT_TXP_LIMIT 0x00070000
  24. #define INDIRECT_TXP_LIMIT_SIZE 0x00080000
  25. #define INDIRECT_ADDRESS 0x00100000
  26. /* corresponding link offsets in EEPROM */
  27. #define EEPROM_LINK_HOST (2*0x64)
  28. #define EEPROM_LINK_GENERAL (2*0x65)
  29. #define EEPROM_LINK_REGULATORY (2*0x66)
  30. #define EEPROM_LINK_CALIBRATION (2*0x67)
  31. #define EEPROM_LINK_PROCESS_ADJST (2*0x68)
  32. #define EEPROM_LINK_OTHERS (2*0x69)
  33. #define EEPROM_LINK_TXP_LIMIT (2*0x6a)
  34. #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
  35. /* General */
  36. #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
  37. #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
  38. #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
  39. #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
  40. #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
  41. #define EEPROM_VERSION (2*0x44) /* 2 bytes */
  42. #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
  43. #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
  44. #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
  45. #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
  46. /* calibration */
  47. struct iwl_eeprom_calib_hdr {
  48. u8 version;
  49. u8 pa_type;
  50. __le16 voltage;
  51. } __packed;
  52. #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
  53. #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
  54. /* temperature */
  55. #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
  56. #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL)
  57. /* SKU Capabilities (actual values from EEPROM definition) */
  58. enum eeprom_sku_bits {
  59. EEPROM_SKU_CAP_BAND_24GHZ = BIT(4),
  60. EEPROM_SKU_CAP_BAND_52GHZ = BIT(5),
  61. EEPROM_SKU_CAP_11N_ENABLE = BIT(6),
  62. EEPROM_SKU_CAP_AMT_ENABLE = BIT(7),
  63. EEPROM_SKU_CAP_IPAN_ENABLE = BIT(8)
  64. };
  65. /* radio config bits (actual values from EEPROM definition) */
  66. #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
  67. #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
  68. #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
  69. #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
  70. #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
  71. #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
  72. /*
  73. * EEPROM bands
  74. * These are the channel numbers from each band in the order
  75. * that they are stored in the EEPROM band information. Note
  76. * that EEPROM bands aren't the same as mac80211 bands, and
  77. * there are even special "ht40 bands" in the EEPROM.
  78. */
  79. static const u8 iwl_eeprom_band_1[14] = { /* 2.4 GHz */
  80. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  81. };
  82. static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
  83. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  84. };
  85. static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
  86. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  87. };
  88. static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
  89. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  90. };
  91. static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
  92. 145, 149, 153, 157, 161, 165
  93. };
  94. static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */
  95. 1, 2, 3, 4, 5, 6, 7
  96. };
  97. static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
  98. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  99. };
  100. #define IWL_NUM_CHANNELS (ARRAY_SIZE(iwl_eeprom_band_1) + \
  101. ARRAY_SIZE(iwl_eeprom_band_2) + \
  102. ARRAY_SIZE(iwl_eeprom_band_3) + \
  103. ARRAY_SIZE(iwl_eeprom_band_4) + \
  104. ARRAY_SIZE(iwl_eeprom_band_5))
  105. /* rate data (static) */
  106. static struct ieee80211_rate iwl_cfg80211_rates[] = {
  107. { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
  108. { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
  109. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  110. { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
  111. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  112. { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
  113. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  114. { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
  115. { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
  116. { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
  117. { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
  118. { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
  119. { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
  120. { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
  121. { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
  122. };
  123. #define RATES_24_OFFS 0
  124. #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
  125. #define RATES_52_OFFS 4
  126. #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
  127. /* EEPROM reading functions */
  128. static u16 iwl_eeprom_query16(const u8 *eeprom, size_t eeprom_size, int offset)
  129. {
  130. if (WARN_ON(offset + sizeof(u16) > eeprom_size))
  131. return 0;
  132. return le16_to_cpup((__le16 *)(eeprom + offset));
  133. }
  134. static u32 eeprom_indirect_address(const u8 *eeprom, size_t eeprom_size,
  135. u32 address)
  136. {
  137. u16 offset = 0;
  138. if ((address & INDIRECT_ADDRESS) == 0)
  139. return address;
  140. switch (address & INDIRECT_TYPE_MSK) {
  141. case INDIRECT_HOST:
  142. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  143. EEPROM_LINK_HOST);
  144. break;
  145. case INDIRECT_GENERAL:
  146. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  147. EEPROM_LINK_GENERAL);
  148. break;
  149. case INDIRECT_REGULATORY:
  150. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  151. EEPROM_LINK_REGULATORY);
  152. break;
  153. case INDIRECT_TXP_LIMIT:
  154. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  155. EEPROM_LINK_TXP_LIMIT);
  156. break;
  157. case INDIRECT_TXP_LIMIT_SIZE:
  158. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  159. EEPROM_LINK_TXP_LIMIT_SIZE);
  160. break;
  161. case INDIRECT_CALIBRATION:
  162. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  163. EEPROM_LINK_CALIBRATION);
  164. break;
  165. case INDIRECT_PROCESS_ADJST:
  166. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  167. EEPROM_LINK_PROCESS_ADJST);
  168. break;
  169. case INDIRECT_OTHERS:
  170. offset = iwl_eeprom_query16(eeprom, eeprom_size,
  171. EEPROM_LINK_OTHERS);
  172. break;
  173. default:
  174. WARN_ON(1);
  175. break;
  176. }
  177. /* translate the offset from words to byte */
  178. return (address & ADDRESS_MSK) + (offset << 1);
  179. }
  180. static const u8 *iwl_eeprom_query_addr(const u8 *eeprom, size_t eeprom_size,
  181. u32 offset)
  182. {
  183. u32 address = eeprom_indirect_address(eeprom, eeprom_size, offset);
  184. if (WARN_ON(address >= eeprom_size))
  185. return NULL;
  186. return &eeprom[address];
  187. }
  188. static int iwl_eeprom_read_calib(const u8 *eeprom, size_t eeprom_size,
  189. struct iwl_nvm_data *data)
  190. {
  191. struct iwl_eeprom_calib_hdr *hdr;
  192. hdr = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size,
  193. EEPROM_CALIB_ALL);
  194. if (!hdr)
  195. return -ENODATA;
  196. data->calib_version = hdr->version;
  197. data->calib_voltage = hdr->voltage;
  198. return 0;
  199. }
  200. /**
  201. * enum iwl_eeprom_channel_flags - channel flags in EEPROM
  202. * @EEPROM_CHANNEL_VALID: channel is usable for this SKU/geo
  203. * @EEPROM_CHANNEL_IBSS: usable as an IBSS channel
  204. * @EEPROM_CHANNEL_ACTIVE: active scanning allowed
  205. * @EEPROM_CHANNEL_RADAR: radar detection required
  206. * @EEPROM_CHANNEL_WIDE: 20 MHz channel okay (?)
  207. * @EEPROM_CHANNEL_DFS: dynamic freq selection candidate
  208. */
  209. enum iwl_eeprom_channel_flags {
  210. EEPROM_CHANNEL_VALID = BIT(0),
  211. EEPROM_CHANNEL_IBSS = BIT(1),
  212. EEPROM_CHANNEL_ACTIVE = BIT(3),
  213. EEPROM_CHANNEL_RADAR = BIT(4),
  214. EEPROM_CHANNEL_WIDE = BIT(5),
  215. EEPROM_CHANNEL_DFS = BIT(7),
  216. };
  217. /**
  218. * struct iwl_eeprom_channel - EEPROM channel data
  219. * @flags: %EEPROM_CHANNEL_* flags
  220. * @max_power_avg: max power (in dBm) on this channel, at most 31 dBm
  221. */
  222. struct iwl_eeprom_channel {
  223. u8 flags;
  224. s8 max_power_avg;
  225. } __packed;
  226. enum iwl_eeprom_enhanced_txpwr_flags {
  227. IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
  228. IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1),
  229. IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
  230. IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3),
  231. IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4),
  232. IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5),
  233. IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6),
  234. IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7),
  235. };
  236. /**
  237. * struct iwl_eeprom_enhanced_txpwr
  238. * @flags: entry flags
  239. * @channel: channel number
  240. * @chain_a_max: chain a max power in 1/2 dBm
  241. * @chain_b_max: chain b max power in 1/2 dBm
  242. * @chain_c_max: chain c max power in 1/2 dBm
  243. * @delta_20_in_40: 20-in-40 deltas (hi/lo)
  244. * @mimo2_max: mimo2 max power in 1/2 dBm
  245. * @mimo3_max: mimo3 max power in 1/2 dBm
  246. *
  247. * This structure presents the enhanced regulatory tx power limit layout
  248. * in an EEPROM image.
  249. */
  250. struct iwl_eeprom_enhanced_txpwr {
  251. u8 flags;
  252. u8 channel;
  253. s8 chain_a_max;
  254. s8 chain_b_max;
  255. s8 chain_c_max;
  256. u8 delta_20_in_40;
  257. s8 mimo2_max;
  258. s8 mimo3_max;
  259. } __packed;
  260. static s8 iwl_get_max_txpwr_half_dbm(const struct iwl_nvm_data *data,
  261. struct iwl_eeprom_enhanced_txpwr *txp)
  262. {
  263. s8 result = 0; /* (.5 dBm) */
  264. /* Take the highest tx power from any valid chains */
  265. if (data->valid_tx_ant & ANT_A && txp->chain_a_max > result)
  266. result = txp->chain_a_max;
  267. if (data->valid_tx_ant & ANT_B && txp->chain_b_max > result)
  268. result = txp->chain_b_max;
  269. if (data->valid_tx_ant & ANT_C && txp->chain_c_max > result)
  270. result = txp->chain_c_max;
  271. if ((data->valid_tx_ant == ANT_AB ||
  272. data->valid_tx_ant == ANT_BC ||
  273. data->valid_tx_ant == ANT_AC) && txp->mimo2_max > result)
  274. result = txp->mimo2_max;
  275. if (data->valid_tx_ant == ANT_ABC && txp->mimo3_max > result)
  276. result = txp->mimo3_max;
  277. return result;
  278. }
  279. #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
  280. #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
  281. #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
  282. #define TXP_CHECK_AND_PRINT(x) \
  283. ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) ? # x " " : "")
  284. static void
  285. iwl_eeprom_enh_txp_read_element(struct iwl_nvm_data *data,
  286. struct iwl_eeprom_enhanced_txpwr *txp,
  287. int n_channels, s8 max_txpower_avg)
  288. {
  289. int ch_idx;
  290. enum nl80211_band band;
  291. band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ?
  292. NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
  293. for (ch_idx = 0; ch_idx < n_channels; ch_idx++) {
  294. struct ieee80211_channel *chan = &data->channels[ch_idx];
  295. /* update matching channel or from common data only */
  296. if (txp->channel != 0 && chan->hw_value != txp->channel)
  297. continue;
  298. /* update matching band only */
  299. if (band != chan->band)
  300. continue;
  301. if (chan->max_power < max_txpower_avg &&
  302. !(txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ))
  303. chan->max_power = max_txpower_avg;
  304. }
  305. }
  306. static void iwl_eeprom_enhanced_txpower(struct device *dev,
  307. struct iwl_nvm_data *data,
  308. const u8 *eeprom, size_t eeprom_size,
  309. int n_channels)
  310. {
  311. struct iwl_eeprom_enhanced_txpwr *txp_array, *txp;
  312. int idx, entries;
  313. __le16 *txp_len;
  314. s8 max_txp_avg_halfdbm;
  315. BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
  316. /* the length is in 16-bit words, but we want entries */
  317. txp_len = (__le16 *)iwl_eeprom_query_addr(eeprom, eeprom_size,
  318. EEPROM_TXP_SZ_OFFS);
  319. entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
  320. txp_array = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size,
  321. EEPROM_TXP_OFFS);
  322. for (idx = 0; idx < entries; idx++) {
  323. txp = &txp_array[idx];
  324. /* skip invalid entries */
  325. if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID))
  326. continue;
  327. IWL_DEBUG_EEPROM(dev, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
  328. (txp->channel && (txp->flags &
  329. IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ?
  330. "Common " : (txp->channel) ?
  331. "Channel" : "Common",
  332. (txp->channel),
  333. TXP_CHECK_AND_PRINT(VALID),
  334. TXP_CHECK_AND_PRINT(BAND_52G),
  335. TXP_CHECK_AND_PRINT(OFDM),
  336. TXP_CHECK_AND_PRINT(40MHZ),
  337. TXP_CHECK_AND_PRINT(HT_AP),
  338. TXP_CHECK_AND_PRINT(RES1),
  339. TXP_CHECK_AND_PRINT(RES2),
  340. TXP_CHECK_AND_PRINT(COMMON_TYPE),
  341. txp->flags);
  342. IWL_DEBUG_EEPROM(dev,
  343. "\t\t chain_A: %d chain_B: %d chain_C: %d\n",
  344. txp->chain_a_max, txp->chain_b_max,
  345. txp->chain_c_max);
  346. IWL_DEBUG_EEPROM(dev,
  347. "\t\t MIMO2: %d MIMO3: %d High 20_on_40: 0x%02x Low 20_on_40: 0x%02x\n",
  348. txp->mimo2_max, txp->mimo3_max,
  349. ((txp->delta_20_in_40 & 0xf0) >> 4),
  350. (txp->delta_20_in_40 & 0x0f));
  351. max_txp_avg_halfdbm = iwl_get_max_txpwr_half_dbm(data, txp);
  352. iwl_eeprom_enh_txp_read_element(data, txp, n_channels,
  353. DIV_ROUND_UP(max_txp_avg_halfdbm, 2));
  354. if (max_txp_avg_halfdbm > data->max_tx_pwr_half_dbm)
  355. data->max_tx_pwr_half_dbm = max_txp_avg_halfdbm;
  356. }
  357. }
  358. static void iwl_init_band_reference(const struct iwl_cfg *cfg,
  359. const u8 *eeprom, size_t eeprom_size,
  360. int eeprom_band, int *eeprom_ch_count,
  361. const struct iwl_eeprom_channel **ch_info,
  362. const u8 **eeprom_ch_array)
  363. {
  364. u32 offset = cfg->eeprom_params->regulatory_bands[eeprom_band - 1];
  365. offset |= INDIRECT_ADDRESS | INDIRECT_REGULATORY;
  366. *ch_info = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, offset);
  367. switch (eeprom_band) {
  368. case 1: /* 2.4GHz band */
  369. *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
  370. *eeprom_ch_array = iwl_eeprom_band_1;
  371. break;
  372. case 2: /* 4.9GHz band */
  373. *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
  374. *eeprom_ch_array = iwl_eeprom_band_2;
  375. break;
  376. case 3: /* 5.2GHz band */
  377. *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
  378. *eeprom_ch_array = iwl_eeprom_band_3;
  379. break;
  380. case 4: /* 5.5GHz band */
  381. *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
  382. *eeprom_ch_array = iwl_eeprom_band_4;
  383. break;
  384. case 5: /* 5.7GHz band */
  385. *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
  386. *eeprom_ch_array = iwl_eeprom_band_5;
  387. break;
  388. case 6: /* 2.4GHz ht40 channels */
  389. *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
  390. *eeprom_ch_array = iwl_eeprom_band_6;
  391. break;
  392. case 7: /* 5 GHz ht40 channels */
  393. *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
  394. *eeprom_ch_array = iwl_eeprom_band_7;
  395. break;
  396. default:
  397. *eeprom_ch_count = 0;
  398. *eeprom_ch_array = NULL;
  399. WARN_ON(1);
  400. }
  401. }
  402. #define CHECK_AND_PRINT(x) \
  403. ((eeprom_ch->flags & EEPROM_CHANNEL_##x) ? # x " " : "")
  404. static void iwl_mod_ht40_chan_info(struct device *dev,
  405. struct iwl_nvm_data *data, int n_channels,
  406. enum nl80211_band band, u16 channel,
  407. const struct iwl_eeprom_channel *eeprom_ch,
  408. u8 clear_ht40_extension_channel)
  409. {
  410. struct ieee80211_channel *chan = NULL;
  411. int i;
  412. for (i = 0; i < n_channels; i++) {
  413. if (data->channels[i].band != band)
  414. continue;
  415. if (data->channels[i].hw_value != channel)
  416. continue;
  417. chan = &data->channels[i];
  418. break;
  419. }
  420. if (!chan)
  421. return;
  422. IWL_DEBUG_EEPROM(dev,
  423. "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
  424. channel,
  425. band == NL80211_BAND_5GHZ ? "5.2" : "2.4",
  426. CHECK_AND_PRINT(IBSS),
  427. CHECK_AND_PRINT(ACTIVE),
  428. CHECK_AND_PRINT(RADAR),
  429. CHECK_AND_PRINT(WIDE),
  430. CHECK_AND_PRINT(DFS),
  431. eeprom_ch->flags,
  432. eeprom_ch->max_power_avg,
  433. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
  434. !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? ""
  435. : "not ");
  436. if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
  437. chan->flags &= ~clear_ht40_extension_channel;
  438. }
  439. #define CHECK_AND_PRINT_I(x) \
  440. ((eeprom_ch_info[ch_idx].flags & EEPROM_CHANNEL_##x) ? # x " " : "")
  441. static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
  442. struct iwl_nvm_data *data,
  443. const u8 *eeprom, size_t eeprom_size)
  444. {
  445. int band, ch_idx;
  446. const struct iwl_eeprom_channel *eeprom_ch_info;
  447. const u8 *eeprom_ch_array;
  448. int eeprom_ch_count;
  449. int n_channels = 0;
  450. /*
  451. * Loop through the 5 EEPROM bands and add them to the parse list
  452. */
  453. for (band = 1; band <= 5; band++) {
  454. struct ieee80211_channel *channel;
  455. iwl_init_band_reference(cfg, eeprom, eeprom_size, band,
  456. &eeprom_ch_count, &eeprom_ch_info,
  457. &eeprom_ch_array);
  458. /* Loop through each band adding each of the channels */
  459. for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) {
  460. const struct iwl_eeprom_channel *eeprom_ch;
  461. eeprom_ch = &eeprom_ch_info[ch_idx];
  462. if (!(eeprom_ch->flags & EEPROM_CHANNEL_VALID)) {
  463. IWL_DEBUG_EEPROM(dev,
  464. "Ch. %d Flags %x [%sGHz] - No traffic\n",
  465. eeprom_ch_array[ch_idx],
  466. eeprom_ch_info[ch_idx].flags,
  467. (band != 1) ? "5.2" : "2.4");
  468. continue;
  469. }
  470. channel = &data->channels[n_channels];
  471. n_channels++;
  472. channel->hw_value = eeprom_ch_array[ch_idx];
  473. channel->band = (band == 1) ? NL80211_BAND_2GHZ
  474. : NL80211_BAND_5GHZ;
  475. channel->center_freq =
  476. ieee80211_channel_to_frequency(
  477. channel->hw_value, channel->band);
  478. /* set no-HT40, will enable as appropriate later */
  479. channel->flags = IEEE80211_CHAN_NO_HT40;
  480. if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
  481. channel->flags |= IEEE80211_CHAN_NO_IR;
  482. if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
  483. channel->flags |= IEEE80211_CHAN_NO_IR;
  484. if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
  485. channel->flags |= IEEE80211_CHAN_RADAR;
  486. /* Initialize regulatory-based run-time data */
  487. channel->max_power =
  488. eeprom_ch_info[ch_idx].max_power_avg;
  489. IWL_DEBUG_EEPROM(dev,
  490. "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
  491. channel->hw_value,
  492. (band != 1) ? "5.2" : "2.4",
  493. CHECK_AND_PRINT_I(VALID),
  494. CHECK_AND_PRINT_I(IBSS),
  495. CHECK_AND_PRINT_I(ACTIVE),
  496. CHECK_AND_PRINT_I(RADAR),
  497. CHECK_AND_PRINT_I(WIDE),
  498. CHECK_AND_PRINT_I(DFS),
  499. eeprom_ch_info[ch_idx].flags,
  500. eeprom_ch_info[ch_idx].max_power_avg,
  501. ((eeprom_ch_info[ch_idx].flags &
  502. EEPROM_CHANNEL_IBSS) &&
  503. !(eeprom_ch_info[ch_idx].flags &
  504. EEPROM_CHANNEL_RADAR))
  505. ? "" : "not ");
  506. }
  507. }
  508. if (cfg->eeprom_params->enhanced_txpower) {
  509. /*
  510. * for newer device (6000 series and up)
  511. * EEPROM contain enhanced tx power information
  512. * driver need to process addition information
  513. * to determine the max channel tx power limits
  514. */
  515. iwl_eeprom_enhanced_txpower(dev, data, eeprom, eeprom_size,
  516. n_channels);
  517. } else {
  518. /* All others use data from channel map */
  519. int i;
  520. data->max_tx_pwr_half_dbm = -128;
  521. for (i = 0; i < n_channels; i++)
  522. data->max_tx_pwr_half_dbm =
  523. max_t(s8, data->max_tx_pwr_half_dbm,
  524. data->channels[i].max_power * 2);
  525. }
  526. /* Check if we do have HT40 channels */
  527. if (cfg->eeprom_params->regulatory_bands[5] ==
  528. EEPROM_REGULATORY_BAND_NO_HT40 &&
  529. cfg->eeprom_params->regulatory_bands[6] ==
  530. EEPROM_REGULATORY_BAND_NO_HT40)
  531. return n_channels;
  532. /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
  533. for (band = 6; band <= 7; band++) {
  534. enum nl80211_band ieeeband;
  535. iwl_init_band_reference(cfg, eeprom, eeprom_size, band,
  536. &eeprom_ch_count, &eeprom_ch_info,
  537. &eeprom_ch_array);
  538. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  539. ieeeband = (band == 6) ? NL80211_BAND_2GHZ
  540. : NL80211_BAND_5GHZ;
  541. /* Loop through each band adding each of the channels */
  542. for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) {
  543. /* Set up driver's info for lower half */
  544. iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband,
  545. eeprom_ch_array[ch_idx],
  546. &eeprom_ch_info[ch_idx],
  547. IEEE80211_CHAN_NO_HT40PLUS);
  548. /* Set up driver's info for upper half */
  549. iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband,
  550. eeprom_ch_array[ch_idx] + 4,
  551. &eeprom_ch_info[ch_idx],
  552. IEEE80211_CHAN_NO_HT40MINUS);
  553. }
  554. }
  555. return n_channels;
  556. }
  557. #endif
  558. int iwl_init_sband_channels(struct iwl_nvm_data *data,
  559. struct ieee80211_supported_band *sband,
  560. int n_channels, enum nl80211_band band)
  561. {
  562. struct ieee80211_channel *chan = &data->channels[0];
  563. int n = 0, idx = 0;
  564. while (idx < n_channels && chan->band != band)
  565. chan = &data->channels[++idx];
  566. sband->channels = &data->channels[idx];
  567. while (idx < n_channels && chan->band == band) {
  568. chan = &data->channels[++idx];
  569. n++;
  570. }
  571. sband->n_channels = n;
  572. return n;
  573. }
  574. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  575. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  576. void iwl_init_ht_hw_capab(struct iwl_trans *trans,
  577. struct iwl_nvm_data *data,
  578. struct ieee80211_sta_ht_cap *ht_info,
  579. enum nl80211_band band,
  580. u8 tx_chains, u8 rx_chains)
  581. {
  582. const struct iwl_cfg *cfg = trans->cfg;
  583. int max_bit_rate = 0;
  584. tx_chains = hweight8(tx_chains);
  585. if (cfg->rx_with_siso_diversity)
  586. rx_chains = 1;
  587. else
  588. rx_chains = hweight8(rx_chains);
  589. if (!(data->sku_cap_11n_enable) ||
  590. (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) ||
  591. !cfg->ht_params) {
  592. ht_info->ht_supported = false;
  593. return;
  594. }
  595. if (data->sku_cap_mimo_disabled)
  596. rx_chains = 1;
  597. ht_info->ht_supported = true;
  598. ht_info->cap = IEEE80211_HT_CAP_DSSSCCK40;
  599. if (cfg->ht_params->stbc) {
  600. ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  601. if (tx_chains > 1)
  602. ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
  603. }
  604. if (cfg->ht_params->ldpc)
  605. ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
  606. if (trans->trans_cfg->mq_rx_supported ||
  607. iwlwifi_mod_params.amsdu_size >= IWL_AMSDU_8K)
  608. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  609. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  610. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
  611. ht_info->mcs.rx_mask[0] = 0xFF;
  612. if (rx_chains >= 2)
  613. ht_info->mcs.rx_mask[1] = 0xFF;
  614. if (rx_chains >= 3)
  615. ht_info->mcs.rx_mask[2] = 0xFF;
  616. if (cfg->ht_params->ht_greenfield_support)
  617. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  618. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  619. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  620. if (cfg->ht_params->ht40_bands & BIT(band)) {
  621. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  622. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  623. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  624. }
  625. /* Highest supported Rx data rate */
  626. max_bit_rate *= rx_chains;
  627. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  628. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  629. /* Tx MCS capabilities */
  630. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  631. if (tx_chains != rx_chains) {
  632. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  633. ht_info->mcs.tx_params |= ((tx_chains - 1) <<
  634. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  635. }
  636. }
  637. #if IS_ENABLED(CONFIG_IWLDVM)
  638. static void iwl_init_sbands(struct iwl_trans *trans, const struct iwl_cfg *cfg,
  639. struct iwl_nvm_data *data,
  640. const u8 *eeprom, size_t eeprom_size)
  641. {
  642. struct device *dev = trans->dev;
  643. int n_channels = iwl_init_channel_map(dev, cfg, data,
  644. eeprom, eeprom_size);
  645. int n_used = 0;
  646. struct ieee80211_supported_band *sband;
  647. sband = &data->bands[NL80211_BAND_2GHZ];
  648. sband->band = NL80211_BAND_2GHZ;
  649. sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
  650. sband->n_bitrates = N_RATES_24;
  651. n_used += iwl_init_sband_channels(data, sband, n_channels,
  652. NL80211_BAND_2GHZ);
  653. iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
  654. data->valid_tx_ant, data->valid_rx_ant);
  655. sband = &data->bands[NL80211_BAND_5GHZ];
  656. sband->band = NL80211_BAND_5GHZ;
  657. sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
  658. sband->n_bitrates = N_RATES_52;
  659. n_used += iwl_init_sband_channels(data, sband, n_channels,
  660. NL80211_BAND_5GHZ);
  661. iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
  662. data->valid_tx_ant, data->valid_rx_ant);
  663. if (n_channels != n_used)
  664. IWL_ERR_DEV(dev, "EEPROM: used only %d of %d channels\n",
  665. n_used, n_channels);
  666. }
  667. /* EEPROM data functions */
  668. struct iwl_nvm_data *
  669. iwl_parse_eeprom_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
  670. const u8 *eeprom, size_t eeprom_size)
  671. {
  672. struct iwl_nvm_data *data;
  673. struct device *dev = trans->dev;
  674. const void *tmp;
  675. u16 radio_cfg, sku;
  676. if (WARN_ON(!cfg || !cfg->eeprom_params))
  677. return NULL;
  678. data = kzalloc(struct_size(data, channels, IWL_NUM_CHANNELS),
  679. GFP_KERNEL);
  680. if (!data)
  681. return NULL;
  682. /* get MAC address(es) */
  683. tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_MAC_ADDRESS);
  684. if (!tmp)
  685. goto err_free;
  686. memcpy(data->hw_addr, tmp, ETH_ALEN);
  687. data->n_hw_addrs = iwl_eeprom_query16(eeprom, eeprom_size,
  688. EEPROM_NUM_MAC_ADDRESS);
  689. if (iwl_eeprom_read_calib(eeprom, eeprom_size, data))
  690. goto err_free;
  691. tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_XTAL);
  692. if (!tmp)
  693. goto err_free;
  694. memcpy(data->xtal_calib, tmp, sizeof(data->xtal_calib));
  695. tmp = iwl_eeprom_query_addr(eeprom, eeprom_size,
  696. EEPROM_RAW_TEMPERATURE);
  697. if (!tmp)
  698. goto err_free;
  699. data->raw_temperature = *(__le16 *)tmp;
  700. tmp = iwl_eeprom_query_addr(eeprom, eeprom_size,
  701. EEPROM_KELVIN_TEMPERATURE);
  702. if (!tmp)
  703. goto err_free;
  704. data->kelvin_temperature = *(__le16 *)tmp;
  705. data->kelvin_voltage = *((__le16 *)tmp + 1);
  706. radio_cfg = iwl_eeprom_query16(eeprom, eeprom_size,
  707. EEPROM_RADIO_CONFIG);
  708. data->radio_cfg_dash = EEPROM_RF_CFG_DASH_MSK(radio_cfg);
  709. data->radio_cfg_pnum = EEPROM_RF_CFG_PNUM_MSK(radio_cfg);
  710. data->radio_cfg_step = EEPROM_RF_CFG_STEP_MSK(radio_cfg);
  711. data->radio_cfg_type = EEPROM_RF_CFG_TYPE_MSK(radio_cfg);
  712. data->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg);
  713. data->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
  714. sku = iwl_eeprom_query16(eeprom, eeprom_size,
  715. EEPROM_SKU_CAP);
  716. data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE;
  717. data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE;
  718. data->sku_cap_band_24ghz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ;
  719. data->sku_cap_band_52ghz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ;
  720. data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE;
  721. if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
  722. data->sku_cap_11n_enable = false;
  723. data->nvm_version = iwl_eeprom_query16(eeprom, eeprom_size,
  724. EEPROM_VERSION);
  725. /* check overrides (some devices have wrong EEPROM) */
  726. if (cfg->valid_tx_ant)
  727. data->valid_tx_ant = cfg->valid_tx_ant;
  728. if (cfg->valid_rx_ant)
  729. data->valid_rx_ant = cfg->valid_rx_ant;
  730. if (!data->valid_tx_ant || !data->valid_rx_ant) {
  731. IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n",
  732. data->valid_tx_ant, data->valid_rx_ant);
  733. goto err_free;
  734. }
  735. iwl_init_sbands(trans, cfg, data, eeprom, eeprom_size);
  736. return data;
  737. err_free:
  738. kfree(data);
  739. return NULL;
  740. }
  741. IWL_EXPORT_SYMBOL(iwl_parse_eeprom_data);
  742. #endif