common.c 143 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /******************************************************************************
  3. *
  4. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  5. *
  6. * Contact Information:
  7. * Intel Linux Wireless <[email protected]>
  8. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  9. *****************************************************************************/
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/sched.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <linux/lockdep.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/delay.h>
  20. #include <linux/skbuff.h>
  21. #include <net/mac80211.h>
  22. #include "common.h"
  23. int
  24. _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
  25. {
  26. const int interval = 10; /* microseconds */
  27. int t = 0;
  28. do {
  29. if ((_il_rd(il, addr) & mask) == (bits & mask))
  30. return t;
  31. udelay(interval);
  32. t += interval;
  33. } while (t < timeout);
  34. return -ETIMEDOUT;
  35. }
  36. EXPORT_SYMBOL(_il_poll_bit);
  37. void
  38. il_set_bit(struct il_priv *p, u32 r, u32 m)
  39. {
  40. unsigned long reg_flags;
  41. spin_lock_irqsave(&p->reg_lock, reg_flags);
  42. _il_set_bit(p, r, m);
  43. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  44. }
  45. EXPORT_SYMBOL(il_set_bit);
  46. void
  47. il_clear_bit(struct il_priv *p, u32 r, u32 m)
  48. {
  49. unsigned long reg_flags;
  50. spin_lock_irqsave(&p->reg_lock, reg_flags);
  51. _il_clear_bit(p, r, m);
  52. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  53. }
  54. EXPORT_SYMBOL(il_clear_bit);
  55. bool
  56. _il_grab_nic_access(struct il_priv *il)
  57. {
  58. int ret;
  59. u32 val;
  60. /* this bit wakes up the NIC */
  61. _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  62. /*
  63. * These bits say the device is running, and should keep running for
  64. * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
  65. * but they do not indicate that embedded SRAM is restored yet;
  66. * 3945 and 4965 have volatile SRAM, and must save/restore contents
  67. * to/from host DRAM when sleeping/waking for power-saving.
  68. * Each direction takes approximately 1/4 millisecond; with this
  69. * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
  70. * series of register accesses are expected (e.g. reading Event Log),
  71. * to keep device from sleeping.
  72. *
  73. * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
  74. * SRAM is okay/restored. We don't check that here because this call
  75. * is just for hardware register access; but GP1 MAC_SLEEP check is a
  76. * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
  77. *
  78. */
  79. ret =
  80. _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
  81. (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
  82. CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
  83. if (unlikely(ret < 0)) {
  84. val = _il_rd(il, CSR_GP_CNTRL);
  85. WARN_ONCE(1, "Timeout waiting for ucode processor access "
  86. "(CSR_GP_CNTRL 0x%08x)\n", val);
  87. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
  88. return false;
  89. }
  90. return true;
  91. }
  92. EXPORT_SYMBOL_GPL(_il_grab_nic_access);
  93. int
  94. il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
  95. {
  96. const int interval = 10; /* microseconds */
  97. int t = 0;
  98. do {
  99. if ((il_rd(il, addr) & mask) == mask)
  100. return t;
  101. udelay(interval);
  102. t += interval;
  103. } while (t < timeout);
  104. return -ETIMEDOUT;
  105. }
  106. EXPORT_SYMBOL(il_poll_bit);
  107. u32
  108. il_rd_prph(struct il_priv *il, u32 reg)
  109. {
  110. unsigned long reg_flags;
  111. u32 val;
  112. spin_lock_irqsave(&il->reg_lock, reg_flags);
  113. _il_grab_nic_access(il);
  114. val = _il_rd_prph(il, reg);
  115. _il_release_nic_access(il);
  116. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  117. return val;
  118. }
  119. EXPORT_SYMBOL(il_rd_prph);
  120. void
  121. il_wr_prph(struct il_priv *il, u32 addr, u32 val)
  122. {
  123. unsigned long reg_flags;
  124. spin_lock_irqsave(&il->reg_lock, reg_flags);
  125. if (likely(_il_grab_nic_access(il))) {
  126. _il_wr_prph(il, addr, val);
  127. _il_release_nic_access(il);
  128. }
  129. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  130. }
  131. EXPORT_SYMBOL(il_wr_prph);
  132. u32
  133. il_read_targ_mem(struct il_priv *il, u32 addr)
  134. {
  135. unsigned long reg_flags;
  136. u32 value;
  137. spin_lock_irqsave(&il->reg_lock, reg_flags);
  138. _il_grab_nic_access(il);
  139. _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
  140. value = _il_rd(il, HBUS_TARG_MEM_RDAT);
  141. _il_release_nic_access(il);
  142. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  143. return value;
  144. }
  145. EXPORT_SYMBOL(il_read_targ_mem);
  146. void
  147. il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
  148. {
  149. unsigned long reg_flags;
  150. spin_lock_irqsave(&il->reg_lock, reg_flags);
  151. if (likely(_il_grab_nic_access(il))) {
  152. _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
  153. _il_wr(il, HBUS_TARG_MEM_WDAT, val);
  154. _il_release_nic_access(il);
  155. }
  156. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  157. }
  158. EXPORT_SYMBOL(il_write_targ_mem);
  159. const char *
  160. il_get_cmd_string(u8 cmd)
  161. {
  162. switch (cmd) {
  163. IL_CMD(N_ALIVE);
  164. IL_CMD(N_ERROR);
  165. IL_CMD(C_RXON);
  166. IL_CMD(C_RXON_ASSOC);
  167. IL_CMD(C_QOS_PARAM);
  168. IL_CMD(C_RXON_TIMING);
  169. IL_CMD(C_ADD_STA);
  170. IL_CMD(C_REM_STA);
  171. IL_CMD(C_WEPKEY);
  172. IL_CMD(N_3945_RX);
  173. IL_CMD(C_TX);
  174. IL_CMD(C_RATE_SCALE);
  175. IL_CMD(C_LEDS);
  176. IL_CMD(C_TX_LINK_QUALITY_CMD);
  177. IL_CMD(C_CHANNEL_SWITCH);
  178. IL_CMD(N_CHANNEL_SWITCH);
  179. IL_CMD(C_SPECTRUM_MEASUREMENT);
  180. IL_CMD(N_SPECTRUM_MEASUREMENT);
  181. IL_CMD(C_POWER_TBL);
  182. IL_CMD(N_PM_SLEEP);
  183. IL_CMD(N_PM_DEBUG_STATS);
  184. IL_CMD(C_SCAN);
  185. IL_CMD(C_SCAN_ABORT);
  186. IL_CMD(N_SCAN_START);
  187. IL_CMD(N_SCAN_RESULTS);
  188. IL_CMD(N_SCAN_COMPLETE);
  189. IL_CMD(N_BEACON);
  190. IL_CMD(C_TX_BEACON);
  191. IL_CMD(C_TX_PWR_TBL);
  192. IL_CMD(C_BT_CONFIG);
  193. IL_CMD(C_STATS);
  194. IL_CMD(N_STATS);
  195. IL_CMD(N_CARD_STATE);
  196. IL_CMD(N_MISSED_BEACONS);
  197. IL_CMD(C_CT_KILL_CONFIG);
  198. IL_CMD(C_SENSITIVITY);
  199. IL_CMD(C_PHY_CALIBRATION);
  200. IL_CMD(N_RX_PHY);
  201. IL_CMD(N_RX_MPDU);
  202. IL_CMD(N_RX);
  203. IL_CMD(N_COMPRESSED_BA);
  204. default:
  205. return "UNKNOWN";
  206. }
  207. }
  208. EXPORT_SYMBOL(il_get_cmd_string);
  209. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  210. static void
  211. il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
  212. struct il_rx_pkt *pkt)
  213. {
  214. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  215. IL_ERR("Bad return from %s (0x%08X)\n",
  216. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  217. return;
  218. }
  219. #ifdef CONFIG_IWLEGACY_DEBUG
  220. switch (cmd->hdr.cmd) {
  221. case C_TX_LINK_QUALITY_CMD:
  222. case C_SENSITIVITY:
  223. D_HC_DUMP("back from %s (0x%08X)\n",
  224. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  225. break;
  226. default:
  227. D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
  228. pkt->hdr.flags);
  229. }
  230. #endif
  231. }
  232. static int
  233. il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
  234. {
  235. int ret;
  236. BUG_ON(!(cmd->flags & CMD_ASYNC));
  237. /* An asynchronous command can not expect an SKB to be set. */
  238. BUG_ON(cmd->flags & CMD_WANT_SKB);
  239. /* Assign a generic callback if one is not provided */
  240. if (!cmd->callback)
  241. cmd->callback = il_generic_cmd_callback;
  242. if (test_bit(S_EXIT_PENDING, &il->status))
  243. return -EBUSY;
  244. ret = il_enqueue_hcmd(il, cmd);
  245. if (ret < 0) {
  246. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  247. il_get_cmd_string(cmd->id), ret);
  248. return ret;
  249. }
  250. return 0;
  251. }
  252. int
  253. il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
  254. {
  255. int cmd_idx;
  256. int ret;
  257. lockdep_assert_held(&il->mutex);
  258. BUG_ON(cmd->flags & CMD_ASYNC);
  259. /* A synchronous command can not have a callback set. */
  260. BUG_ON(cmd->callback);
  261. D_INFO("Attempting to send sync command %s\n",
  262. il_get_cmd_string(cmd->id));
  263. set_bit(S_HCMD_ACTIVE, &il->status);
  264. D_INFO("Setting HCMD_ACTIVE for command %s\n",
  265. il_get_cmd_string(cmd->id));
  266. cmd_idx = il_enqueue_hcmd(il, cmd);
  267. if (cmd_idx < 0) {
  268. ret = cmd_idx;
  269. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  270. il_get_cmd_string(cmd->id), ret);
  271. goto out;
  272. }
  273. ret = wait_event_timeout(il->wait_command_queue,
  274. !test_bit(S_HCMD_ACTIVE, &il->status),
  275. HOST_COMPLETE_TIMEOUT);
  276. if (!ret) {
  277. if (test_bit(S_HCMD_ACTIVE, &il->status)) {
  278. IL_ERR("Error sending %s: time out after %dms.\n",
  279. il_get_cmd_string(cmd->id),
  280. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  281. clear_bit(S_HCMD_ACTIVE, &il->status);
  282. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  283. il_get_cmd_string(cmd->id));
  284. ret = -ETIMEDOUT;
  285. goto cancel;
  286. }
  287. }
  288. if (test_bit(S_RFKILL, &il->status)) {
  289. IL_ERR("Command %s aborted: RF KILL Switch\n",
  290. il_get_cmd_string(cmd->id));
  291. ret = -ECANCELED;
  292. goto fail;
  293. }
  294. if (test_bit(S_FW_ERROR, &il->status)) {
  295. IL_ERR("Command %s failed: FW Error\n",
  296. il_get_cmd_string(cmd->id));
  297. ret = -EIO;
  298. goto fail;
  299. }
  300. if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
  301. IL_ERR("Error: Response NULL in '%s'\n",
  302. il_get_cmd_string(cmd->id));
  303. ret = -EIO;
  304. goto cancel;
  305. }
  306. ret = 0;
  307. goto out;
  308. cancel:
  309. if (cmd->flags & CMD_WANT_SKB) {
  310. /*
  311. * Cancel the CMD_WANT_SKB flag for the cmd in the
  312. * TX cmd queue. Otherwise in case the cmd comes
  313. * in later, it will possibly set an invalid
  314. * address (cmd->meta.source).
  315. */
  316. il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
  317. }
  318. fail:
  319. if (cmd->reply_page) {
  320. il_free_pages(il, cmd->reply_page);
  321. cmd->reply_page = 0;
  322. }
  323. out:
  324. return ret;
  325. }
  326. EXPORT_SYMBOL(il_send_cmd_sync);
  327. int
  328. il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
  329. {
  330. if (cmd->flags & CMD_ASYNC)
  331. return il_send_cmd_async(il, cmd);
  332. return il_send_cmd_sync(il, cmd);
  333. }
  334. EXPORT_SYMBOL(il_send_cmd);
  335. int
  336. il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
  337. {
  338. struct il_host_cmd cmd = {
  339. .id = id,
  340. .len = len,
  341. .data = data,
  342. };
  343. return il_send_cmd_sync(il, &cmd);
  344. }
  345. EXPORT_SYMBOL(il_send_cmd_pdu);
  346. int
  347. il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
  348. void (*callback) (struct il_priv *il,
  349. struct il_device_cmd *cmd,
  350. struct il_rx_pkt *pkt))
  351. {
  352. struct il_host_cmd cmd = {
  353. .id = id,
  354. .len = len,
  355. .data = data,
  356. };
  357. cmd.flags |= CMD_ASYNC;
  358. cmd.callback = callback;
  359. return il_send_cmd_async(il, &cmd);
  360. }
  361. EXPORT_SYMBOL(il_send_cmd_pdu_async);
  362. /* default: IL_LED_BLINK(0) using blinking idx table */
  363. static int led_mode;
  364. module_param(led_mode, int, 0444);
  365. MODULE_PARM_DESC(led_mode,
  366. "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
  367. /* Throughput OFF time(ms) ON time (ms)
  368. * >300 25 25
  369. * >200 to 300 40 40
  370. * >100 to 200 55 55
  371. * >70 to 100 65 65
  372. * >50 to 70 75 75
  373. * >20 to 50 85 85
  374. * >10 to 20 95 95
  375. * >5 to 10 110 110
  376. * >1 to 5 130 130
  377. * >0 to 1 167 167
  378. * <=0 SOLID ON
  379. */
  380. static const struct ieee80211_tpt_blink il_blink[] = {
  381. {.throughput = 0, .blink_time = 334},
  382. {.throughput = 1 * 1024 - 1, .blink_time = 260},
  383. {.throughput = 5 * 1024 - 1, .blink_time = 220},
  384. {.throughput = 10 * 1024 - 1, .blink_time = 190},
  385. {.throughput = 20 * 1024 - 1, .blink_time = 170},
  386. {.throughput = 50 * 1024 - 1, .blink_time = 150},
  387. {.throughput = 70 * 1024 - 1, .blink_time = 130},
  388. {.throughput = 100 * 1024 - 1, .blink_time = 110},
  389. {.throughput = 200 * 1024 - 1, .blink_time = 80},
  390. {.throughput = 300 * 1024 - 1, .blink_time = 50},
  391. };
  392. /*
  393. * Adjust led blink rate to compensate on a MAC Clock difference on every HW
  394. * Led blink rate analysis showed an average deviation of 0% on 3945,
  395. * 5% on 4965 HW.
  396. * Need to compensate on the led on/off time per HW according to the deviation
  397. * to achieve the desired led frequency
  398. * The calculation is: (100-averageDeviation)/100 * blinkTime
  399. * For code efficiency the calculation will be:
  400. * compensation = (100 - averageDeviation) * 64 / 100
  401. * NewBlinkTime = (compensation * BlinkTime) / 64
  402. */
  403. static inline u8
  404. il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
  405. {
  406. if (!compensation) {
  407. IL_ERR("undefined blink compensation: "
  408. "use pre-defined blinking time\n");
  409. return time;
  410. }
  411. return (u8) ((time * compensation) >> 6);
  412. }
  413. /* Set led pattern command */
  414. static int
  415. il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
  416. {
  417. struct il_led_cmd led_cmd = {
  418. .id = IL_LED_LINK,
  419. .interval = IL_DEF_LED_INTRVL
  420. };
  421. int ret;
  422. if (!test_bit(S_READY, &il->status))
  423. return -EBUSY;
  424. if (il->blink_on == on && il->blink_off == off)
  425. return 0;
  426. if (off == 0) {
  427. /* led is SOLID_ON */
  428. on = IL_LED_SOLID;
  429. }
  430. D_LED("Led blink time compensation=%u\n",
  431. il->cfg->led_compensation);
  432. led_cmd.on =
  433. il_blink_compensation(il, on,
  434. il->cfg->led_compensation);
  435. led_cmd.off =
  436. il_blink_compensation(il, off,
  437. il->cfg->led_compensation);
  438. ret = il->ops->send_led_cmd(il, &led_cmd);
  439. if (!ret) {
  440. il->blink_on = on;
  441. il->blink_off = off;
  442. }
  443. return ret;
  444. }
  445. static void
  446. il_led_brightness_set(struct led_classdev *led_cdev,
  447. enum led_brightness brightness)
  448. {
  449. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  450. unsigned long on = 0;
  451. if (brightness > 0)
  452. on = IL_LED_SOLID;
  453. il_led_cmd(il, on, 0);
  454. }
  455. static int
  456. il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
  457. unsigned long *delay_off)
  458. {
  459. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  460. return il_led_cmd(il, *delay_on, *delay_off);
  461. }
  462. void
  463. il_leds_init(struct il_priv *il)
  464. {
  465. int mode = led_mode;
  466. int ret;
  467. if (mode == IL_LED_DEFAULT)
  468. mode = il->cfg->led_mode;
  469. il->led.name =
  470. kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
  471. il->led.brightness_set = il_led_brightness_set;
  472. il->led.blink_set = il_led_blink_set;
  473. il->led.max_brightness = 1;
  474. switch (mode) {
  475. case IL_LED_DEFAULT:
  476. WARN_ON(1);
  477. break;
  478. case IL_LED_BLINK:
  479. il->led.default_trigger =
  480. ieee80211_create_tpt_led_trigger(il->hw,
  481. IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
  482. il_blink,
  483. ARRAY_SIZE(il_blink));
  484. break;
  485. case IL_LED_RF_STATE:
  486. il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
  487. break;
  488. }
  489. ret = led_classdev_register(&il->pci_dev->dev, &il->led);
  490. if (ret) {
  491. kfree(il->led.name);
  492. return;
  493. }
  494. il->led_registered = true;
  495. }
  496. EXPORT_SYMBOL(il_leds_init);
  497. void
  498. il_leds_exit(struct il_priv *il)
  499. {
  500. if (!il->led_registered)
  501. return;
  502. led_classdev_unregister(&il->led);
  503. kfree(il->led.name);
  504. }
  505. EXPORT_SYMBOL(il_leds_exit);
  506. /************************** EEPROM BANDS ****************************
  507. *
  508. * The il_eeprom_band definitions below provide the mapping from the
  509. * EEPROM contents to the specific channel number supported for each
  510. * band.
  511. *
  512. * For example, il_priv->eeprom.band_3_channels[4] from the band_3
  513. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  514. * The specific geography and calibration information for that channel
  515. * is contained in the eeprom map itself.
  516. *
  517. * During init, we copy the eeprom information and channel map
  518. * information into il->channel_info_24/52 and il->channel_map_24/52
  519. *
  520. * channel_map_24/52 provides the idx in the channel_info array for a
  521. * given channel. We have to have two separate maps as there is channel
  522. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  523. * band_2
  524. *
  525. * A value of 0xff stored in the channel_map indicates that the channel
  526. * is not supported by the hardware at all.
  527. *
  528. * A value of 0xfe in the channel_map indicates that the channel is not
  529. * valid for Tx with the current hardware. This means that
  530. * while the system can tune and receive on a given channel, it may not
  531. * be able to associate or transmit any frames on that
  532. * channel. There is no corresponding channel information for that
  533. * entry.
  534. *
  535. *********************************************************************/
  536. /* 2.4 GHz */
  537. const u8 il_eeprom_band_1[14] = {
  538. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  539. };
  540. /* 5.2 GHz bands */
  541. static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
  542. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  543. };
  544. static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
  545. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  546. };
  547. static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
  548. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  549. };
  550. static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
  551. 145, 149, 153, 157, 161, 165
  552. };
  553. static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
  554. 1, 2, 3, 4, 5, 6, 7
  555. };
  556. static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
  557. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  558. };
  559. /******************************************************************************
  560. *
  561. * EEPROM related functions
  562. *
  563. ******************************************************************************/
  564. static int
  565. il_eeprom_verify_signature(struct il_priv *il)
  566. {
  567. u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
  568. int ret = 0;
  569. D_EEPROM("EEPROM signature=0x%08x\n", gp);
  570. switch (gp) {
  571. case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
  572. case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
  573. break;
  574. default:
  575. IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
  576. ret = -ENOENT;
  577. break;
  578. }
  579. return ret;
  580. }
  581. const u8 *
  582. il_eeprom_query_addr(const struct il_priv *il, size_t offset)
  583. {
  584. BUG_ON(offset >= il->cfg->eeprom_size);
  585. return &il->eeprom[offset];
  586. }
  587. EXPORT_SYMBOL(il_eeprom_query_addr);
  588. u16
  589. il_eeprom_query16(const struct il_priv *il, size_t offset)
  590. {
  591. if (!il->eeprom)
  592. return 0;
  593. return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
  594. }
  595. EXPORT_SYMBOL(il_eeprom_query16);
  596. /*
  597. * il_eeprom_init - read EEPROM contents
  598. *
  599. * Load the EEPROM contents from adapter into il->eeprom
  600. *
  601. * NOTE: This routine uses the non-debug IO access functions.
  602. */
  603. int
  604. il_eeprom_init(struct il_priv *il)
  605. {
  606. __le16 *e;
  607. u32 gp = _il_rd(il, CSR_EEPROM_GP);
  608. int sz;
  609. int ret;
  610. int addr;
  611. /* allocate eeprom */
  612. sz = il->cfg->eeprom_size;
  613. D_EEPROM("NVM size = %d\n", sz);
  614. il->eeprom = kzalloc(sz, GFP_KERNEL);
  615. if (!il->eeprom)
  616. return -ENOMEM;
  617. e = (__le16 *) il->eeprom;
  618. il->ops->apm_init(il);
  619. ret = il_eeprom_verify_signature(il);
  620. if (ret < 0) {
  621. IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  622. ret = -ENOENT;
  623. goto err;
  624. }
  625. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  626. ret = il->ops->eeprom_acquire_semaphore(il);
  627. if (ret < 0) {
  628. IL_ERR("Failed to acquire EEPROM semaphore.\n");
  629. ret = -ENOENT;
  630. goto err;
  631. }
  632. /* eeprom is an array of 16bit values */
  633. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  634. u32 r;
  635. _il_wr(il, CSR_EEPROM_REG,
  636. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  637. ret =
  638. _il_poll_bit(il, CSR_EEPROM_REG,
  639. CSR_EEPROM_REG_READ_VALID_MSK,
  640. CSR_EEPROM_REG_READ_VALID_MSK,
  641. IL_EEPROM_ACCESS_TIMEOUT);
  642. if (ret < 0) {
  643. IL_ERR("Time out reading EEPROM[%d]\n", addr);
  644. goto done;
  645. }
  646. r = _il_rd(il, CSR_EEPROM_REG);
  647. e[addr / 2] = cpu_to_le16(r >> 16);
  648. }
  649. D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
  650. il_eeprom_query16(il, EEPROM_VERSION));
  651. ret = 0;
  652. done:
  653. il->ops->eeprom_release_semaphore(il);
  654. err:
  655. if (ret)
  656. il_eeprom_free(il);
  657. /* Reset chip to save power until we load uCode during "up". */
  658. il_apm_stop(il);
  659. return ret;
  660. }
  661. EXPORT_SYMBOL(il_eeprom_init);
  662. void
  663. il_eeprom_free(struct il_priv *il)
  664. {
  665. kfree(il->eeprom);
  666. il->eeprom = NULL;
  667. }
  668. EXPORT_SYMBOL(il_eeprom_free);
  669. static void
  670. il_init_band_reference(const struct il_priv *il, int eep_band,
  671. int *eeprom_ch_count,
  672. const struct il_eeprom_channel **eeprom_ch_info,
  673. const u8 **eeprom_ch_idx)
  674. {
  675. u32 offset = il->cfg->regulatory_bands[eep_band - 1];
  676. switch (eep_band) {
  677. case 1: /* 2.4GHz band */
  678. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
  679. *eeprom_ch_info =
  680. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  681. offset);
  682. *eeprom_ch_idx = il_eeprom_band_1;
  683. break;
  684. case 2: /* 4.9GHz band */
  685. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
  686. *eeprom_ch_info =
  687. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  688. offset);
  689. *eeprom_ch_idx = il_eeprom_band_2;
  690. break;
  691. case 3: /* 5.2GHz band */
  692. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
  693. *eeprom_ch_info =
  694. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  695. offset);
  696. *eeprom_ch_idx = il_eeprom_band_3;
  697. break;
  698. case 4: /* 5.5GHz band */
  699. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
  700. *eeprom_ch_info =
  701. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  702. offset);
  703. *eeprom_ch_idx = il_eeprom_band_4;
  704. break;
  705. case 5: /* 5.7GHz band */
  706. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
  707. *eeprom_ch_info =
  708. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  709. offset);
  710. *eeprom_ch_idx = il_eeprom_band_5;
  711. break;
  712. case 6: /* 2.4GHz ht40 channels */
  713. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
  714. *eeprom_ch_info =
  715. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  716. offset);
  717. *eeprom_ch_idx = il_eeprom_band_6;
  718. break;
  719. case 7: /* 5 GHz ht40 channels */
  720. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
  721. *eeprom_ch_info =
  722. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  723. offset);
  724. *eeprom_ch_idx = il_eeprom_band_7;
  725. break;
  726. default:
  727. BUG();
  728. }
  729. }
  730. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  731. ? # x " " : "")
  732. /*
  733. * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
  734. *
  735. * Does not set up a command, or touch hardware.
  736. */
  737. static int
  738. il_mod_ht40_chan_info(struct il_priv *il, enum nl80211_band band, u16 channel,
  739. const struct il_eeprom_channel *eeprom_ch,
  740. u8 clear_ht40_extension_channel)
  741. {
  742. struct il_channel_info *ch_info;
  743. ch_info =
  744. (struct il_channel_info *)il_get_channel_info(il, band, channel);
  745. if (!il_is_channel_valid(ch_info))
  746. return -1;
  747. D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
  748. " Ad-Hoc %ssupported\n", ch_info->channel,
  749. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  750. CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
  751. CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
  752. CHECK_AND_PRINT(DFS), eeprom_ch->flags,
  753. eeprom_ch->max_power_avg,
  754. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
  755. !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
  756. ch_info->ht40_eeprom = *eeprom_ch;
  757. ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
  758. ch_info->ht40_flags = eeprom_ch->flags;
  759. if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
  760. ch_info->ht40_extension_channel &=
  761. ~clear_ht40_extension_channel;
  762. return 0;
  763. }
  764. #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  765. ? # x " " : "")
  766. /*
  767. * il_init_channel_map - Set up driver's info for all possible channels
  768. */
  769. int
  770. il_init_channel_map(struct il_priv *il)
  771. {
  772. int eeprom_ch_count = 0;
  773. const u8 *eeprom_ch_idx = NULL;
  774. const struct il_eeprom_channel *eeprom_ch_info = NULL;
  775. int band, ch;
  776. struct il_channel_info *ch_info;
  777. if (il->channel_count) {
  778. D_EEPROM("Channel map already initialized.\n");
  779. return 0;
  780. }
  781. D_EEPROM("Initializing regulatory info from EEPROM\n");
  782. il->channel_count =
  783. ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
  784. ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
  785. ARRAY_SIZE(il_eeprom_band_5);
  786. D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
  787. il->channel_info =
  788. kcalloc(il->channel_count, sizeof(struct il_channel_info),
  789. GFP_KERNEL);
  790. if (!il->channel_info) {
  791. IL_ERR("Could not allocate channel_info\n");
  792. il->channel_count = 0;
  793. return -ENOMEM;
  794. }
  795. ch_info = il->channel_info;
  796. /* Loop through the 5 EEPROM bands adding them in order to the
  797. * channel map we maintain (that contains additional information than
  798. * what just in the EEPROM) */
  799. for (band = 1; band <= 5; band++) {
  800. il_init_band_reference(il, band, &eeprom_ch_count,
  801. &eeprom_ch_info, &eeprom_ch_idx);
  802. /* Loop through each band adding each of the channels */
  803. for (ch = 0; ch < eeprom_ch_count; ch++) {
  804. ch_info->channel = eeprom_ch_idx[ch];
  805. ch_info->band =
  806. (band ==
  807. 1) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  808. /* permanently store EEPROM's channel regulatory flags
  809. * and max power in channel info database. */
  810. ch_info->eeprom = eeprom_ch_info[ch];
  811. /* Copy the run-time flags so they are there even on
  812. * invalid channels */
  813. ch_info->flags = eeprom_ch_info[ch].flags;
  814. /* First write that ht40 is not enabled, and then enable
  815. * one by one */
  816. ch_info->ht40_extension_channel =
  817. IEEE80211_CHAN_NO_HT40;
  818. if (!(il_is_channel_valid(ch_info))) {
  819. D_EEPROM("Ch. %d Flags %x [%sGHz] - "
  820. "No traffic\n", ch_info->channel,
  821. ch_info->flags,
  822. il_is_channel_a_band(ch_info) ? "5.2" :
  823. "2.4");
  824. ch_info++;
  825. continue;
  826. }
  827. /* Initialize regulatory-based run-time data */
  828. ch_info->max_power_avg = ch_info->curr_txpow =
  829. eeprom_ch_info[ch].max_power_avg;
  830. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  831. ch_info->min_power = 0;
  832. D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
  833. " Ad-Hoc %ssupported\n", ch_info->channel,
  834. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  835. CHECK_AND_PRINT_I(VALID),
  836. CHECK_AND_PRINT_I(IBSS),
  837. CHECK_AND_PRINT_I(ACTIVE),
  838. CHECK_AND_PRINT_I(RADAR),
  839. CHECK_AND_PRINT_I(WIDE),
  840. CHECK_AND_PRINT_I(DFS),
  841. eeprom_ch_info[ch].flags,
  842. eeprom_ch_info[ch].max_power_avg,
  843. ((eeprom_ch_info[ch].
  844. flags & EEPROM_CHANNEL_IBSS) &&
  845. !(eeprom_ch_info[ch].
  846. flags & EEPROM_CHANNEL_RADAR)) ? "" :
  847. "not ");
  848. ch_info++;
  849. }
  850. }
  851. /* Check if we do have HT40 channels */
  852. if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
  853. il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
  854. return 0;
  855. /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
  856. for (band = 6; band <= 7; band++) {
  857. enum nl80211_band ieeeband;
  858. il_init_band_reference(il, band, &eeprom_ch_count,
  859. &eeprom_ch_info, &eeprom_ch_idx);
  860. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  861. ieeeband =
  862. (band == 6) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  863. /* Loop through each band adding each of the channels */
  864. for (ch = 0; ch < eeprom_ch_count; ch++) {
  865. /* Set up driver's info for lower half */
  866. il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
  867. &eeprom_ch_info[ch],
  868. IEEE80211_CHAN_NO_HT40PLUS);
  869. /* Set up driver's info for upper half */
  870. il_mod_ht40_chan_info(il, ieeeband,
  871. eeprom_ch_idx[ch] + 4,
  872. &eeprom_ch_info[ch],
  873. IEEE80211_CHAN_NO_HT40MINUS);
  874. }
  875. }
  876. return 0;
  877. }
  878. EXPORT_SYMBOL(il_init_channel_map);
  879. /*
  880. * il_free_channel_map - undo allocations in il_init_channel_map
  881. */
  882. void
  883. il_free_channel_map(struct il_priv *il)
  884. {
  885. kfree(il->channel_info);
  886. il->channel_count = 0;
  887. }
  888. EXPORT_SYMBOL(il_free_channel_map);
  889. /*
  890. * il_get_channel_info - Find driver's ilate channel info
  891. *
  892. * Based on band and channel number.
  893. */
  894. const struct il_channel_info *
  895. il_get_channel_info(const struct il_priv *il, enum nl80211_band band,
  896. u16 channel)
  897. {
  898. int i;
  899. switch (band) {
  900. case NL80211_BAND_5GHZ:
  901. for (i = 14; i < il->channel_count; i++) {
  902. if (il->channel_info[i].channel == channel)
  903. return &il->channel_info[i];
  904. }
  905. break;
  906. case NL80211_BAND_2GHZ:
  907. if (channel >= 1 && channel <= 14)
  908. return &il->channel_info[channel - 1];
  909. break;
  910. default:
  911. BUG();
  912. }
  913. return NULL;
  914. }
  915. EXPORT_SYMBOL(il_get_channel_info);
  916. /*
  917. * Setting power level allows the card to go to sleep when not busy.
  918. *
  919. * We calculate a sleep command based on the required latency, which
  920. * we get from mac80211.
  921. */
  922. #define SLP_VEC(X0, X1, X2, X3, X4) { \
  923. cpu_to_le32(X0), \
  924. cpu_to_le32(X1), \
  925. cpu_to_le32(X2), \
  926. cpu_to_le32(X3), \
  927. cpu_to_le32(X4) \
  928. }
  929. static void
  930. il_build_powertable_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
  931. {
  932. static const __le32 interval[3][IL_POWER_VEC_SIZE] = {
  933. SLP_VEC(2, 2, 4, 6, 0xFF),
  934. SLP_VEC(2, 4, 7, 10, 10),
  935. SLP_VEC(4, 7, 10, 10, 0xFF)
  936. };
  937. int i, dtim_period, no_dtim;
  938. u32 max_sleep;
  939. bool skip;
  940. memset(cmd, 0, sizeof(*cmd));
  941. if (il->power_data.pci_pm)
  942. cmd->flags |= IL_POWER_PCI_PM_MSK;
  943. /* if no Power Save, we are done */
  944. if (il->power_data.ps_disabled)
  945. return;
  946. cmd->flags = IL_POWER_DRIVER_ALLOW_SLEEP_MSK;
  947. cmd->keep_alive_seconds = 0;
  948. cmd->debug_flags = 0;
  949. cmd->rx_data_timeout = cpu_to_le32(25 * 1024);
  950. cmd->tx_data_timeout = cpu_to_le32(25 * 1024);
  951. cmd->keep_alive_beacons = 0;
  952. dtim_period = il->vif ? il->vif->bss_conf.dtim_period : 0;
  953. if (dtim_period <= 2) {
  954. memcpy(cmd->sleep_interval, interval[0], sizeof(interval[0]));
  955. no_dtim = 2;
  956. } else if (dtim_period <= 10) {
  957. memcpy(cmd->sleep_interval, interval[1], sizeof(interval[1]));
  958. no_dtim = 2;
  959. } else {
  960. memcpy(cmd->sleep_interval, interval[2], sizeof(interval[2]));
  961. no_dtim = 0;
  962. }
  963. if (dtim_period == 0) {
  964. dtim_period = 1;
  965. skip = false;
  966. } else {
  967. skip = !!no_dtim;
  968. }
  969. if (skip) {
  970. __le32 tmp = cmd->sleep_interval[IL_POWER_VEC_SIZE - 1];
  971. max_sleep = le32_to_cpu(tmp);
  972. if (max_sleep == 0xFF)
  973. max_sleep = dtim_period * (skip + 1);
  974. else if (max_sleep > dtim_period)
  975. max_sleep = (max_sleep / dtim_period) * dtim_period;
  976. cmd->flags |= IL_POWER_SLEEP_OVER_DTIM_MSK;
  977. } else {
  978. max_sleep = dtim_period;
  979. cmd->flags &= ~IL_POWER_SLEEP_OVER_DTIM_MSK;
  980. }
  981. for (i = 0; i < IL_POWER_VEC_SIZE; i++)
  982. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  983. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  984. }
  985. static int
  986. il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
  987. {
  988. D_POWER("Sending power/sleep command\n");
  989. D_POWER("Flags value = 0x%08X\n", cmd->flags);
  990. D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  991. D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  992. D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  993. le32_to_cpu(cmd->sleep_interval[0]),
  994. le32_to_cpu(cmd->sleep_interval[1]),
  995. le32_to_cpu(cmd->sleep_interval[2]),
  996. le32_to_cpu(cmd->sleep_interval[3]),
  997. le32_to_cpu(cmd->sleep_interval[4]));
  998. return il_send_cmd_pdu(il, C_POWER_TBL,
  999. sizeof(struct il_powertable_cmd), cmd);
  1000. }
  1001. static int
  1002. il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
  1003. {
  1004. int ret;
  1005. bool update_chains;
  1006. lockdep_assert_held(&il->mutex);
  1007. /* Don't update the RX chain when chain noise calibration is running */
  1008. update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
  1009. il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
  1010. if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
  1011. return 0;
  1012. if (!il_is_ready_rf(il))
  1013. return -EIO;
  1014. /* scan complete use sleep_power_next, need to be updated */
  1015. memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
  1016. if (test_bit(S_SCANNING, &il->status) && !force) {
  1017. D_INFO("Defer power set mode while scanning\n");
  1018. return 0;
  1019. }
  1020. if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
  1021. set_bit(S_POWER_PMI, &il->status);
  1022. ret = il_set_power(il, cmd);
  1023. if (!ret) {
  1024. if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
  1025. clear_bit(S_POWER_PMI, &il->status);
  1026. if (il->ops->update_chain_flags && update_chains)
  1027. il->ops->update_chain_flags(il);
  1028. else if (il->ops->update_chain_flags)
  1029. D_POWER("Cannot update the power, chain noise "
  1030. "calibration running: %d\n",
  1031. il->chain_noise_data.state);
  1032. memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
  1033. } else
  1034. IL_ERR("set power fail, ret = %d", ret);
  1035. return ret;
  1036. }
  1037. int
  1038. il_power_update_mode(struct il_priv *il, bool force)
  1039. {
  1040. struct il_powertable_cmd cmd;
  1041. il_build_powertable_cmd(il, &cmd);
  1042. return il_power_set_mode(il, &cmd, force);
  1043. }
  1044. EXPORT_SYMBOL(il_power_update_mode);
  1045. /* initialize to default */
  1046. void
  1047. il_power_initialize(struct il_priv *il)
  1048. {
  1049. u16 lctl;
  1050. pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  1051. il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
  1052. il->power_data.debug_sleep_level_override = -1;
  1053. memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
  1054. }
  1055. EXPORT_SYMBOL(il_power_initialize);
  1056. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  1057. * sending probe req. This should be set long enough to hear probe responses
  1058. * from more than one AP. */
  1059. #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  1060. #define IL_ACTIVE_DWELL_TIME_52 (20)
  1061. #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  1062. #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  1063. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  1064. * Must be set longer than active dwell time.
  1065. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  1066. #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  1067. #define IL_PASSIVE_DWELL_TIME_52 (10)
  1068. #define IL_PASSIVE_DWELL_BASE (100)
  1069. #define IL_CHANNEL_TUNE_TIME 5
  1070. static int
  1071. il_send_scan_abort(struct il_priv *il)
  1072. {
  1073. int ret;
  1074. struct il_rx_pkt *pkt;
  1075. struct il_host_cmd cmd = {
  1076. .id = C_SCAN_ABORT,
  1077. .flags = CMD_WANT_SKB,
  1078. };
  1079. /* Exit instantly with error when device is not ready
  1080. * to receive scan abort command or it does not perform
  1081. * hardware scan currently */
  1082. if (!test_bit(S_READY, &il->status) ||
  1083. !test_bit(S_GEO_CONFIGURED, &il->status) ||
  1084. !test_bit(S_SCAN_HW, &il->status) ||
  1085. test_bit(S_FW_ERROR, &il->status) ||
  1086. test_bit(S_EXIT_PENDING, &il->status))
  1087. return -EIO;
  1088. ret = il_send_cmd_sync(il, &cmd);
  1089. if (ret)
  1090. return ret;
  1091. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1092. if (pkt->u.status != CAN_ABORT_STATUS) {
  1093. /* The scan abort will return 1 for success or
  1094. * 2 for "failure". A failure condition can be
  1095. * due to simply not being in an active scan which
  1096. * can occur if we send the scan abort before we
  1097. * the microcode has notified us that a scan is
  1098. * completed. */
  1099. D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
  1100. ret = -EIO;
  1101. }
  1102. il_free_pages(il, cmd.reply_page);
  1103. return ret;
  1104. }
  1105. static void
  1106. il_complete_scan(struct il_priv *il, bool aborted)
  1107. {
  1108. struct cfg80211_scan_info info = {
  1109. .aborted = aborted,
  1110. };
  1111. /* check if scan was requested from mac80211 */
  1112. if (il->scan_request) {
  1113. D_SCAN("Complete scan in mac80211\n");
  1114. ieee80211_scan_completed(il->hw, &info);
  1115. }
  1116. il->scan_vif = NULL;
  1117. il->scan_request = NULL;
  1118. }
  1119. void
  1120. il_force_scan_end(struct il_priv *il)
  1121. {
  1122. lockdep_assert_held(&il->mutex);
  1123. if (!test_bit(S_SCANNING, &il->status)) {
  1124. D_SCAN("Forcing scan end while not scanning\n");
  1125. return;
  1126. }
  1127. D_SCAN("Forcing scan end\n");
  1128. clear_bit(S_SCANNING, &il->status);
  1129. clear_bit(S_SCAN_HW, &il->status);
  1130. clear_bit(S_SCAN_ABORTING, &il->status);
  1131. il_complete_scan(il, true);
  1132. }
  1133. static void
  1134. il_do_scan_abort(struct il_priv *il)
  1135. {
  1136. int ret;
  1137. lockdep_assert_held(&il->mutex);
  1138. if (!test_bit(S_SCANNING, &il->status)) {
  1139. D_SCAN("Not performing scan to abort\n");
  1140. return;
  1141. }
  1142. if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
  1143. D_SCAN("Scan abort in progress\n");
  1144. return;
  1145. }
  1146. ret = il_send_scan_abort(il);
  1147. if (ret) {
  1148. D_SCAN("Send scan abort failed %d\n", ret);
  1149. il_force_scan_end(il);
  1150. } else
  1151. D_SCAN("Successfully send scan abort\n");
  1152. }
  1153. /*
  1154. * il_scan_cancel - Cancel any currently executing HW scan
  1155. */
  1156. int
  1157. il_scan_cancel(struct il_priv *il)
  1158. {
  1159. D_SCAN("Queuing abort scan\n");
  1160. queue_work(il->workqueue, &il->abort_scan);
  1161. return 0;
  1162. }
  1163. EXPORT_SYMBOL(il_scan_cancel);
  1164. /*
  1165. * il_scan_cancel_timeout - Cancel any currently executing HW scan
  1166. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1167. *
  1168. */
  1169. int
  1170. il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
  1171. {
  1172. unsigned long timeout = jiffies + msecs_to_jiffies(ms);
  1173. lockdep_assert_held(&il->mutex);
  1174. D_SCAN("Scan cancel timeout\n");
  1175. il_do_scan_abort(il);
  1176. while (time_before_eq(jiffies, timeout)) {
  1177. if (!test_bit(S_SCAN_HW, &il->status))
  1178. break;
  1179. msleep(20);
  1180. }
  1181. return test_bit(S_SCAN_HW, &il->status);
  1182. }
  1183. EXPORT_SYMBOL(il_scan_cancel_timeout);
  1184. /* Service response to C_SCAN (0x80) */
  1185. static void
  1186. il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
  1187. {
  1188. #ifdef CONFIG_IWLEGACY_DEBUG
  1189. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1190. struct il_scanreq_notification *notif =
  1191. (struct il_scanreq_notification *)pkt->u.raw;
  1192. D_SCAN("Scan request status = 0x%x\n", notif->status);
  1193. #endif
  1194. }
  1195. /* Service N_SCAN_START (0x82) */
  1196. static void
  1197. il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
  1198. {
  1199. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1200. struct il_scanstart_notification *notif =
  1201. (struct il_scanstart_notification *)pkt->u.raw;
  1202. il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  1203. D_SCAN("Scan start: " "%d [802.11%s] "
  1204. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
  1205. notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
  1206. le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
  1207. }
  1208. /* Service N_SCAN_RESULTS (0x83) */
  1209. static void
  1210. il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
  1211. {
  1212. #ifdef CONFIG_IWLEGACY_DEBUG
  1213. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1214. struct il_scanresults_notification *notif =
  1215. (struct il_scanresults_notification *)pkt->u.raw;
  1216. D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
  1217. "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
  1218. le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
  1219. le32_to_cpu(notif->stats[0]),
  1220. le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
  1221. #endif
  1222. }
  1223. /* Service N_SCAN_COMPLETE (0x84) */
  1224. static void
  1225. il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
  1226. {
  1227. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1228. struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  1229. D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  1230. scan_notif->scanned_channels, scan_notif->tsf_low,
  1231. scan_notif->tsf_high, scan_notif->status);
  1232. /* The HW is no longer scanning */
  1233. clear_bit(S_SCAN_HW, &il->status);
  1234. D_SCAN("Scan on %sGHz took %dms\n",
  1235. (il->scan_band == NL80211_BAND_2GHZ) ? "2.4" : "5.2",
  1236. jiffies_to_msecs(jiffies - il->scan_start));
  1237. queue_work(il->workqueue, &il->scan_completed);
  1238. }
  1239. void
  1240. il_setup_rx_scan_handlers(struct il_priv *il)
  1241. {
  1242. /* scan handlers */
  1243. il->handlers[C_SCAN] = il_hdl_scan;
  1244. il->handlers[N_SCAN_START] = il_hdl_scan_start;
  1245. il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
  1246. il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
  1247. }
  1248. EXPORT_SYMBOL(il_setup_rx_scan_handlers);
  1249. u16
  1250. il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band,
  1251. u8 n_probes)
  1252. {
  1253. if (band == NL80211_BAND_5GHZ)
  1254. return IL_ACTIVE_DWELL_TIME_52 +
  1255. IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  1256. else
  1257. return IL_ACTIVE_DWELL_TIME_24 +
  1258. IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  1259. }
  1260. EXPORT_SYMBOL(il_get_active_dwell_time);
  1261. u16
  1262. il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band,
  1263. struct ieee80211_vif *vif)
  1264. {
  1265. u16 value;
  1266. u16 passive =
  1267. (band ==
  1268. NL80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
  1269. IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
  1270. IL_PASSIVE_DWELL_TIME_52;
  1271. if (il_is_any_associated(il)) {
  1272. /*
  1273. * If we're associated, we clamp the maximum passive
  1274. * dwell time to be 98% of the smallest beacon interval
  1275. * (minus 2 * channel tune time)
  1276. */
  1277. value = il->vif ? il->vif->bss_conf.beacon_int : 0;
  1278. if (value > IL_PASSIVE_DWELL_BASE || !value)
  1279. value = IL_PASSIVE_DWELL_BASE;
  1280. value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
  1281. passive = min(value, passive);
  1282. }
  1283. return passive;
  1284. }
  1285. EXPORT_SYMBOL(il_get_passive_dwell_time);
  1286. void
  1287. il_init_scan_params(struct il_priv *il)
  1288. {
  1289. u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
  1290. if (!il->scan_tx_ant[NL80211_BAND_5GHZ])
  1291. il->scan_tx_ant[NL80211_BAND_5GHZ] = ant_idx;
  1292. if (!il->scan_tx_ant[NL80211_BAND_2GHZ])
  1293. il->scan_tx_ant[NL80211_BAND_2GHZ] = ant_idx;
  1294. }
  1295. EXPORT_SYMBOL(il_init_scan_params);
  1296. static int
  1297. il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
  1298. {
  1299. int ret;
  1300. lockdep_assert_held(&il->mutex);
  1301. cancel_delayed_work(&il->scan_check);
  1302. if (!il_is_ready_rf(il)) {
  1303. IL_WARN("Request scan called when driver not ready.\n");
  1304. return -EIO;
  1305. }
  1306. if (test_bit(S_SCAN_HW, &il->status)) {
  1307. D_SCAN("Multiple concurrent scan requests in parallel.\n");
  1308. return -EBUSY;
  1309. }
  1310. if (test_bit(S_SCAN_ABORTING, &il->status)) {
  1311. D_SCAN("Scan request while abort pending.\n");
  1312. return -EBUSY;
  1313. }
  1314. D_SCAN("Starting scan...\n");
  1315. set_bit(S_SCANNING, &il->status);
  1316. il->scan_start = jiffies;
  1317. ret = il->ops->request_scan(il, vif);
  1318. if (ret) {
  1319. clear_bit(S_SCANNING, &il->status);
  1320. return ret;
  1321. }
  1322. queue_delayed_work(il->workqueue, &il->scan_check,
  1323. IL_SCAN_CHECK_WATCHDOG);
  1324. return 0;
  1325. }
  1326. int
  1327. il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1328. struct ieee80211_scan_request *hw_req)
  1329. {
  1330. struct cfg80211_scan_request *req = &hw_req->req;
  1331. struct il_priv *il = hw->priv;
  1332. int ret;
  1333. if (req->n_channels == 0) {
  1334. IL_ERR("Can not scan on no channels.\n");
  1335. return -EINVAL;
  1336. }
  1337. mutex_lock(&il->mutex);
  1338. D_MAC80211("enter\n");
  1339. if (test_bit(S_SCANNING, &il->status)) {
  1340. D_SCAN("Scan already in progress.\n");
  1341. ret = -EAGAIN;
  1342. goto out_unlock;
  1343. }
  1344. /* mac80211 will only ask for one band at a time */
  1345. il->scan_request = req;
  1346. il->scan_vif = vif;
  1347. il->scan_band = req->channels[0]->band;
  1348. ret = il_scan_initiate(il, vif);
  1349. out_unlock:
  1350. D_MAC80211("leave ret %d\n", ret);
  1351. mutex_unlock(&il->mutex);
  1352. return ret;
  1353. }
  1354. EXPORT_SYMBOL(il_mac_hw_scan);
  1355. static void
  1356. il_bg_scan_check(struct work_struct *data)
  1357. {
  1358. struct il_priv *il =
  1359. container_of(data, struct il_priv, scan_check.work);
  1360. D_SCAN("Scan check work\n");
  1361. /* Since we are here firmware does not finish scan and
  1362. * most likely is in bad shape, so we don't bother to
  1363. * send abort command, just force scan complete to mac80211 */
  1364. mutex_lock(&il->mutex);
  1365. il_force_scan_end(il);
  1366. mutex_unlock(&il->mutex);
  1367. }
  1368. /*
  1369. * il_fill_probe_req - fill in all required fields and IE for probe request
  1370. */
  1371. u16
  1372. il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
  1373. const u8 *ta, const u8 *ies, int ie_len, int left)
  1374. {
  1375. int len = 0;
  1376. u8 *pos = NULL;
  1377. /* Make sure there is enough space for the probe request,
  1378. * two mandatory IEs and the data */
  1379. left -= 24;
  1380. if (left < 0)
  1381. return 0;
  1382. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1383. eth_broadcast_addr(frame->da);
  1384. memcpy(frame->sa, ta, ETH_ALEN);
  1385. eth_broadcast_addr(frame->bssid);
  1386. frame->seq_ctrl = 0;
  1387. len += 24;
  1388. /* ...next IE... */
  1389. pos = &frame->u.probe_req.variable[0];
  1390. /* fill in our indirect SSID IE */
  1391. left -= 2;
  1392. if (left < 0)
  1393. return 0;
  1394. *pos++ = WLAN_EID_SSID;
  1395. *pos++ = 0;
  1396. len += 2;
  1397. if (WARN_ON(left < ie_len))
  1398. return len;
  1399. if (ies && ie_len) {
  1400. memcpy(pos, ies, ie_len);
  1401. len += ie_len;
  1402. }
  1403. return (u16) len;
  1404. }
  1405. EXPORT_SYMBOL(il_fill_probe_req);
  1406. static void
  1407. il_bg_abort_scan(struct work_struct *work)
  1408. {
  1409. struct il_priv *il = container_of(work, struct il_priv, abort_scan);
  1410. D_SCAN("Abort scan work\n");
  1411. /* We keep scan_check work queued in case when firmware will not
  1412. * report back scan completed notification */
  1413. mutex_lock(&il->mutex);
  1414. il_scan_cancel_timeout(il, 200);
  1415. mutex_unlock(&il->mutex);
  1416. }
  1417. static void
  1418. il_bg_scan_completed(struct work_struct *work)
  1419. {
  1420. struct il_priv *il = container_of(work, struct il_priv, scan_completed);
  1421. bool aborted;
  1422. D_SCAN("Completed scan.\n");
  1423. cancel_delayed_work(&il->scan_check);
  1424. mutex_lock(&il->mutex);
  1425. aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
  1426. if (aborted)
  1427. D_SCAN("Aborted scan completed.\n");
  1428. if (!test_and_clear_bit(S_SCANNING, &il->status)) {
  1429. D_SCAN("Scan already completed.\n");
  1430. goto out_settings;
  1431. }
  1432. il_complete_scan(il, aborted);
  1433. out_settings:
  1434. /* Can we still talk to firmware ? */
  1435. if (!il_is_ready_rf(il))
  1436. goto out;
  1437. /*
  1438. * We do not commit power settings while scan is pending,
  1439. * do it now if the settings changed.
  1440. */
  1441. il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
  1442. il_set_tx_power(il, il->tx_power_next, false);
  1443. il->ops->post_scan(il);
  1444. out:
  1445. mutex_unlock(&il->mutex);
  1446. }
  1447. void
  1448. il_setup_scan_deferred_work(struct il_priv *il)
  1449. {
  1450. INIT_WORK(&il->scan_completed, il_bg_scan_completed);
  1451. INIT_WORK(&il->abort_scan, il_bg_abort_scan);
  1452. INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
  1453. }
  1454. EXPORT_SYMBOL(il_setup_scan_deferred_work);
  1455. void
  1456. il_cancel_scan_deferred_work(struct il_priv *il)
  1457. {
  1458. cancel_work_sync(&il->abort_scan);
  1459. cancel_work_sync(&il->scan_completed);
  1460. if (cancel_delayed_work_sync(&il->scan_check)) {
  1461. mutex_lock(&il->mutex);
  1462. il_force_scan_end(il);
  1463. mutex_unlock(&il->mutex);
  1464. }
  1465. }
  1466. EXPORT_SYMBOL(il_cancel_scan_deferred_work);
  1467. /* il->sta_lock must be held */
  1468. static void
  1469. il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
  1470. {
  1471. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
  1472. IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
  1473. sta_id, il->stations[sta_id].sta.sta.addr);
  1474. if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
  1475. D_ASSOC("STA id %u addr %pM already present"
  1476. " in uCode (according to driver)\n", sta_id,
  1477. il->stations[sta_id].sta.sta.addr);
  1478. } else {
  1479. il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
  1480. D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
  1481. il->stations[sta_id].sta.sta.addr);
  1482. }
  1483. }
  1484. static int
  1485. il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
  1486. struct il_rx_pkt *pkt, bool sync)
  1487. {
  1488. u8 sta_id = addsta->sta.sta_id;
  1489. unsigned long flags;
  1490. int ret = -EIO;
  1491. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1492. IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
  1493. return ret;
  1494. }
  1495. D_INFO("Processing response for adding station %u\n", sta_id);
  1496. spin_lock_irqsave(&il->sta_lock, flags);
  1497. switch (pkt->u.add_sta.status) {
  1498. case ADD_STA_SUCCESS_MSK:
  1499. D_INFO("C_ADD_STA PASSED\n");
  1500. il_sta_ucode_activate(il, sta_id);
  1501. ret = 0;
  1502. break;
  1503. case ADD_STA_NO_ROOM_IN_TBL:
  1504. IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
  1505. break;
  1506. case ADD_STA_NO_BLOCK_ACK_RESOURCE:
  1507. IL_ERR("Adding station %d failed, no block ack resource.\n",
  1508. sta_id);
  1509. break;
  1510. case ADD_STA_MODIFY_NON_EXIST_STA:
  1511. IL_ERR("Attempting to modify non-existing station %d\n",
  1512. sta_id);
  1513. break;
  1514. default:
  1515. D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
  1516. break;
  1517. }
  1518. D_INFO("%s station id %u addr %pM\n",
  1519. il->stations[sta_id].sta.mode ==
  1520. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
  1521. il->stations[sta_id].sta.sta.addr);
  1522. /*
  1523. * XXX: The MAC address in the command buffer is often changed from
  1524. * the original sent to the device. That is, the MAC address
  1525. * written to the command buffer often is not the same MAC address
  1526. * read from the command buffer when the command returns. This
  1527. * issue has not yet been resolved and this debugging is left to
  1528. * observe the problem.
  1529. */
  1530. D_INFO("%s station according to cmd buffer %pM\n",
  1531. il->stations[sta_id].sta.mode ==
  1532. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
  1533. spin_unlock_irqrestore(&il->sta_lock, flags);
  1534. return ret;
  1535. }
  1536. static void
  1537. il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
  1538. struct il_rx_pkt *pkt)
  1539. {
  1540. struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
  1541. il_process_add_sta_resp(il, addsta, pkt, false);
  1542. }
  1543. int
  1544. il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
  1545. {
  1546. struct il_rx_pkt *pkt = NULL;
  1547. int ret = 0;
  1548. u8 data[sizeof(*sta)];
  1549. struct il_host_cmd cmd = {
  1550. .id = C_ADD_STA,
  1551. .flags = flags,
  1552. .data = data,
  1553. };
  1554. u8 sta_id __maybe_unused = sta->sta.sta_id;
  1555. D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
  1556. flags & CMD_ASYNC ? "a" : "");
  1557. if (flags & CMD_ASYNC)
  1558. cmd.callback = il_add_sta_callback;
  1559. else {
  1560. cmd.flags |= CMD_WANT_SKB;
  1561. might_sleep();
  1562. }
  1563. cmd.len = il->ops->build_addsta_hcmd(sta, data);
  1564. ret = il_send_cmd(il, &cmd);
  1565. if (ret)
  1566. return ret;
  1567. if (flags & CMD_ASYNC)
  1568. return 0;
  1569. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1570. ret = il_process_add_sta_resp(il, sta, pkt, true);
  1571. il_free_pages(il, cmd.reply_page);
  1572. return ret;
  1573. }
  1574. EXPORT_SYMBOL(il_send_add_sta);
  1575. static void
  1576. il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
  1577. {
  1578. struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->deflink.ht_cap;
  1579. __le32 sta_flags;
  1580. if (!sta || !sta_ht_inf->ht_supported)
  1581. goto done;
  1582. D_ASSOC("spatial multiplexing power save mode: %s\n",
  1583. (sta->deflink.smps_mode == IEEE80211_SMPS_STATIC) ? "static" :
  1584. (sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC) ? "dynamic" :
  1585. "disabled");
  1586. sta_flags = il->stations[idx].sta.station_flags;
  1587. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  1588. switch (sta->deflink.smps_mode) {
  1589. case IEEE80211_SMPS_STATIC:
  1590. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  1591. break;
  1592. case IEEE80211_SMPS_DYNAMIC:
  1593. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  1594. break;
  1595. case IEEE80211_SMPS_OFF:
  1596. break;
  1597. default:
  1598. IL_WARN("Invalid MIMO PS mode %d\n", sta->deflink.smps_mode);
  1599. break;
  1600. }
  1601. sta_flags |=
  1602. cpu_to_le32((u32) sta_ht_inf->
  1603. ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  1604. sta_flags |=
  1605. cpu_to_le32((u32) sta_ht_inf->
  1606. ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  1607. if (il_is_ht40_tx_allowed(il, &sta->deflink.ht_cap))
  1608. sta_flags |= STA_FLG_HT40_EN_MSK;
  1609. else
  1610. sta_flags &= ~STA_FLG_HT40_EN_MSK;
  1611. il->stations[idx].sta.station_flags = sta_flags;
  1612. done:
  1613. return;
  1614. }
  1615. /*
  1616. * il_prep_station - Prepare station information for addition
  1617. *
  1618. * should be called with sta_lock held
  1619. */
  1620. u8
  1621. il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
  1622. struct ieee80211_sta *sta)
  1623. {
  1624. struct il_station_entry *station;
  1625. int i;
  1626. u8 sta_id = IL_INVALID_STATION;
  1627. u16 rate;
  1628. if (is_ap)
  1629. sta_id = IL_AP_ID;
  1630. else if (is_broadcast_ether_addr(addr))
  1631. sta_id = il->hw_params.bcast_id;
  1632. else
  1633. for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
  1634. if (ether_addr_equal(il->stations[i].sta.sta.addr,
  1635. addr)) {
  1636. sta_id = i;
  1637. break;
  1638. }
  1639. if (!il->stations[i].used &&
  1640. sta_id == IL_INVALID_STATION)
  1641. sta_id = i;
  1642. }
  1643. /*
  1644. * These two conditions have the same outcome, but keep them
  1645. * separate
  1646. */
  1647. if (unlikely(sta_id == IL_INVALID_STATION))
  1648. return sta_id;
  1649. /*
  1650. * uCode is not able to deal with multiple requests to add a
  1651. * station. Keep track if one is in progress so that we do not send
  1652. * another.
  1653. */
  1654. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1655. D_INFO("STA %d already in process of being added.\n", sta_id);
  1656. return sta_id;
  1657. }
  1658. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1659. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
  1660. ether_addr_equal(il->stations[sta_id].sta.sta.addr, addr)) {
  1661. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1662. sta_id, addr);
  1663. return sta_id;
  1664. }
  1665. station = &il->stations[sta_id];
  1666. station->used = IL_STA_DRIVER_ACTIVE;
  1667. D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
  1668. il->num_stations++;
  1669. /* Set up the C_ADD_STA command to send to device */
  1670. memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
  1671. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  1672. station->sta.mode = 0;
  1673. station->sta.sta.sta_id = sta_id;
  1674. station->sta.station_flags = 0;
  1675. /*
  1676. * OK to call unconditionally, since local stations (IBSS BSSID
  1677. * STA and broadcast STA) pass in a NULL sta, and mac80211
  1678. * doesn't allow HT IBSS.
  1679. */
  1680. il_set_ht_add_station(il, sta_id, sta);
  1681. /* 3945 only */
  1682. rate = (il->band == NL80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
  1683. /* Turn on both antennas for the station... */
  1684. station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
  1685. return sta_id;
  1686. }
  1687. EXPORT_SYMBOL_GPL(il_prep_station);
  1688. #define STA_WAIT_TIMEOUT (HZ/2)
  1689. /*
  1690. * il_add_station_common -
  1691. */
  1692. int
  1693. il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
  1694. struct ieee80211_sta *sta, u8 *sta_id_r)
  1695. {
  1696. unsigned long flags_spin;
  1697. int ret = 0;
  1698. u8 sta_id;
  1699. struct il_addsta_cmd sta_cmd;
  1700. *sta_id_r = 0;
  1701. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1702. sta_id = il_prep_station(il, addr, is_ap, sta);
  1703. if (sta_id == IL_INVALID_STATION) {
  1704. IL_ERR("Unable to prepare station %pM for addition\n", addr);
  1705. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1706. return -EINVAL;
  1707. }
  1708. /*
  1709. * uCode is not able to deal with multiple requests to add a
  1710. * station. Keep track if one is in progress so that we do not send
  1711. * another.
  1712. */
  1713. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1714. D_INFO("STA %d already in process of being added.\n", sta_id);
  1715. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1716. return -EEXIST;
  1717. }
  1718. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1719. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1720. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1721. sta_id, addr);
  1722. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1723. return -EEXIST;
  1724. }
  1725. il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
  1726. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  1727. sizeof(struct il_addsta_cmd));
  1728. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1729. /* Add station to device's station table */
  1730. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1731. if (ret) {
  1732. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1733. IL_ERR("Adding station %pM failed.\n",
  1734. il->stations[sta_id].sta.sta.addr);
  1735. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1736. il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  1737. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1738. }
  1739. *sta_id_r = sta_id;
  1740. return ret;
  1741. }
  1742. EXPORT_SYMBOL(il_add_station_common);
  1743. /*
  1744. * il_sta_ucode_deactivate - deactivate ucode status for a station
  1745. *
  1746. * il->sta_lock must be held
  1747. */
  1748. static void
  1749. il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
  1750. {
  1751. /* Ucode must be active and driver must be non active */
  1752. if ((il->stations[sta_id].
  1753. used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
  1754. IL_STA_UCODE_ACTIVE)
  1755. IL_ERR("removed non active STA %u\n", sta_id);
  1756. il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
  1757. memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
  1758. D_ASSOC("Removed STA %u\n", sta_id);
  1759. }
  1760. static int
  1761. il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
  1762. bool temporary)
  1763. {
  1764. struct il_rx_pkt *pkt;
  1765. int ret;
  1766. unsigned long flags_spin;
  1767. struct il_rem_sta_cmd rm_sta_cmd;
  1768. struct il_host_cmd cmd = {
  1769. .id = C_REM_STA,
  1770. .len = sizeof(struct il_rem_sta_cmd),
  1771. .flags = CMD_SYNC,
  1772. .data = &rm_sta_cmd,
  1773. };
  1774. memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
  1775. rm_sta_cmd.num_sta = 1;
  1776. memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
  1777. cmd.flags |= CMD_WANT_SKB;
  1778. ret = il_send_cmd(il, &cmd);
  1779. if (ret)
  1780. return ret;
  1781. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1782. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1783. IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
  1784. ret = -EIO;
  1785. }
  1786. if (!ret) {
  1787. switch (pkt->u.rem_sta.status) {
  1788. case REM_STA_SUCCESS_MSK:
  1789. if (!temporary) {
  1790. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1791. il_sta_ucode_deactivate(il, sta_id);
  1792. spin_unlock_irqrestore(&il->sta_lock,
  1793. flags_spin);
  1794. }
  1795. D_ASSOC("C_REM_STA PASSED\n");
  1796. break;
  1797. default:
  1798. ret = -EIO;
  1799. IL_ERR("C_REM_STA failed\n");
  1800. break;
  1801. }
  1802. }
  1803. il_free_pages(il, cmd.reply_page);
  1804. return ret;
  1805. }
  1806. /*
  1807. * il_remove_station - Remove driver's knowledge of station.
  1808. */
  1809. int
  1810. il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
  1811. {
  1812. unsigned long flags;
  1813. if (!il_is_ready(il)) {
  1814. D_INFO("Unable to remove station %pM, device not ready.\n",
  1815. addr);
  1816. /*
  1817. * It is typical for stations to be removed when we are
  1818. * going down. Return success since device will be down
  1819. * soon anyway
  1820. */
  1821. return 0;
  1822. }
  1823. D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
  1824. if (WARN_ON(sta_id == IL_INVALID_STATION))
  1825. return -EINVAL;
  1826. spin_lock_irqsave(&il->sta_lock, flags);
  1827. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  1828. D_INFO("Removing %pM but non DRIVER active\n", addr);
  1829. goto out_err;
  1830. }
  1831. if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1832. D_INFO("Removing %pM but non UCODE active\n", addr);
  1833. goto out_err;
  1834. }
  1835. if (il->stations[sta_id].used & IL_STA_LOCAL) {
  1836. kfree(il->stations[sta_id].lq);
  1837. il->stations[sta_id].lq = NULL;
  1838. }
  1839. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1840. il->num_stations--;
  1841. BUG_ON(il->num_stations < 0);
  1842. spin_unlock_irqrestore(&il->sta_lock, flags);
  1843. return il_send_remove_station(il, addr, sta_id, false);
  1844. out_err:
  1845. spin_unlock_irqrestore(&il->sta_lock, flags);
  1846. return -EINVAL;
  1847. }
  1848. EXPORT_SYMBOL_GPL(il_remove_station);
  1849. /*
  1850. * il_clear_ucode_stations - clear ucode station table bits
  1851. *
  1852. * This function clears all the bits in the driver indicating
  1853. * which stations are active in the ucode. Call when something
  1854. * other than explicit station management would cause this in
  1855. * the ucode, e.g. unassociated RXON.
  1856. */
  1857. void
  1858. il_clear_ucode_stations(struct il_priv *il)
  1859. {
  1860. int i;
  1861. unsigned long flags_spin;
  1862. bool cleared = false;
  1863. D_INFO("Clearing ucode stations in driver\n");
  1864. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1865. for (i = 0; i < il->hw_params.max_stations; i++) {
  1866. if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
  1867. D_INFO("Clearing ucode active for station %d\n", i);
  1868. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1869. cleared = true;
  1870. }
  1871. }
  1872. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1873. if (!cleared)
  1874. D_INFO("No active stations found to be cleared\n");
  1875. }
  1876. EXPORT_SYMBOL(il_clear_ucode_stations);
  1877. /*
  1878. * il_restore_stations() - Restore driver known stations to device
  1879. *
  1880. * All stations considered active by driver, but not present in ucode, is
  1881. * restored.
  1882. *
  1883. * Function sleeps.
  1884. */
  1885. void
  1886. il_restore_stations(struct il_priv *il)
  1887. {
  1888. struct il_addsta_cmd sta_cmd;
  1889. struct il_link_quality_cmd lq;
  1890. unsigned long flags_spin;
  1891. int i;
  1892. bool found = false;
  1893. int ret;
  1894. bool send_lq;
  1895. if (!il_is_ready(il)) {
  1896. D_INFO("Not ready yet, not restoring any stations.\n");
  1897. return;
  1898. }
  1899. D_ASSOC("Restoring all known stations ... start.\n");
  1900. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1901. for (i = 0; i < il->hw_params.max_stations; i++) {
  1902. if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
  1903. !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
  1904. D_ASSOC("Restoring sta %pM\n",
  1905. il->stations[i].sta.sta.addr);
  1906. il->stations[i].sta.mode = 0;
  1907. il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
  1908. found = true;
  1909. }
  1910. }
  1911. for (i = 0; i < il->hw_params.max_stations; i++) {
  1912. if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
  1913. memcpy(&sta_cmd, &il->stations[i].sta,
  1914. sizeof(struct il_addsta_cmd));
  1915. send_lq = false;
  1916. if (il->stations[i].lq) {
  1917. memcpy(&lq, il->stations[i].lq,
  1918. sizeof(struct il_link_quality_cmd));
  1919. send_lq = true;
  1920. }
  1921. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1922. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1923. if (ret) {
  1924. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1925. IL_ERR("Adding station %pM failed.\n",
  1926. il->stations[i].sta.sta.addr);
  1927. il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
  1928. il->stations[i].used &=
  1929. ~IL_STA_UCODE_INPROGRESS;
  1930. spin_unlock_irqrestore(&il->sta_lock,
  1931. flags_spin);
  1932. }
  1933. /*
  1934. * Rate scaling has already been initialized, send
  1935. * current LQ command
  1936. */
  1937. if (send_lq)
  1938. il_send_lq_cmd(il, &lq, CMD_SYNC, true);
  1939. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1940. il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
  1941. }
  1942. }
  1943. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1944. if (!found)
  1945. D_INFO("Restoring all known stations"
  1946. " .... no stations to be restored.\n");
  1947. else
  1948. D_INFO("Restoring all known stations" " .... complete.\n");
  1949. }
  1950. EXPORT_SYMBOL(il_restore_stations);
  1951. int
  1952. il_get_free_ucode_key_idx(struct il_priv *il)
  1953. {
  1954. int i;
  1955. for (i = 0; i < il->sta_key_max_num; i++)
  1956. if (!test_and_set_bit(i, &il->ucode_key_table))
  1957. return i;
  1958. return WEP_INVALID_OFFSET;
  1959. }
  1960. EXPORT_SYMBOL(il_get_free_ucode_key_idx);
  1961. void
  1962. il_dealloc_bcast_stations(struct il_priv *il)
  1963. {
  1964. unsigned long flags;
  1965. int i;
  1966. spin_lock_irqsave(&il->sta_lock, flags);
  1967. for (i = 0; i < il->hw_params.max_stations; i++) {
  1968. if (!(il->stations[i].used & IL_STA_BCAST))
  1969. continue;
  1970. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1971. il->num_stations--;
  1972. BUG_ON(il->num_stations < 0);
  1973. kfree(il->stations[i].lq);
  1974. il->stations[i].lq = NULL;
  1975. }
  1976. spin_unlock_irqrestore(&il->sta_lock, flags);
  1977. }
  1978. EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
  1979. #ifdef CONFIG_IWLEGACY_DEBUG
  1980. static void
  1981. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1982. {
  1983. int i;
  1984. D_RATE("lq station id 0x%x\n", lq->sta_id);
  1985. D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
  1986. lq->general_params.dual_stream_ant_msk);
  1987. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
  1988. D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
  1989. }
  1990. #else
  1991. static inline void
  1992. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1993. {
  1994. }
  1995. #endif
  1996. /*
  1997. * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
  1998. *
  1999. * It sometimes happens when a HT rate has been in use and we
  2000. * loose connectivity with AP then mac80211 will first tell us that the
  2001. * current channel is not HT anymore before removing the station. In such a
  2002. * scenario the RXON flags will be updated to indicate we are not
  2003. * communicating HT anymore, but the LQ command may still contain HT rates.
  2004. * Test for this to prevent driver from sending LQ command between the time
  2005. * RXON flags are updated and when LQ command is updated.
  2006. */
  2007. static bool
  2008. il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
  2009. {
  2010. int i;
  2011. if (il->ht.enabled)
  2012. return true;
  2013. D_INFO("Channel %u is not an HT channel\n", il->active.channel);
  2014. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  2015. if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
  2016. D_INFO("idx %d of LQ expects HT channel\n", i);
  2017. return false;
  2018. }
  2019. }
  2020. return true;
  2021. }
  2022. /*
  2023. * il_send_lq_cmd() - Send link quality command
  2024. * @init: This command is sent as part of station initialization right
  2025. * after station has been added.
  2026. *
  2027. * The link quality command is sent as the last step of station creation.
  2028. * This is the special case in which init is set and we call a callback in
  2029. * this case to clear the state indicating that station creation is in
  2030. * progress.
  2031. */
  2032. int
  2033. il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
  2034. u8 flags, bool init)
  2035. {
  2036. int ret = 0;
  2037. unsigned long flags_spin;
  2038. struct il_host_cmd cmd = {
  2039. .id = C_TX_LINK_QUALITY_CMD,
  2040. .len = sizeof(struct il_link_quality_cmd),
  2041. .flags = flags,
  2042. .data = lq,
  2043. };
  2044. if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
  2045. return -EINVAL;
  2046. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2047. if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  2048. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2049. return -EINVAL;
  2050. }
  2051. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2052. il_dump_lq_cmd(il, lq);
  2053. BUG_ON(init && (cmd.flags & CMD_ASYNC));
  2054. if (il_is_lq_table_valid(il, lq))
  2055. ret = il_send_cmd(il, &cmd);
  2056. else
  2057. ret = -EINVAL;
  2058. if (cmd.flags & CMD_ASYNC)
  2059. return ret;
  2060. if (init) {
  2061. D_INFO("init LQ command complete,"
  2062. " clearing sta addition status for sta %d\n",
  2063. lq->sta_id);
  2064. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2065. il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  2066. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2067. }
  2068. return ret;
  2069. }
  2070. EXPORT_SYMBOL(il_send_lq_cmd);
  2071. int
  2072. il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2073. struct ieee80211_sta *sta)
  2074. {
  2075. struct il_priv *il = hw->priv;
  2076. struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
  2077. int ret;
  2078. mutex_lock(&il->mutex);
  2079. D_MAC80211("enter station %pM\n", sta->addr);
  2080. ret = il_remove_station(il, sta_common->sta_id, sta->addr);
  2081. if (ret)
  2082. IL_ERR("Error removing station %pM\n", sta->addr);
  2083. D_MAC80211("leave ret %d\n", ret);
  2084. mutex_unlock(&il->mutex);
  2085. return ret;
  2086. }
  2087. EXPORT_SYMBOL(il_mac_sta_remove);
  2088. /************************** RX-FUNCTIONS ****************************/
  2089. /*
  2090. * Rx theory of operation
  2091. *
  2092. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  2093. * each of which point to Receive Buffers to be filled by the NIC. These get
  2094. * used not only for Rx frames, but for any command response or notification
  2095. * from the NIC. The driver and NIC manage the Rx buffers by means
  2096. * of idxes into the circular buffer.
  2097. *
  2098. * Rx Queue Indexes
  2099. * The host/firmware share two idx registers for managing the Rx buffers.
  2100. *
  2101. * The READ idx maps to the first position that the firmware may be writing
  2102. * to -- the driver can read up to (but not including) this position and get
  2103. * good data.
  2104. * The READ idx is managed by the firmware once the card is enabled.
  2105. *
  2106. * The WRITE idx maps to the last position the driver has read from -- the
  2107. * position preceding WRITE is the last slot the firmware can place a packet.
  2108. *
  2109. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2110. * WRITE = READ.
  2111. *
  2112. * During initialization, the host sets up the READ queue position to the first
  2113. * IDX position, and WRITE to the last (READ - 1 wrapped)
  2114. *
  2115. * When the firmware places a packet in a buffer, it will advance the READ idx
  2116. * and fire the RX interrupt. The driver can then query the READ idx and
  2117. * process as many packets as possible, moving the WRITE idx forward as it
  2118. * resets the Rx queue buffers with new memory.
  2119. *
  2120. * The management in the driver is as follows:
  2121. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2122. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2123. * to replenish the iwl->rxq->rx_free.
  2124. * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
  2125. * iwl->rxq is replenished and the READ IDX is updated (updating the
  2126. * 'processed' and 'read' driver idxes as well)
  2127. * + A received packet is processed and handed to the kernel network stack,
  2128. * detached from the iwl->rxq. The driver 'processed' idx is updated.
  2129. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2130. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2131. * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
  2132. * were enough free buffers and RX_STALLED is set it is cleared.
  2133. *
  2134. *
  2135. * Driver sequence:
  2136. *
  2137. * il_rx_queue_alloc() Allocates rx_free
  2138. * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2139. * il_rx_queue_restock
  2140. * il_rx_queue_restock() Moves available buffers from rx_free into Rx
  2141. * queue, updates firmware pointers, and updates
  2142. * the WRITE idx. If insufficient rx_free buffers
  2143. * are available, schedules il_rx_replenish
  2144. *
  2145. * -- enable interrupts --
  2146. * ISR - il_rx() Detach il_rx_bufs from pool up to the
  2147. * READ IDX, detaching the SKB from the pool.
  2148. * Moves the packet buffer from queue to rx_used.
  2149. * Calls il_rx_queue_restock to refill any empty
  2150. * slots.
  2151. * ...
  2152. *
  2153. */
  2154. /*
  2155. * il_rx_queue_space - Return number of free slots available in queue.
  2156. */
  2157. int
  2158. il_rx_queue_space(const struct il_rx_queue *q)
  2159. {
  2160. int s = q->read - q->write;
  2161. if (s <= 0)
  2162. s += RX_QUEUE_SIZE;
  2163. /* keep some buffer to not confuse full and empty queue */
  2164. s -= 2;
  2165. if (s < 0)
  2166. s = 0;
  2167. return s;
  2168. }
  2169. EXPORT_SYMBOL(il_rx_queue_space);
  2170. /*
  2171. * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2172. */
  2173. void
  2174. il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
  2175. {
  2176. unsigned long flags;
  2177. u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
  2178. u32 reg;
  2179. spin_lock_irqsave(&q->lock, flags);
  2180. if (q->need_update == 0)
  2181. goto exit_unlock;
  2182. /* If power-saving is in use, make sure device is awake */
  2183. if (test_bit(S_POWER_PMI, &il->status)) {
  2184. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2185. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2186. D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
  2187. reg);
  2188. il_set_bit(il, CSR_GP_CNTRL,
  2189. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2190. goto exit_unlock;
  2191. }
  2192. q->write_actual = (q->write & ~0x7);
  2193. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2194. /* Else device is assumed to be awake */
  2195. } else {
  2196. /* Device expects a multiple of 8 */
  2197. q->write_actual = (q->write & ~0x7);
  2198. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2199. }
  2200. q->need_update = 0;
  2201. exit_unlock:
  2202. spin_unlock_irqrestore(&q->lock, flags);
  2203. }
  2204. EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
  2205. int
  2206. il_rx_queue_alloc(struct il_priv *il)
  2207. {
  2208. struct il_rx_queue *rxq = &il->rxq;
  2209. struct device *dev = &il->pci_dev->dev;
  2210. int i;
  2211. spin_lock_init(&rxq->lock);
  2212. INIT_LIST_HEAD(&rxq->rx_free);
  2213. INIT_LIST_HEAD(&rxq->rx_used);
  2214. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2215. rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
  2216. GFP_KERNEL);
  2217. if (!rxq->bd)
  2218. goto err_bd;
  2219. rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct il_rb_status),
  2220. &rxq->rb_stts_dma, GFP_KERNEL);
  2221. if (!rxq->rb_stts)
  2222. goto err_rb;
  2223. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2224. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2225. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2226. /* Set us so that we have processed and used all buffers, but have
  2227. * not restocked the Rx queue with fresh buffers */
  2228. rxq->read = rxq->write = 0;
  2229. rxq->write_actual = 0;
  2230. rxq->free_count = 0;
  2231. rxq->need_update = 0;
  2232. return 0;
  2233. err_rb:
  2234. dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2235. rxq->bd_dma);
  2236. err_bd:
  2237. return -ENOMEM;
  2238. }
  2239. EXPORT_SYMBOL(il_rx_queue_alloc);
  2240. void
  2241. il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
  2242. {
  2243. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2244. struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2245. if (!report->state) {
  2246. D_11H("Spectrum Measure Notification: Start\n");
  2247. return;
  2248. }
  2249. memcpy(&il->measure_report, report, sizeof(*report));
  2250. il->measurement_status |= MEASUREMENT_READY;
  2251. }
  2252. EXPORT_SYMBOL(il_hdl_spectrum_measurement);
  2253. /*
  2254. * returns non-zero if packet should be dropped
  2255. */
  2256. int
  2257. il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
  2258. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2259. {
  2260. u16 fc = le16_to_cpu(hdr->frame_control);
  2261. /*
  2262. * All contexts have the same setting here due to it being
  2263. * a module parameter, so OK to check any context.
  2264. */
  2265. if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2266. return 0;
  2267. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2268. return 0;
  2269. D_RX("decrypt_res:0x%x\n", decrypt_res);
  2270. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2271. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2272. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2273. * Decryption will be done in SW. */
  2274. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2275. RX_RES_STATUS_BAD_KEY_TTAK)
  2276. break;
  2277. fallthrough;
  2278. case RX_RES_STATUS_SEC_TYPE_WEP:
  2279. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2280. RX_RES_STATUS_BAD_ICV_MIC) {
  2281. /* bad ICV, the packet is destroyed since the
  2282. * decryption is inplace, drop it */
  2283. D_RX("Packet destroyed\n");
  2284. return -1;
  2285. }
  2286. fallthrough;
  2287. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2288. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2289. RX_RES_STATUS_DECRYPT_OK) {
  2290. D_RX("hw decrypt successfully!!!\n");
  2291. stats->flag |= RX_FLAG_DECRYPTED;
  2292. }
  2293. break;
  2294. default:
  2295. break;
  2296. }
  2297. return 0;
  2298. }
  2299. EXPORT_SYMBOL(il_set_decrypted_flag);
  2300. /*
  2301. * il_txq_update_write_ptr - Send new write idx to hardware
  2302. */
  2303. void
  2304. il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
  2305. {
  2306. u32 reg = 0;
  2307. int txq_id = txq->q.id;
  2308. if (txq->need_update == 0)
  2309. return;
  2310. /* if we're trying to save power */
  2311. if (test_bit(S_POWER_PMI, &il->status)) {
  2312. /* wake up nic if it's powered down ...
  2313. * uCode will wake up, and interrupt us again, so next
  2314. * time we'll skip this part. */
  2315. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2316. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2317. D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
  2318. txq_id, reg);
  2319. il_set_bit(il, CSR_GP_CNTRL,
  2320. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2321. return;
  2322. }
  2323. il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2324. /*
  2325. * else not in power-save mode,
  2326. * uCode will never sleep when we're
  2327. * trying to tx (during RFKILL, we're not trying to tx).
  2328. */
  2329. } else
  2330. _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2331. txq->need_update = 0;
  2332. }
  2333. EXPORT_SYMBOL(il_txq_update_write_ptr);
  2334. /*
  2335. * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  2336. */
  2337. void
  2338. il_tx_queue_unmap(struct il_priv *il, int txq_id)
  2339. {
  2340. struct il_tx_queue *txq = &il->txq[txq_id];
  2341. struct il_queue *q = &txq->q;
  2342. if (q->n_bd == 0)
  2343. return;
  2344. while (q->write_ptr != q->read_ptr) {
  2345. il->ops->txq_free_tfd(il, txq);
  2346. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2347. }
  2348. }
  2349. EXPORT_SYMBOL(il_tx_queue_unmap);
  2350. /*
  2351. * il_tx_queue_free - Deallocate DMA queue.
  2352. * @txq: Transmit queue to deallocate.
  2353. *
  2354. * Empty queue by removing and destroying all BD's.
  2355. * Free all buffers.
  2356. * 0-fill, but do not free "txq" descriptor structure.
  2357. */
  2358. void
  2359. il_tx_queue_free(struct il_priv *il, int txq_id)
  2360. {
  2361. struct il_tx_queue *txq = &il->txq[txq_id];
  2362. struct device *dev = &il->pci_dev->dev;
  2363. int i;
  2364. il_tx_queue_unmap(il, txq_id);
  2365. /* De-alloc array of command/tx buffers */
  2366. if (txq->cmd) {
  2367. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  2368. kfree(txq->cmd[i]);
  2369. }
  2370. /* De-alloc circular buffer of TFDs */
  2371. if (txq->q.n_bd)
  2372. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2373. txq->tfds, txq->q.dma_addr);
  2374. /* De-alloc array of per-TFD driver data */
  2375. kfree(txq->skbs);
  2376. txq->skbs = NULL;
  2377. /* deallocate arrays */
  2378. kfree(txq->cmd);
  2379. kfree(txq->meta);
  2380. txq->cmd = NULL;
  2381. txq->meta = NULL;
  2382. /* 0-fill queue descriptor structure */
  2383. memset(txq, 0, sizeof(*txq));
  2384. }
  2385. EXPORT_SYMBOL(il_tx_queue_free);
  2386. /*
  2387. * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  2388. */
  2389. void
  2390. il_cmd_queue_unmap(struct il_priv *il)
  2391. {
  2392. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2393. struct il_queue *q = &txq->q;
  2394. int i;
  2395. if (q->n_bd == 0)
  2396. return;
  2397. while (q->read_ptr != q->write_ptr) {
  2398. i = il_get_cmd_idx(q, q->read_ptr, 0);
  2399. if (txq->meta[i].flags & CMD_MAPPED) {
  2400. dma_unmap_single(&il->pci_dev->dev,
  2401. dma_unmap_addr(&txq->meta[i], mapping),
  2402. dma_unmap_len(&txq->meta[i], len),
  2403. DMA_BIDIRECTIONAL);
  2404. txq->meta[i].flags = 0;
  2405. }
  2406. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2407. }
  2408. i = q->n_win;
  2409. if (txq->meta[i].flags & CMD_MAPPED) {
  2410. dma_unmap_single(&il->pci_dev->dev,
  2411. dma_unmap_addr(&txq->meta[i], mapping),
  2412. dma_unmap_len(&txq->meta[i], len),
  2413. DMA_BIDIRECTIONAL);
  2414. txq->meta[i].flags = 0;
  2415. }
  2416. }
  2417. EXPORT_SYMBOL(il_cmd_queue_unmap);
  2418. /*
  2419. * il_cmd_queue_free - Deallocate DMA queue.
  2420. *
  2421. * Empty queue by removing and destroying all BD's.
  2422. * Free all buffers.
  2423. * 0-fill, but do not free "txq" descriptor structure.
  2424. */
  2425. void
  2426. il_cmd_queue_free(struct il_priv *il)
  2427. {
  2428. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2429. struct device *dev = &il->pci_dev->dev;
  2430. int i;
  2431. il_cmd_queue_unmap(il);
  2432. /* De-alloc array of command/tx buffers */
  2433. if (txq->cmd) {
  2434. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  2435. kfree(txq->cmd[i]);
  2436. }
  2437. /* De-alloc circular buffer of TFDs */
  2438. if (txq->q.n_bd)
  2439. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2440. txq->tfds, txq->q.dma_addr);
  2441. /* deallocate arrays */
  2442. kfree(txq->cmd);
  2443. kfree(txq->meta);
  2444. txq->cmd = NULL;
  2445. txq->meta = NULL;
  2446. /* 0-fill queue descriptor structure */
  2447. memset(txq, 0, sizeof(*txq));
  2448. }
  2449. EXPORT_SYMBOL(il_cmd_queue_free);
  2450. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  2451. * DMA services
  2452. *
  2453. * Theory of operation
  2454. *
  2455. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  2456. * of buffer descriptors, each of which points to one or more data buffers for
  2457. * the device to read from or fill. Driver and device exchange status of each
  2458. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  2459. * entries in each circular buffer, to protect against confusing empty and full
  2460. * queue states.
  2461. *
  2462. * The device reads or writes the data in the queues via the device's several
  2463. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  2464. *
  2465. * For Tx queue, there are low mark and high mark limits. If, after queuing
  2466. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  2467. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  2468. * Tx queue resumed.
  2469. *
  2470. * See more detailed info in 4965.h.
  2471. ***************************************************/
  2472. int
  2473. il_queue_space(const struct il_queue *q)
  2474. {
  2475. int s = q->read_ptr - q->write_ptr;
  2476. if (q->read_ptr > q->write_ptr)
  2477. s -= q->n_bd;
  2478. if (s <= 0)
  2479. s += q->n_win;
  2480. /* keep some reserve to not confuse empty and full situations */
  2481. s -= 2;
  2482. if (s < 0)
  2483. s = 0;
  2484. return s;
  2485. }
  2486. EXPORT_SYMBOL(il_queue_space);
  2487. /*
  2488. * il_queue_init - Initialize queue's high/low-water and read/write idxes
  2489. */
  2490. static int
  2491. il_queue_init(struct il_priv *il, struct il_queue *q, int slots, u32 id)
  2492. {
  2493. /*
  2494. * TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  2495. * il_queue_inc_wrap and il_queue_dec_wrap are broken.
  2496. */
  2497. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  2498. /* FIXME: remove q->n_bd */
  2499. q->n_bd = TFD_QUEUE_SIZE_MAX;
  2500. q->n_win = slots;
  2501. q->id = id;
  2502. /* slots_must be power-of-two size, otherwise
  2503. * il_get_cmd_idx is broken. */
  2504. BUG_ON(!is_power_of_2(slots));
  2505. q->low_mark = q->n_win / 4;
  2506. if (q->low_mark < 4)
  2507. q->low_mark = 4;
  2508. q->high_mark = q->n_win / 8;
  2509. if (q->high_mark < 2)
  2510. q->high_mark = 2;
  2511. q->write_ptr = q->read_ptr = 0;
  2512. return 0;
  2513. }
  2514. /*
  2515. * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  2516. */
  2517. static int
  2518. il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
  2519. {
  2520. struct device *dev = &il->pci_dev->dev;
  2521. size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  2522. /* Driver ilate data, only for Tx (not command) queues,
  2523. * not shared with device. */
  2524. if (id != il->cmd_queue) {
  2525. txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX,
  2526. sizeof(struct sk_buff *),
  2527. GFP_KERNEL);
  2528. if (!txq->skbs) {
  2529. IL_ERR("Fail to alloc skbs\n");
  2530. goto error;
  2531. }
  2532. } else
  2533. txq->skbs = NULL;
  2534. /* Circular buffer of transmit frame descriptors (TFDs),
  2535. * shared with device */
  2536. txq->tfds =
  2537. dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
  2538. if (!txq->tfds)
  2539. goto error;
  2540. txq->q.id = id;
  2541. return 0;
  2542. error:
  2543. kfree(txq->skbs);
  2544. txq->skbs = NULL;
  2545. return -ENOMEM;
  2546. }
  2547. /*
  2548. * il_tx_queue_init - Allocate and initialize one tx/cmd queue
  2549. */
  2550. int
  2551. il_tx_queue_init(struct il_priv *il, u32 txq_id)
  2552. {
  2553. int i, len, ret;
  2554. int slots, actual_slots;
  2555. struct il_tx_queue *txq = &il->txq[txq_id];
  2556. /*
  2557. * Alloc buffer array for commands (Tx or other types of commands).
  2558. * For the command queue (#4/#9), allocate command space + one big
  2559. * command for scan, since scan command is very huge; the system will
  2560. * not have two scans at the same time, so only one is needed.
  2561. * For normal Tx queues (all other queues), no super-size command
  2562. * space is needed.
  2563. */
  2564. if (txq_id == il->cmd_queue) {
  2565. slots = TFD_CMD_SLOTS;
  2566. actual_slots = slots + 1;
  2567. } else {
  2568. slots = TFD_TX_CMD_SLOTS;
  2569. actual_slots = slots;
  2570. }
  2571. txq->meta =
  2572. kcalloc(actual_slots, sizeof(struct il_cmd_meta), GFP_KERNEL);
  2573. txq->cmd =
  2574. kcalloc(actual_slots, sizeof(struct il_device_cmd *), GFP_KERNEL);
  2575. if (!txq->meta || !txq->cmd)
  2576. goto out_free_arrays;
  2577. len = sizeof(struct il_device_cmd);
  2578. for (i = 0; i < actual_slots; i++) {
  2579. /* only happens for cmd queue */
  2580. if (i == slots)
  2581. len = IL_MAX_CMD_SIZE;
  2582. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  2583. if (!txq->cmd[i])
  2584. goto err;
  2585. }
  2586. /* Alloc driver data array and TFD circular buffer */
  2587. ret = il_tx_queue_alloc(il, txq, txq_id);
  2588. if (ret)
  2589. goto err;
  2590. txq->need_update = 0;
  2591. /*
  2592. * For the default queues 0-3, set up the swq_id
  2593. * already -- all others need to get one later
  2594. * (if they need one at all).
  2595. */
  2596. if (txq_id < 4)
  2597. il_set_swq_id(txq, txq_id, txq_id);
  2598. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2599. il_queue_init(il, &txq->q, slots, txq_id);
  2600. /* Tell device where to find queue */
  2601. il->ops->txq_init(il, txq);
  2602. return 0;
  2603. err:
  2604. for (i = 0; i < actual_slots; i++)
  2605. kfree(txq->cmd[i]);
  2606. out_free_arrays:
  2607. kfree(txq->meta);
  2608. txq->meta = NULL;
  2609. kfree(txq->cmd);
  2610. txq->cmd = NULL;
  2611. return -ENOMEM;
  2612. }
  2613. EXPORT_SYMBOL(il_tx_queue_init);
  2614. void
  2615. il_tx_queue_reset(struct il_priv *il, u32 txq_id)
  2616. {
  2617. int slots, actual_slots;
  2618. struct il_tx_queue *txq = &il->txq[txq_id];
  2619. if (txq_id == il->cmd_queue) {
  2620. slots = TFD_CMD_SLOTS;
  2621. actual_slots = TFD_CMD_SLOTS + 1;
  2622. } else {
  2623. slots = TFD_TX_CMD_SLOTS;
  2624. actual_slots = TFD_TX_CMD_SLOTS;
  2625. }
  2626. memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
  2627. txq->need_update = 0;
  2628. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2629. il_queue_init(il, &txq->q, slots, txq_id);
  2630. /* Tell device where to find queue */
  2631. il->ops->txq_init(il, txq);
  2632. }
  2633. EXPORT_SYMBOL(il_tx_queue_reset);
  2634. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  2635. /*
  2636. * il_enqueue_hcmd - enqueue a uCode command
  2637. * @il: device ilate data point
  2638. * @cmd: a point to the ucode command structure
  2639. *
  2640. * The function returns < 0 values to indicate the operation is
  2641. * failed. On success, it turns the idx (> 0) of command in the
  2642. * command queue.
  2643. */
  2644. int
  2645. il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
  2646. {
  2647. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2648. struct il_queue *q = &txq->q;
  2649. struct il_device_cmd *out_cmd;
  2650. struct il_cmd_meta *out_meta;
  2651. dma_addr_t phys_addr;
  2652. unsigned long flags;
  2653. u32 idx;
  2654. u16 fix_size;
  2655. cmd->len = il->ops->get_hcmd_size(cmd->id, cmd->len);
  2656. fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
  2657. /* If any of the command structures end up being larger than
  2658. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  2659. * we will need to increase the size of the TFD entries
  2660. * Also, check to see if command buffer should not exceed the size
  2661. * of device_cmd and max_cmd_size. */
  2662. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  2663. !(cmd->flags & CMD_SIZE_HUGE));
  2664. BUG_ON(fix_size > IL_MAX_CMD_SIZE);
  2665. if (il_is_rfkill(il) || il_is_ctkill(il)) {
  2666. IL_WARN("Not sending command - %s KILL\n",
  2667. il_is_rfkill(il) ? "RF" : "CT");
  2668. return -EIO;
  2669. }
  2670. spin_lock_irqsave(&il->hcmd_lock, flags);
  2671. if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  2672. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2673. IL_ERR("Restarting adapter due to command queue full\n");
  2674. queue_work(il->workqueue, &il->restart);
  2675. return -ENOSPC;
  2676. }
  2677. idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  2678. out_cmd = txq->cmd[idx];
  2679. out_meta = &txq->meta[idx];
  2680. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  2681. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2682. return -ENOSPC;
  2683. }
  2684. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  2685. out_meta->flags = cmd->flags | CMD_MAPPED;
  2686. if (cmd->flags & CMD_WANT_SKB)
  2687. out_meta->source = cmd;
  2688. if (cmd->flags & CMD_ASYNC)
  2689. out_meta->callback = cmd->callback;
  2690. out_cmd->hdr.cmd = cmd->id;
  2691. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  2692. /* At this point, the out_cmd now has all of the incoming cmd
  2693. * information */
  2694. out_cmd->hdr.flags = 0;
  2695. out_cmd->hdr.sequence =
  2696. cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
  2697. if (cmd->flags & CMD_SIZE_HUGE)
  2698. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  2699. #ifdef CONFIG_IWLEGACY_DEBUG
  2700. switch (out_cmd->hdr.cmd) {
  2701. case C_TX_LINK_QUALITY_CMD:
  2702. case C_SENSITIVITY:
  2703. D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
  2704. "%d bytes at %d[%d]:%d\n",
  2705. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2706. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  2707. q->write_ptr, idx, il->cmd_queue);
  2708. break;
  2709. default:
  2710. D_HC("Sending command %s (#%x), seq: 0x%04X, "
  2711. "%d bytes at %d[%d]:%d\n",
  2712. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2713. le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
  2714. idx, il->cmd_queue);
  2715. }
  2716. #endif
  2717. phys_addr = dma_map_single(&il->pci_dev->dev, &out_cmd->hdr, fix_size,
  2718. DMA_BIDIRECTIONAL);
  2719. if (unlikely(dma_mapping_error(&il->pci_dev->dev, phys_addr))) {
  2720. idx = -ENOMEM;
  2721. goto out;
  2722. }
  2723. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  2724. dma_unmap_len_set(out_meta, len, fix_size);
  2725. txq->need_update = 1;
  2726. if (il->ops->txq_update_byte_cnt_tbl)
  2727. /* Set up entry in queue's byte count circular buffer */
  2728. il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
  2729. il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
  2730. U32_PAD(cmd->len));
  2731. /* Increment and update queue's write idx */
  2732. q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
  2733. il_txq_update_write_ptr(il, txq);
  2734. out:
  2735. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2736. return idx;
  2737. }
  2738. /*
  2739. * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  2740. *
  2741. * When FW advances 'R' idx, all entries between old and new 'R' idx
  2742. * need to be reclaimed. As result, some free space forms. If there is
  2743. * enough free space (> low mark), wake the stack that feeds us.
  2744. */
  2745. static void
  2746. il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
  2747. {
  2748. struct il_tx_queue *txq = &il->txq[txq_id];
  2749. struct il_queue *q = &txq->q;
  2750. int nfreed = 0;
  2751. if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
  2752. IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
  2753. "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
  2754. q->write_ptr, q->read_ptr);
  2755. return;
  2756. }
  2757. for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  2758. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2759. if (nfreed++ > 0) {
  2760. IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
  2761. q->write_ptr, q->read_ptr);
  2762. queue_work(il->workqueue, &il->restart);
  2763. }
  2764. }
  2765. }
  2766. /*
  2767. * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2768. * @rxb: Rx buffer to reclaim
  2769. *
  2770. * If an Rx buffer has an async callback associated with it the callback
  2771. * will be executed. The attached skb (if present) will only be freed
  2772. * if the callback returns 1
  2773. */
  2774. void
  2775. il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
  2776. {
  2777. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2778. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2779. int txq_id = SEQ_TO_QUEUE(sequence);
  2780. int idx = SEQ_TO_IDX(sequence);
  2781. int cmd_idx;
  2782. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2783. struct il_device_cmd *cmd;
  2784. struct il_cmd_meta *meta;
  2785. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2786. unsigned long flags;
  2787. /* If a Tx command is being handled and it isn't in the actual
  2788. * command queue then there a command routing bug has been introduced
  2789. * in the queue management code. */
  2790. if (WARN
  2791. (txq_id != il->cmd_queue,
  2792. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  2793. txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
  2794. il->txq[il->cmd_queue].q.write_ptr)) {
  2795. il_print_hex_error(il, pkt, 32);
  2796. return;
  2797. }
  2798. cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
  2799. cmd = txq->cmd[cmd_idx];
  2800. meta = &txq->meta[cmd_idx];
  2801. txq->time_stamp = jiffies;
  2802. dma_unmap_single(&il->pci_dev->dev, dma_unmap_addr(meta, mapping),
  2803. dma_unmap_len(meta, len), DMA_BIDIRECTIONAL);
  2804. /* Input error checking is done when commands are added to queue. */
  2805. if (meta->flags & CMD_WANT_SKB) {
  2806. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  2807. rxb->page = NULL;
  2808. } else if (meta->callback)
  2809. meta->callback(il, cmd, pkt);
  2810. spin_lock_irqsave(&il->hcmd_lock, flags);
  2811. il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
  2812. if (!(meta->flags & CMD_ASYNC)) {
  2813. clear_bit(S_HCMD_ACTIVE, &il->status);
  2814. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  2815. il_get_cmd_string(cmd->hdr.cmd));
  2816. wake_up(&il->wait_command_queue);
  2817. }
  2818. /* Mark as unmapped */
  2819. meta->flags = 0;
  2820. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2821. }
  2822. EXPORT_SYMBOL(il_tx_cmd_complete);
  2823. MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
  2824. MODULE_VERSION(IWLWIFI_VERSION);
  2825. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  2826. MODULE_LICENSE("GPL");
  2827. /*
  2828. * set bt_coex_active to true, uCode will do kill/defer
  2829. * every time the priority line is asserted (BT is sending signals on the
  2830. * priority line in the PCIx).
  2831. * set bt_coex_active to false, uCode will ignore the BT activity and
  2832. * perform the normal operation
  2833. *
  2834. * User might experience transmit issue on some platform due to WiFi/BT
  2835. * co-exist problem. The possible behaviors are:
  2836. * Able to scan and finding all the available AP
  2837. * Not able to associate with any AP
  2838. * On those platforms, WiFi communication can be restored by set
  2839. * "bt_coex_active" module parameter to "false"
  2840. *
  2841. * default: bt_coex_active = true (BT_COEX_ENABLE)
  2842. */
  2843. static bool bt_coex_active = true;
  2844. module_param(bt_coex_active, bool, 0444);
  2845. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
  2846. u32 il_debug_level;
  2847. EXPORT_SYMBOL(il_debug_level);
  2848. const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  2849. EXPORT_SYMBOL(il_bcast_addr);
  2850. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  2851. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  2852. static void
  2853. il_init_ht_hw_capab(const struct il_priv *il,
  2854. struct ieee80211_sta_ht_cap *ht_info,
  2855. enum nl80211_band band)
  2856. {
  2857. u16 max_bit_rate = 0;
  2858. u8 rx_chains_num = il->hw_params.rx_chains_num;
  2859. u8 tx_chains_num = il->hw_params.tx_chains_num;
  2860. ht_info->cap = 0;
  2861. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  2862. ht_info->ht_supported = true;
  2863. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  2864. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  2865. if (il->hw_params.ht40_channel & BIT(band)) {
  2866. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  2867. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  2868. ht_info->mcs.rx_mask[4] = 0x01;
  2869. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  2870. }
  2871. if (il->cfg->mod_params->amsdu_size_8K)
  2872. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  2873. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  2874. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  2875. ht_info->mcs.rx_mask[0] = 0xFF;
  2876. if (rx_chains_num >= 2)
  2877. ht_info->mcs.rx_mask[1] = 0xFF;
  2878. if (rx_chains_num >= 3)
  2879. ht_info->mcs.rx_mask[2] = 0xFF;
  2880. /* Highest supported Rx data rate */
  2881. max_bit_rate *= rx_chains_num;
  2882. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  2883. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  2884. /* Tx MCS capabilities */
  2885. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  2886. if (tx_chains_num != rx_chains_num) {
  2887. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  2888. ht_info->mcs.tx_params |=
  2889. ((tx_chains_num -
  2890. 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2891. }
  2892. }
  2893. /*
  2894. * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
  2895. */
  2896. int
  2897. il_init_geos(struct il_priv *il)
  2898. {
  2899. struct il_channel_info *ch;
  2900. struct ieee80211_supported_band *sband;
  2901. struct ieee80211_channel *channels;
  2902. struct ieee80211_channel *geo_ch;
  2903. struct ieee80211_rate *rates;
  2904. int i = 0;
  2905. s8 max_tx_power = 0;
  2906. if (il->bands[NL80211_BAND_2GHZ].n_bitrates ||
  2907. il->bands[NL80211_BAND_5GHZ].n_bitrates) {
  2908. D_INFO("Geography modes already initialized.\n");
  2909. set_bit(S_GEO_CONFIGURED, &il->status);
  2910. return 0;
  2911. }
  2912. channels =
  2913. kcalloc(il->channel_count, sizeof(struct ieee80211_channel),
  2914. GFP_KERNEL);
  2915. if (!channels)
  2916. return -ENOMEM;
  2917. rates =
  2918. kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
  2919. GFP_KERNEL);
  2920. if (!rates) {
  2921. kfree(channels);
  2922. return -ENOMEM;
  2923. }
  2924. /* 5.2GHz channels start after the 2.4GHz channels */
  2925. sband = &il->bands[NL80211_BAND_5GHZ];
  2926. sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
  2927. /* just OFDM */
  2928. sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
  2929. sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
  2930. if (il->cfg->sku & IL_SKU_N)
  2931. il_init_ht_hw_capab(il, &sband->ht_cap, NL80211_BAND_5GHZ);
  2932. sband = &il->bands[NL80211_BAND_2GHZ];
  2933. sband->channels = channels;
  2934. /* OFDM & CCK */
  2935. sband->bitrates = rates;
  2936. sband->n_bitrates = RATE_COUNT_LEGACY;
  2937. if (il->cfg->sku & IL_SKU_N)
  2938. il_init_ht_hw_capab(il, &sband->ht_cap, NL80211_BAND_2GHZ);
  2939. il->ieee_channels = channels;
  2940. il->ieee_rates = rates;
  2941. for (i = 0; i < il->channel_count; i++) {
  2942. ch = &il->channel_info[i];
  2943. if (!il_is_channel_valid(ch))
  2944. continue;
  2945. sband = &il->bands[ch->band];
  2946. geo_ch = &sband->channels[sband->n_channels++];
  2947. geo_ch->center_freq =
  2948. ieee80211_channel_to_frequency(ch->channel, ch->band);
  2949. geo_ch->max_power = ch->max_power_avg;
  2950. geo_ch->max_antenna_gain = 0xff;
  2951. geo_ch->hw_value = ch->channel;
  2952. if (il_is_channel_valid(ch)) {
  2953. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  2954. geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2955. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  2956. geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2957. if (ch->flags & EEPROM_CHANNEL_RADAR)
  2958. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  2959. geo_ch->flags |= ch->ht40_extension_channel;
  2960. if (ch->max_power_avg > max_tx_power)
  2961. max_tx_power = ch->max_power_avg;
  2962. } else {
  2963. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  2964. }
  2965. D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
  2966. geo_ch->center_freq,
  2967. il_is_channel_a_band(ch) ? "5.2" : "2.4",
  2968. geo_ch->
  2969. flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
  2970. geo_ch->flags);
  2971. }
  2972. il->tx_power_device_lmt = max_tx_power;
  2973. il->tx_power_user_lmt = max_tx_power;
  2974. il->tx_power_next = max_tx_power;
  2975. if (il->bands[NL80211_BAND_5GHZ].n_channels == 0 &&
  2976. (il->cfg->sku & IL_SKU_A)) {
  2977. IL_INFO("Incorrectly detected BG card as ABG. "
  2978. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  2979. il->pci_dev->device, il->pci_dev->subsystem_device);
  2980. il->cfg->sku &= ~IL_SKU_A;
  2981. }
  2982. IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  2983. il->bands[NL80211_BAND_2GHZ].n_channels,
  2984. il->bands[NL80211_BAND_5GHZ].n_channels);
  2985. set_bit(S_GEO_CONFIGURED, &il->status);
  2986. return 0;
  2987. }
  2988. EXPORT_SYMBOL(il_init_geos);
  2989. /*
  2990. * il_free_geos - undo allocations in il_init_geos
  2991. */
  2992. void
  2993. il_free_geos(struct il_priv *il)
  2994. {
  2995. kfree(il->ieee_channels);
  2996. kfree(il->ieee_rates);
  2997. clear_bit(S_GEO_CONFIGURED, &il->status);
  2998. }
  2999. EXPORT_SYMBOL(il_free_geos);
  3000. static bool
  3001. il_is_channel_extension(struct il_priv *il, enum nl80211_band band,
  3002. u16 channel, u8 extension_chan_offset)
  3003. {
  3004. const struct il_channel_info *ch_info;
  3005. ch_info = il_get_channel_info(il, band, channel);
  3006. if (!il_is_channel_valid(ch_info))
  3007. return false;
  3008. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  3009. return !(ch_info->
  3010. ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
  3011. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  3012. return !(ch_info->
  3013. ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
  3014. return false;
  3015. }
  3016. bool
  3017. il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
  3018. {
  3019. if (!il->ht.enabled || !il->ht.is_40mhz)
  3020. return false;
  3021. /*
  3022. * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  3023. * the bit will not set if it is pure 40MHz case
  3024. */
  3025. if (ht_cap && !ht_cap->ht_supported)
  3026. return false;
  3027. #ifdef CONFIG_IWLEGACY_DEBUGFS
  3028. if (il->disable_ht40)
  3029. return false;
  3030. #endif
  3031. return il_is_channel_extension(il, il->band,
  3032. le16_to_cpu(il->staging.channel),
  3033. il->ht.extension_chan_offset);
  3034. }
  3035. EXPORT_SYMBOL(il_is_ht40_tx_allowed);
  3036. static u16 noinline
  3037. il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  3038. {
  3039. u16 new_val;
  3040. u16 beacon_factor;
  3041. /*
  3042. * If mac80211 hasn't given us a beacon interval, program
  3043. * the default into the device.
  3044. */
  3045. if (!beacon_val)
  3046. return DEFAULT_BEACON_INTERVAL;
  3047. /*
  3048. * If the beacon interval we obtained from the peer
  3049. * is too large, we'll have to wake up more often
  3050. * (and in IBSS case, we'll beacon too much)
  3051. *
  3052. * For example, if max_beacon_val is 4096, and the
  3053. * requested beacon interval is 7000, we'll have to
  3054. * use 3500 to be able to wake up on the beacons.
  3055. *
  3056. * This could badly influence beacon detection stats.
  3057. */
  3058. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  3059. new_val = beacon_val / beacon_factor;
  3060. if (!new_val)
  3061. new_val = max_beacon_val;
  3062. return new_val;
  3063. }
  3064. int
  3065. il_send_rxon_timing(struct il_priv *il)
  3066. {
  3067. u64 tsf;
  3068. s32 interval_tm, rem;
  3069. struct ieee80211_conf *conf = NULL;
  3070. u16 beacon_int;
  3071. struct ieee80211_vif *vif = il->vif;
  3072. conf = &il->hw->conf;
  3073. lockdep_assert_held(&il->mutex);
  3074. memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
  3075. il->timing.timestamp = cpu_to_le64(il->timestamp);
  3076. il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
  3077. beacon_int = vif ? vif->bss_conf.beacon_int : 0;
  3078. /*
  3079. * TODO: For IBSS we need to get atim_win from mac80211,
  3080. * for now just always use 0
  3081. */
  3082. il->timing.atim_win = 0;
  3083. beacon_int =
  3084. il_adjust_beacon_interval(beacon_int,
  3085. il->hw_params.max_beacon_itrvl *
  3086. TIME_UNIT);
  3087. il->timing.beacon_interval = cpu_to_le16(beacon_int);
  3088. tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
  3089. interval_tm = beacon_int * TIME_UNIT;
  3090. rem = do_div(tsf, interval_tm);
  3091. il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  3092. il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
  3093. D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
  3094. le16_to_cpu(il->timing.beacon_interval),
  3095. le32_to_cpu(il->timing.beacon_init_val),
  3096. le16_to_cpu(il->timing.atim_win));
  3097. return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
  3098. &il->timing);
  3099. }
  3100. EXPORT_SYMBOL(il_send_rxon_timing);
  3101. void
  3102. il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
  3103. {
  3104. struct il_rxon_cmd *rxon = &il->staging;
  3105. if (hw_decrypt)
  3106. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  3107. else
  3108. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  3109. }
  3110. EXPORT_SYMBOL(il_set_rxon_hwcrypto);
  3111. /* validate RXON structure is valid */
  3112. int
  3113. il_check_rxon_cmd(struct il_priv *il)
  3114. {
  3115. struct il_rxon_cmd *rxon = &il->staging;
  3116. bool error = false;
  3117. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  3118. if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
  3119. IL_WARN("check 2.4G: wrong narrow\n");
  3120. error = true;
  3121. }
  3122. if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
  3123. IL_WARN("check 2.4G: wrong radar\n");
  3124. error = true;
  3125. }
  3126. } else {
  3127. if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
  3128. IL_WARN("check 5.2G: not short slot!\n");
  3129. error = true;
  3130. }
  3131. if (rxon->flags & RXON_FLG_CCK_MSK) {
  3132. IL_WARN("check 5.2G: CCK!\n");
  3133. error = true;
  3134. }
  3135. }
  3136. if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
  3137. IL_WARN("mac/bssid mcast!\n");
  3138. error = true;
  3139. }
  3140. /* make sure basic rates 6Mbps and 1Mbps are supported */
  3141. if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
  3142. (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
  3143. IL_WARN("neither 1 nor 6 are basic\n");
  3144. error = true;
  3145. }
  3146. if (le16_to_cpu(rxon->assoc_id) > 2007) {
  3147. IL_WARN("aid > 2007\n");
  3148. error = true;
  3149. }
  3150. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
  3151. (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
  3152. IL_WARN("CCK and short slot\n");
  3153. error = true;
  3154. }
  3155. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
  3156. (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
  3157. IL_WARN("CCK and auto detect");
  3158. error = true;
  3159. }
  3160. if ((rxon->
  3161. flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
  3162. RXON_FLG_TGG_PROTECT_MSK) {
  3163. IL_WARN("TGg but no auto-detect\n");
  3164. error = true;
  3165. }
  3166. if (error)
  3167. IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
  3168. if (error) {
  3169. IL_ERR("Invalid RXON\n");
  3170. return -EINVAL;
  3171. }
  3172. return 0;
  3173. }
  3174. EXPORT_SYMBOL(il_check_rxon_cmd);
  3175. /*
  3176. * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  3177. * @il: staging_rxon is compared to active_rxon
  3178. *
  3179. * If the RXON structure is changing enough to require a new tune,
  3180. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  3181. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  3182. */
  3183. int
  3184. il_full_rxon_required(struct il_priv *il)
  3185. {
  3186. const struct il_rxon_cmd *staging = &il->staging;
  3187. const struct il_rxon_cmd *active = &il->active;
  3188. #define CHK(cond) \
  3189. if ((cond)) { \
  3190. D_INFO("need full RXON - " #cond "\n"); \
  3191. return 1; \
  3192. }
  3193. #define CHK_NEQ(c1, c2) \
  3194. if ((c1) != (c2)) { \
  3195. D_INFO("need full RXON - " \
  3196. #c1 " != " #c2 " - %d != %d\n", \
  3197. (c1), (c2)); \
  3198. return 1; \
  3199. }
  3200. /* These items are only settable from the full RXON command */
  3201. CHK(!il_is_associated(il));
  3202. CHK(!ether_addr_equal_64bits(staging->bssid_addr, active->bssid_addr));
  3203. CHK(!ether_addr_equal_64bits(staging->node_addr, active->node_addr));
  3204. CHK(!ether_addr_equal_64bits(staging->wlap_bssid_addr,
  3205. active->wlap_bssid_addr));
  3206. CHK_NEQ(staging->dev_type, active->dev_type);
  3207. CHK_NEQ(staging->channel, active->channel);
  3208. CHK_NEQ(staging->air_propagation, active->air_propagation);
  3209. CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
  3210. active->ofdm_ht_single_stream_basic_rates);
  3211. CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
  3212. active->ofdm_ht_dual_stream_basic_rates);
  3213. CHK_NEQ(staging->assoc_id, active->assoc_id);
  3214. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  3215. * be updated with the RXON_ASSOC command -- however only some
  3216. * flag transitions are allowed using RXON_ASSOC */
  3217. /* Check if we are not switching bands */
  3218. CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
  3219. active->flags & RXON_FLG_BAND_24G_MSK);
  3220. /* Check if we are switching association toggle */
  3221. CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
  3222. active->filter_flags & RXON_FILTER_ASSOC_MSK);
  3223. #undef CHK
  3224. #undef CHK_NEQ
  3225. return 0;
  3226. }
  3227. EXPORT_SYMBOL(il_full_rxon_required);
  3228. u8
  3229. il_get_lowest_plcp(struct il_priv *il)
  3230. {
  3231. /*
  3232. * Assign the lowest rate -- should really get this from
  3233. * the beacon skb from mac80211.
  3234. */
  3235. if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
  3236. return RATE_1M_PLCP;
  3237. else
  3238. return RATE_6M_PLCP;
  3239. }
  3240. EXPORT_SYMBOL(il_get_lowest_plcp);
  3241. static void
  3242. _il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3243. {
  3244. struct il_rxon_cmd *rxon = &il->staging;
  3245. if (!il->ht.enabled) {
  3246. rxon->flags &=
  3247. ~(RXON_FLG_CHANNEL_MODE_MSK |
  3248. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
  3249. | RXON_FLG_HT_PROT_MSK);
  3250. return;
  3251. }
  3252. rxon->flags |=
  3253. cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
  3254. /* Set up channel bandwidth:
  3255. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  3256. /* clear the HT channel mode before set the mode */
  3257. rxon->flags &=
  3258. ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3259. if (il_is_ht40_tx_allowed(il, NULL)) {
  3260. /* pure ht40 */
  3261. if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  3262. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  3263. /* Note: control channel is opposite of extension channel */
  3264. switch (il->ht.extension_chan_offset) {
  3265. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3266. rxon->flags &=
  3267. ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3268. break;
  3269. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3270. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3271. break;
  3272. }
  3273. } else {
  3274. /* Note: control channel is opposite of extension channel */
  3275. switch (il->ht.extension_chan_offset) {
  3276. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3277. rxon->flags &=
  3278. ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3279. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3280. break;
  3281. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3282. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3283. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3284. break;
  3285. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  3286. default:
  3287. /* channel location only valid if in Mixed mode */
  3288. IL_ERR("invalid extension channel offset\n");
  3289. break;
  3290. }
  3291. }
  3292. } else {
  3293. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  3294. }
  3295. if (il->ops->set_rxon_chain)
  3296. il->ops->set_rxon_chain(il);
  3297. D_ASSOC("rxon flags 0x%X operation mode :0x%X "
  3298. "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
  3299. il->ht.protection, il->ht.extension_chan_offset);
  3300. }
  3301. void
  3302. il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3303. {
  3304. _il_set_rxon_ht(il, ht_conf);
  3305. }
  3306. EXPORT_SYMBOL(il_set_rxon_ht);
  3307. /* Return valid, unused, channel for a passive scan to reset the RF */
  3308. u8
  3309. il_get_single_channel_number(struct il_priv *il, enum nl80211_band band)
  3310. {
  3311. const struct il_channel_info *ch_info;
  3312. int i;
  3313. u8 channel = 0;
  3314. u8 min, max;
  3315. if (band == NL80211_BAND_5GHZ) {
  3316. min = 14;
  3317. max = il->channel_count;
  3318. } else {
  3319. min = 0;
  3320. max = 14;
  3321. }
  3322. for (i = min; i < max; i++) {
  3323. channel = il->channel_info[i].channel;
  3324. if (channel == le16_to_cpu(il->staging.channel))
  3325. continue;
  3326. ch_info = il_get_channel_info(il, band, channel);
  3327. if (il_is_channel_valid(ch_info))
  3328. break;
  3329. }
  3330. return channel;
  3331. }
  3332. EXPORT_SYMBOL(il_get_single_channel_number);
  3333. /*
  3334. * il_set_rxon_channel - Set the band and channel values in staging RXON
  3335. * @ch: requested channel as a pointer to struct ieee80211_channel
  3336. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  3337. * in the staging RXON flag structure based on the ch->band
  3338. */
  3339. int
  3340. il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
  3341. {
  3342. enum nl80211_band band = ch->band;
  3343. u16 channel = ch->hw_value;
  3344. if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
  3345. return 0;
  3346. il->staging.channel = cpu_to_le16(channel);
  3347. if (band == NL80211_BAND_5GHZ)
  3348. il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
  3349. else
  3350. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3351. il->band = band;
  3352. D_INFO("Staging channel set to %d [%d]\n", channel, band);
  3353. return 0;
  3354. }
  3355. EXPORT_SYMBOL(il_set_rxon_channel);
  3356. void
  3357. il_set_flags_for_band(struct il_priv *il, enum nl80211_band band,
  3358. struct ieee80211_vif *vif)
  3359. {
  3360. if (band == NL80211_BAND_5GHZ) {
  3361. il->staging.flags &=
  3362. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
  3363. RXON_FLG_CCK_MSK);
  3364. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3365. } else {
  3366. /* Copied from il_post_associate() */
  3367. if (vif && vif->bss_conf.use_short_slot)
  3368. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3369. else
  3370. il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  3371. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3372. il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
  3373. il->staging.flags &= ~RXON_FLG_CCK_MSK;
  3374. }
  3375. }
  3376. EXPORT_SYMBOL(il_set_flags_for_band);
  3377. /*
  3378. * initialize rxon structure with default values from eeprom
  3379. */
  3380. void
  3381. il_connection_init_rx_config(struct il_priv *il)
  3382. {
  3383. const struct il_channel_info *ch_info;
  3384. memset(&il->staging, 0, sizeof(il->staging));
  3385. switch (il->iw_mode) {
  3386. case NL80211_IFTYPE_UNSPECIFIED:
  3387. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3388. break;
  3389. case NL80211_IFTYPE_STATION:
  3390. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3391. il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  3392. break;
  3393. case NL80211_IFTYPE_ADHOC:
  3394. il->staging.dev_type = RXON_DEV_TYPE_IBSS;
  3395. il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  3396. il->staging.filter_flags =
  3397. RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  3398. break;
  3399. default:
  3400. IL_ERR("Unsupported interface type %d\n", il->vif->type);
  3401. return;
  3402. }
  3403. #if 0
  3404. /* TODO: Figure out when short_preamble would be set and cache from
  3405. * that */
  3406. if (!hw_to_local(il->hw)->short_preamble)
  3407. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  3408. else
  3409. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  3410. #endif
  3411. ch_info =
  3412. il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
  3413. if (!ch_info)
  3414. ch_info = &il->channel_info[0];
  3415. il->staging.channel = cpu_to_le16(ch_info->channel);
  3416. il->band = ch_info->band;
  3417. il_set_flags_for_band(il, il->band, il->vif);
  3418. il->staging.ofdm_basic_rates =
  3419. (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3420. il->staging.cck_basic_rates =
  3421. (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3422. /* clear both MIX and PURE40 mode flag */
  3423. il->staging.flags &=
  3424. ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
  3425. if (il->vif)
  3426. memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
  3427. il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
  3428. il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
  3429. }
  3430. EXPORT_SYMBOL(il_connection_init_rx_config);
  3431. void
  3432. il_set_rate(struct il_priv *il)
  3433. {
  3434. const struct ieee80211_supported_band *hw = NULL;
  3435. struct ieee80211_rate *rate;
  3436. int i;
  3437. hw = il_get_hw_mode(il, il->band);
  3438. if (!hw) {
  3439. IL_ERR("Failed to set rate: unable to get hw mode\n");
  3440. return;
  3441. }
  3442. il->active_rate = 0;
  3443. for (i = 0; i < hw->n_bitrates; i++) {
  3444. rate = &(hw->bitrates[i]);
  3445. if (rate->hw_value < RATE_COUNT_LEGACY)
  3446. il->active_rate |= (1 << rate->hw_value);
  3447. }
  3448. D_RATE("Set active_rate = %0x\n", il->active_rate);
  3449. il->staging.cck_basic_rates =
  3450. (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3451. il->staging.ofdm_basic_rates =
  3452. (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3453. }
  3454. EXPORT_SYMBOL(il_set_rate);
  3455. void
  3456. il_chswitch_done(struct il_priv *il, bool is_success)
  3457. {
  3458. if (test_bit(S_EXIT_PENDING, &il->status))
  3459. return;
  3460. if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3461. ieee80211_chswitch_done(il->vif, is_success);
  3462. }
  3463. EXPORT_SYMBOL(il_chswitch_done);
  3464. void
  3465. il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
  3466. {
  3467. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3468. struct il_csa_notification *csa = &(pkt->u.csa_notif);
  3469. struct il_rxon_cmd *rxon = (void *)&il->active;
  3470. if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3471. return;
  3472. if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
  3473. rxon->channel = csa->channel;
  3474. il->staging.channel = csa->channel;
  3475. D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
  3476. il_chswitch_done(il, true);
  3477. } else {
  3478. IL_ERR("CSA notif (fail) : channel %d\n",
  3479. le16_to_cpu(csa->channel));
  3480. il_chswitch_done(il, false);
  3481. }
  3482. }
  3483. EXPORT_SYMBOL(il_hdl_csa);
  3484. #ifdef CONFIG_IWLEGACY_DEBUG
  3485. void
  3486. il_print_rx_config_cmd(struct il_priv *il)
  3487. {
  3488. struct il_rxon_cmd *rxon = &il->staging;
  3489. D_RADIO("RX CONFIG:\n");
  3490. il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3491. D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3492. D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3493. D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
  3494. D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3495. D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
  3496. D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3497. D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3498. D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3499. D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3500. }
  3501. EXPORT_SYMBOL(il_print_rx_config_cmd);
  3502. #endif
  3503. /*
  3504. * il_irq_handle_error - called for HW or SW error interrupt from card
  3505. */
  3506. void
  3507. il_irq_handle_error(struct il_priv *il)
  3508. {
  3509. /* Set the FW error flag -- cleared on il_down */
  3510. set_bit(S_FW_ERROR, &il->status);
  3511. /* Cancel currently queued command. */
  3512. clear_bit(S_HCMD_ACTIVE, &il->status);
  3513. IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
  3514. il->ops->dump_nic_error_log(il);
  3515. if (il->ops->dump_fh)
  3516. il->ops->dump_fh(il, NULL, false);
  3517. #ifdef CONFIG_IWLEGACY_DEBUG
  3518. if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
  3519. il_print_rx_config_cmd(il);
  3520. #endif
  3521. wake_up(&il->wait_command_queue);
  3522. /* Keep the restart process from trying to send host
  3523. * commands by clearing the INIT status bit */
  3524. clear_bit(S_READY, &il->status);
  3525. if (!test_bit(S_EXIT_PENDING, &il->status)) {
  3526. IL_DBG(IL_DL_FW_ERRORS,
  3527. "Restarting adapter due to uCode error.\n");
  3528. if (il->cfg->mod_params->restart_fw)
  3529. queue_work(il->workqueue, &il->restart);
  3530. }
  3531. }
  3532. EXPORT_SYMBOL(il_irq_handle_error);
  3533. static int
  3534. _il_apm_stop_master(struct il_priv *il)
  3535. {
  3536. int ret = 0;
  3537. /* stop device's busmaster DMA activity */
  3538. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  3539. ret =
  3540. _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  3541. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  3542. if (ret < 0)
  3543. IL_WARN("Master Disable Timed Out, 100 usec\n");
  3544. D_INFO("stop master\n");
  3545. return ret;
  3546. }
  3547. void
  3548. _il_apm_stop(struct il_priv *il)
  3549. {
  3550. lockdep_assert_held(&il->reg_lock);
  3551. D_INFO("Stop card, put in low power state\n");
  3552. /* Stop device's DMA activity */
  3553. _il_apm_stop_master(il);
  3554. /* Reset the entire device */
  3555. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  3556. udelay(10);
  3557. /*
  3558. * Clear "initialization complete" bit to move adapter from
  3559. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  3560. */
  3561. _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3562. }
  3563. EXPORT_SYMBOL(_il_apm_stop);
  3564. void
  3565. il_apm_stop(struct il_priv *il)
  3566. {
  3567. unsigned long flags;
  3568. spin_lock_irqsave(&il->reg_lock, flags);
  3569. _il_apm_stop(il);
  3570. spin_unlock_irqrestore(&il->reg_lock, flags);
  3571. }
  3572. EXPORT_SYMBOL(il_apm_stop);
  3573. /*
  3574. * Start up NIC's basic functionality after it has been reset
  3575. * (e.g. after platform boot, or shutdown via il_apm_stop())
  3576. * NOTE: This does not load uCode nor start the embedded processor
  3577. */
  3578. int
  3579. il_apm_init(struct il_priv *il)
  3580. {
  3581. int ret = 0;
  3582. u16 lctl;
  3583. D_INFO("Init card's basic functions\n");
  3584. /*
  3585. * Use "set_bit" below rather than "write", to preserve any hardware
  3586. * bits already set by default after reset.
  3587. */
  3588. /* Disable L0S exit timer (platform NMI Work/Around) */
  3589. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3590. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  3591. /*
  3592. * Disable L0s without affecting L1;
  3593. * don't wait for ICH L0s (ICH bug W/A)
  3594. */
  3595. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3596. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  3597. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  3598. il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  3599. /*
  3600. * Enable HAP INTA (interrupt from management bus) to
  3601. * wake device's PCI Express link L1a -> L0s
  3602. * NOTE: This is no-op for 3945 (non-existent bit)
  3603. */
  3604. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  3605. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  3606. /*
  3607. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  3608. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  3609. * If so (likely), disable L0S, so device moves directly L0->L1;
  3610. * costs negligible amount of power savings.
  3611. * If not (unlikely), enable L0S, so there is at least some
  3612. * power savings, even without L1.
  3613. */
  3614. if (il->cfg->set_l0s) {
  3615. ret = pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  3616. if (!ret && (lctl & PCI_EXP_LNKCTL_ASPM_L1)) {
  3617. /* L1-ASPM enabled; disable(!) L0S */
  3618. il_set_bit(il, CSR_GIO_REG,
  3619. CSR_GIO_REG_VAL_L0S_ENABLED);
  3620. D_POWER("L1 Enabled; Disabling L0S\n");
  3621. } else {
  3622. /* L1-ASPM disabled; enable(!) L0S */
  3623. il_clear_bit(il, CSR_GIO_REG,
  3624. CSR_GIO_REG_VAL_L0S_ENABLED);
  3625. D_POWER("L1 Disabled; Enabling L0S\n");
  3626. }
  3627. }
  3628. /* Configure analog phase-lock-loop before activating to D0A */
  3629. if (il->cfg->pll_cfg_val)
  3630. il_set_bit(il, CSR_ANA_PLL_CFG,
  3631. il->cfg->pll_cfg_val);
  3632. /*
  3633. * Set "initialization complete" bit to move adapter from
  3634. * D0U* --> D0A* (powered-up active) state.
  3635. */
  3636. il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3637. /*
  3638. * Wait for clock stabilization; once stabilized, access to
  3639. * device-internal resources is supported, e.g. il_wr_prph()
  3640. * and accesses to uCode SRAM.
  3641. */
  3642. ret =
  3643. _il_poll_bit(il, CSR_GP_CNTRL,
  3644. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  3645. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  3646. if (ret < 0) {
  3647. D_INFO("Failed to init the card\n");
  3648. goto out;
  3649. }
  3650. /*
  3651. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  3652. * BSM (Boostrap State Machine) is only in 3945 and 4965.
  3653. *
  3654. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  3655. * do not disable clocks. This preserves any hardware bits already
  3656. * set by default in "CLK_CTRL_REG" after reset.
  3657. */
  3658. if (il->cfg->use_bsm)
  3659. il_wr_prph(il, APMG_CLK_EN_REG,
  3660. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  3661. else
  3662. il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  3663. udelay(20);
  3664. /* Disable L1-Active */
  3665. il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
  3666. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  3667. out:
  3668. return ret;
  3669. }
  3670. EXPORT_SYMBOL(il_apm_init);
  3671. int
  3672. il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
  3673. {
  3674. int ret;
  3675. s8 prev_tx_power;
  3676. bool defer;
  3677. lockdep_assert_held(&il->mutex);
  3678. if (il->tx_power_user_lmt == tx_power && !force)
  3679. return 0;
  3680. if (!il->ops->send_tx_power)
  3681. return -EOPNOTSUPP;
  3682. /* 0 dBm mean 1 milliwatt */
  3683. if (tx_power < 0) {
  3684. IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
  3685. return -EINVAL;
  3686. }
  3687. if (tx_power > il->tx_power_device_lmt) {
  3688. IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
  3689. tx_power, il->tx_power_device_lmt);
  3690. return -EINVAL;
  3691. }
  3692. if (!il_is_ready_rf(il))
  3693. return -EIO;
  3694. /* scan complete and commit_rxon use tx_power_next value,
  3695. * it always need to be updated for newest request */
  3696. il->tx_power_next = tx_power;
  3697. /* do not set tx power when scanning or channel changing */
  3698. defer = test_bit(S_SCANNING, &il->status) ||
  3699. memcmp(&il->active, &il->staging, sizeof(il->staging));
  3700. if (defer && !force) {
  3701. D_INFO("Deferring tx power set\n");
  3702. return 0;
  3703. }
  3704. prev_tx_power = il->tx_power_user_lmt;
  3705. il->tx_power_user_lmt = tx_power;
  3706. ret = il->ops->send_tx_power(il);
  3707. /* if fail to set tx_power, restore the orig. tx power */
  3708. if (ret) {
  3709. il->tx_power_user_lmt = prev_tx_power;
  3710. il->tx_power_next = prev_tx_power;
  3711. }
  3712. return ret;
  3713. }
  3714. EXPORT_SYMBOL(il_set_tx_power);
  3715. void
  3716. il_send_bt_config(struct il_priv *il)
  3717. {
  3718. struct il_bt_cmd bt_cmd = {
  3719. .lead_time = BT_LEAD_TIME_DEF,
  3720. .max_kill = BT_MAX_KILL_DEF,
  3721. .kill_ack_mask = 0,
  3722. .kill_cts_mask = 0,
  3723. };
  3724. if (!bt_coex_active)
  3725. bt_cmd.flags = BT_COEX_DISABLE;
  3726. else
  3727. bt_cmd.flags = BT_COEX_ENABLE;
  3728. D_INFO("BT coex %s\n",
  3729. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  3730. if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
  3731. IL_ERR("failed to send BT Coex Config\n");
  3732. }
  3733. EXPORT_SYMBOL(il_send_bt_config);
  3734. int
  3735. il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
  3736. {
  3737. struct il_stats_cmd stats_cmd = {
  3738. .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
  3739. };
  3740. if (flags & CMD_ASYNC)
  3741. return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
  3742. &stats_cmd, NULL);
  3743. else
  3744. return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
  3745. &stats_cmd);
  3746. }
  3747. EXPORT_SYMBOL(il_send_stats_request);
  3748. void
  3749. il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
  3750. {
  3751. #ifdef CONFIG_IWLEGACY_DEBUG
  3752. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3753. struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3754. D_RX("sleep mode: %d, src: %d\n",
  3755. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3756. #endif
  3757. }
  3758. EXPORT_SYMBOL(il_hdl_pm_sleep);
  3759. void
  3760. il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
  3761. {
  3762. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3763. u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
  3764. D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
  3765. il_get_cmd_string(pkt->hdr.cmd));
  3766. il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
  3767. }
  3768. EXPORT_SYMBOL(il_hdl_pm_debug_stats);
  3769. void
  3770. il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
  3771. {
  3772. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3773. IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
  3774. "seq 0x%04X ser 0x%08X\n",
  3775. le32_to_cpu(pkt->u.err_resp.error_type),
  3776. il_get_cmd_string(pkt->u.err_resp.cmd_id),
  3777. pkt->u.err_resp.cmd_id,
  3778. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3779. le32_to_cpu(pkt->u.err_resp.error_info));
  3780. }
  3781. EXPORT_SYMBOL(il_hdl_error);
  3782. void
  3783. il_clear_isr_stats(struct il_priv *il)
  3784. {
  3785. memset(&il->isr_stats, 0, sizeof(il->isr_stats));
  3786. }
  3787. int
  3788. il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  3789. unsigned int link_id, u16 queue,
  3790. const struct ieee80211_tx_queue_params *params)
  3791. {
  3792. struct il_priv *il = hw->priv;
  3793. unsigned long flags;
  3794. int q;
  3795. D_MAC80211("enter\n");
  3796. if (!il_is_ready_rf(il)) {
  3797. D_MAC80211("leave - RF not ready\n");
  3798. return -EIO;
  3799. }
  3800. if (queue >= AC_NUM) {
  3801. D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  3802. return 0;
  3803. }
  3804. q = AC_NUM - 1 - queue;
  3805. spin_lock_irqsave(&il->lock, flags);
  3806. il->qos_data.def_qos_parm.ac[q].cw_min =
  3807. cpu_to_le16(params->cw_min);
  3808. il->qos_data.def_qos_parm.ac[q].cw_max =
  3809. cpu_to_le16(params->cw_max);
  3810. il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  3811. il->qos_data.def_qos_parm.ac[q].edca_txop =
  3812. cpu_to_le16((params->txop * 32));
  3813. il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  3814. spin_unlock_irqrestore(&il->lock, flags);
  3815. D_MAC80211("leave\n");
  3816. return 0;
  3817. }
  3818. EXPORT_SYMBOL(il_mac_conf_tx);
  3819. int
  3820. il_mac_tx_last_beacon(struct ieee80211_hw *hw)
  3821. {
  3822. struct il_priv *il = hw->priv;
  3823. int ret;
  3824. D_MAC80211("enter\n");
  3825. ret = (il->ibss_manager == IL_IBSS_MANAGER);
  3826. D_MAC80211("leave ret %d\n", ret);
  3827. return ret;
  3828. }
  3829. EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
  3830. static int
  3831. il_set_mode(struct il_priv *il)
  3832. {
  3833. il_connection_init_rx_config(il);
  3834. if (il->ops->set_rxon_chain)
  3835. il->ops->set_rxon_chain(il);
  3836. return il_commit_rxon(il);
  3837. }
  3838. int
  3839. il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3840. {
  3841. struct il_priv *il = hw->priv;
  3842. int err;
  3843. bool reset;
  3844. mutex_lock(&il->mutex);
  3845. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3846. if (!il_is_ready_rf(il)) {
  3847. IL_WARN("Try to add interface when device not ready\n");
  3848. err = -EINVAL;
  3849. goto out;
  3850. }
  3851. /*
  3852. * We do not support multiple virtual interfaces, but on hardware reset
  3853. * we have to add the same interface again.
  3854. */
  3855. reset = (il->vif == vif);
  3856. if (il->vif && !reset) {
  3857. err = -EOPNOTSUPP;
  3858. goto out;
  3859. }
  3860. il->vif = vif;
  3861. il->iw_mode = vif->type;
  3862. err = il_set_mode(il);
  3863. if (err) {
  3864. IL_WARN("Fail to set mode %d\n", vif->type);
  3865. if (!reset) {
  3866. il->vif = NULL;
  3867. il->iw_mode = NL80211_IFTYPE_STATION;
  3868. }
  3869. }
  3870. out:
  3871. D_MAC80211("leave err %d\n", err);
  3872. mutex_unlock(&il->mutex);
  3873. return err;
  3874. }
  3875. EXPORT_SYMBOL(il_mac_add_interface);
  3876. static void
  3877. il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif)
  3878. {
  3879. lockdep_assert_held(&il->mutex);
  3880. if (il->scan_vif == vif) {
  3881. il_scan_cancel_timeout(il, 200);
  3882. il_force_scan_end(il);
  3883. }
  3884. il_set_mode(il);
  3885. }
  3886. void
  3887. il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3888. {
  3889. struct il_priv *il = hw->priv;
  3890. mutex_lock(&il->mutex);
  3891. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3892. WARN_ON(il->vif != vif);
  3893. il->vif = NULL;
  3894. il->iw_mode = NL80211_IFTYPE_UNSPECIFIED;
  3895. il_teardown_interface(il, vif);
  3896. eth_zero_addr(il->bssid);
  3897. D_MAC80211("leave\n");
  3898. mutex_unlock(&il->mutex);
  3899. }
  3900. EXPORT_SYMBOL(il_mac_remove_interface);
  3901. int
  3902. il_alloc_txq_mem(struct il_priv *il)
  3903. {
  3904. if (!il->txq)
  3905. il->txq =
  3906. kcalloc(il->cfg->num_of_queues,
  3907. sizeof(struct il_tx_queue),
  3908. GFP_KERNEL);
  3909. if (!il->txq) {
  3910. IL_ERR("Not enough memory for txq\n");
  3911. return -ENOMEM;
  3912. }
  3913. return 0;
  3914. }
  3915. EXPORT_SYMBOL(il_alloc_txq_mem);
  3916. void
  3917. il_free_txq_mem(struct il_priv *il)
  3918. {
  3919. kfree(il->txq);
  3920. il->txq = NULL;
  3921. }
  3922. EXPORT_SYMBOL(il_free_txq_mem);
  3923. int
  3924. il_force_reset(struct il_priv *il, bool external)
  3925. {
  3926. struct il_force_reset *force_reset;
  3927. if (test_bit(S_EXIT_PENDING, &il->status))
  3928. return -EINVAL;
  3929. force_reset = &il->force_reset;
  3930. force_reset->reset_request_count++;
  3931. if (!external) {
  3932. if (force_reset->last_force_reset_jiffies &&
  3933. time_after(force_reset->last_force_reset_jiffies +
  3934. force_reset->reset_duration, jiffies)) {
  3935. D_INFO("force reset rejected\n");
  3936. force_reset->reset_reject_count++;
  3937. return -EAGAIN;
  3938. }
  3939. }
  3940. force_reset->reset_success_count++;
  3941. force_reset->last_force_reset_jiffies = jiffies;
  3942. /*
  3943. * if the request is from external(ex: debugfs),
  3944. * then always perform the request in regardless the module
  3945. * parameter setting
  3946. * if the request is from internal (uCode error or driver
  3947. * detect failure), then fw_restart module parameter
  3948. * need to be check before performing firmware reload
  3949. */
  3950. if (!external && !il->cfg->mod_params->restart_fw) {
  3951. D_INFO("Cancel firmware reload based on "
  3952. "module parameter setting\n");
  3953. return 0;
  3954. }
  3955. IL_ERR("On demand firmware reload\n");
  3956. /* Set the FW error flag -- cleared on il_down */
  3957. set_bit(S_FW_ERROR, &il->status);
  3958. wake_up(&il->wait_command_queue);
  3959. /*
  3960. * Keep the restart process from trying to send host
  3961. * commands by clearing the INIT status bit
  3962. */
  3963. clear_bit(S_READY, &il->status);
  3964. queue_work(il->workqueue, &il->restart);
  3965. return 0;
  3966. }
  3967. EXPORT_SYMBOL(il_force_reset);
  3968. int
  3969. il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  3970. enum nl80211_iftype newtype, bool newp2p)
  3971. {
  3972. struct il_priv *il = hw->priv;
  3973. int err;
  3974. mutex_lock(&il->mutex);
  3975. D_MAC80211("enter: type %d, addr %pM newtype %d newp2p %d\n",
  3976. vif->type, vif->addr, newtype, newp2p);
  3977. if (newp2p) {
  3978. err = -EOPNOTSUPP;
  3979. goto out;
  3980. }
  3981. if (!il->vif || !il_is_ready_rf(il)) {
  3982. /*
  3983. * Huh? But wait ... this can maybe happen when
  3984. * we're in the middle of a firmware restart!
  3985. */
  3986. err = -EBUSY;
  3987. goto out;
  3988. }
  3989. /* success */
  3990. vif->type = newtype;
  3991. vif->p2p = false;
  3992. il->iw_mode = newtype;
  3993. il_teardown_interface(il, vif);
  3994. err = 0;
  3995. out:
  3996. D_MAC80211("leave err %d\n", err);
  3997. mutex_unlock(&il->mutex);
  3998. return err;
  3999. }
  4000. EXPORT_SYMBOL(il_mac_change_interface);
  4001. void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4002. u32 queues, bool drop)
  4003. {
  4004. struct il_priv *il = hw->priv;
  4005. unsigned long timeout = jiffies + msecs_to_jiffies(500);
  4006. int i;
  4007. mutex_lock(&il->mutex);
  4008. D_MAC80211("enter\n");
  4009. if (il->txq == NULL)
  4010. goto out;
  4011. for (i = 0; i < il->hw_params.max_txq_num; i++) {
  4012. struct il_queue *q;
  4013. if (i == il->cmd_queue)
  4014. continue;
  4015. q = &il->txq[i].q;
  4016. if (q->read_ptr == q->write_ptr)
  4017. continue;
  4018. if (time_after(jiffies, timeout)) {
  4019. IL_ERR("Failed to flush queue %d\n", q->id);
  4020. break;
  4021. }
  4022. msleep(20);
  4023. }
  4024. out:
  4025. D_MAC80211("leave\n");
  4026. mutex_unlock(&il->mutex);
  4027. }
  4028. EXPORT_SYMBOL(il_mac_flush);
  4029. /*
  4030. * On every watchdog tick we check (latest) time stamp. If it does not
  4031. * change during timeout period and queue is not empty we reset firmware.
  4032. */
  4033. static int
  4034. il_check_stuck_queue(struct il_priv *il, int cnt)
  4035. {
  4036. struct il_tx_queue *txq = &il->txq[cnt];
  4037. struct il_queue *q = &txq->q;
  4038. unsigned long timeout;
  4039. unsigned long now = jiffies;
  4040. int ret;
  4041. if (q->read_ptr == q->write_ptr) {
  4042. txq->time_stamp = now;
  4043. return 0;
  4044. }
  4045. timeout =
  4046. txq->time_stamp +
  4047. msecs_to_jiffies(il->cfg->wd_timeout);
  4048. if (time_after(now, timeout)) {
  4049. IL_ERR("Queue %d stuck for %u ms.\n", q->id,
  4050. jiffies_to_msecs(now - txq->time_stamp));
  4051. ret = il_force_reset(il, false);
  4052. return (ret == -EAGAIN) ? 0 : 1;
  4053. }
  4054. return 0;
  4055. }
  4056. /*
  4057. * Making watchdog tick be a quarter of timeout assure we will
  4058. * discover the queue hung between timeout and 1.25*timeout
  4059. */
  4060. #define IL_WD_TICK(timeout) ((timeout) / 4)
  4061. /*
  4062. * Watchdog timer callback, we check each tx queue for stuck, if hung
  4063. * we reset the firmware. If everything is fine just rearm the timer.
  4064. */
  4065. void
  4066. il_bg_watchdog(struct timer_list *t)
  4067. {
  4068. struct il_priv *il = from_timer(il, t, watchdog);
  4069. int cnt;
  4070. unsigned long timeout;
  4071. if (test_bit(S_EXIT_PENDING, &il->status))
  4072. return;
  4073. timeout = il->cfg->wd_timeout;
  4074. if (timeout == 0)
  4075. return;
  4076. /* monitor and check for stuck cmd queue */
  4077. if (il_check_stuck_queue(il, il->cmd_queue))
  4078. return;
  4079. /* monitor and check for other stuck queues */
  4080. for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
  4081. /* skip as we already checked the command queue */
  4082. if (cnt == il->cmd_queue)
  4083. continue;
  4084. if (il_check_stuck_queue(il, cnt))
  4085. return;
  4086. }
  4087. mod_timer(&il->watchdog,
  4088. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4089. }
  4090. EXPORT_SYMBOL(il_bg_watchdog);
  4091. void
  4092. il_setup_watchdog(struct il_priv *il)
  4093. {
  4094. unsigned int timeout = il->cfg->wd_timeout;
  4095. if (timeout)
  4096. mod_timer(&il->watchdog,
  4097. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4098. else
  4099. del_timer(&il->watchdog);
  4100. }
  4101. EXPORT_SYMBOL(il_setup_watchdog);
  4102. /*
  4103. * extended beacon time format
  4104. * time in usec will be changed into a 32-bit value in extended:internal format
  4105. * the extended part is the beacon counts
  4106. * the internal part is the time in usec within one beacon interval
  4107. */
  4108. u32
  4109. il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
  4110. {
  4111. u32 quot;
  4112. u32 rem;
  4113. u32 interval = beacon_interval * TIME_UNIT;
  4114. if (!interval || !usec)
  4115. return 0;
  4116. quot =
  4117. (usec /
  4118. interval) & (il_beacon_time_mask_high(il,
  4119. il->hw_params.
  4120. beacon_time_tsf_bits) >> il->
  4121. hw_params.beacon_time_tsf_bits);
  4122. rem =
  4123. (usec % interval) & il_beacon_time_mask_low(il,
  4124. il->hw_params.
  4125. beacon_time_tsf_bits);
  4126. return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
  4127. }
  4128. EXPORT_SYMBOL(il_usecs_to_beacons);
  4129. /* base is usually what we get from ucode with each received frame,
  4130. * the same as HW timer counter counting down
  4131. */
  4132. __le32
  4133. il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
  4134. u32 beacon_interval)
  4135. {
  4136. u32 base_low = base & il_beacon_time_mask_low(il,
  4137. il->hw_params.
  4138. beacon_time_tsf_bits);
  4139. u32 addon_low = addon & il_beacon_time_mask_low(il,
  4140. il->hw_params.
  4141. beacon_time_tsf_bits);
  4142. u32 interval = beacon_interval * TIME_UNIT;
  4143. u32 res = (base & il_beacon_time_mask_high(il,
  4144. il->hw_params.
  4145. beacon_time_tsf_bits)) +
  4146. (addon & il_beacon_time_mask_high(il,
  4147. il->hw_params.
  4148. beacon_time_tsf_bits));
  4149. if (base_low > addon_low)
  4150. res += base_low - addon_low;
  4151. else if (base_low < addon_low) {
  4152. res += interval + base_low - addon_low;
  4153. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4154. } else
  4155. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4156. return cpu_to_le32(res);
  4157. }
  4158. EXPORT_SYMBOL(il_add_beacon_time);
  4159. #ifdef CONFIG_PM_SLEEP
  4160. static int
  4161. il_pci_suspend(struct device *device)
  4162. {
  4163. struct il_priv *il = dev_get_drvdata(device);
  4164. /*
  4165. * This function is called when system goes into suspend state
  4166. * mac80211 will call il_mac_stop() from the mac80211 suspend function
  4167. * first but since il_mac_stop() has no knowledge of who the caller is,
  4168. * it will not call apm_ops.stop() to stop the DMA operation.
  4169. * Calling apm_ops.stop here to make sure we stop the DMA.
  4170. */
  4171. il_apm_stop(il);
  4172. return 0;
  4173. }
  4174. static int
  4175. il_pci_resume(struct device *device)
  4176. {
  4177. struct pci_dev *pdev = to_pci_dev(device);
  4178. struct il_priv *il = pci_get_drvdata(pdev);
  4179. bool hw_rfkill = false;
  4180. /*
  4181. * We disable the RETRY_TIMEOUT register (0x41) to keep
  4182. * PCI Tx retries from interfering with C3 CPU state.
  4183. */
  4184. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  4185. il_enable_interrupts(il);
  4186. if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4187. hw_rfkill = true;
  4188. if (hw_rfkill)
  4189. set_bit(S_RFKILL, &il->status);
  4190. else
  4191. clear_bit(S_RFKILL, &il->status);
  4192. wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
  4193. return 0;
  4194. }
  4195. SIMPLE_DEV_PM_OPS(il_pm_ops, il_pci_suspend, il_pci_resume);
  4196. EXPORT_SYMBOL(il_pm_ops);
  4197. #endif /* CONFIG_PM_SLEEP */
  4198. static void
  4199. il_update_qos(struct il_priv *il)
  4200. {
  4201. if (test_bit(S_EXIT_PENDING, &il->status))
  4202. return;
  4203. il->qos_data.def_qos_parm.qos_flags = 0;
  4204. if (il->qos_data.qos_active)
  4205. il->qos_data.def_qos_parm.qos_flags |=
  4206. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  4207. if (il->ht.enabled)
  4208. il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  4209. D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  4210. il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
  4211. il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
  4212. &il->qos_data.def_qos_parm, NULL);
  4213. }
  4214. /*
  4215. * il_mac_config - mac80211 config callback
  4216. */
  4217. int
  4218. il_mac_config(struct ieee80211_hw *hw, u32 changed)
  4219. {
  4220. struct il_priv *il = hw->priv;
  4221. const struct il_channel_info *ch_info;
  4222. struct ieee80211_conf *conf = &hw->conf;
  4223. struct ieee80211_channel *channel = conf->chandef.chan;
  4224. struct il_ht_config *ht_conf = &il->current_ht_config;
  4225. unsigned long flags = 0;
  4226. int ret = 0;
  4227. u16 ch;
  4228. int scan_active = 0;
  4229. bool ht_changed = false;
  4230. mutex_lock(&il->mutex);
  4231. D_MAC80211("enter: channel %d changed 0x%X\n", channel->hw_value,
  4232. changed);
  4233. if (unlikely(test_bit(S_SCANNING, &il->status))) {
  4234. scan_active = 1;
  4235. D_MAC80211("scan active\n");
  4236. }
  4237. if (changed &
  4238. (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
  4239. /* mac80211 uses static for non-HT which is what we want */
  4240. il->current_ht_config.smps = conf->smps_mode;
  4241. /*
  4242. * Recalculate chain counts.
  4243. *
  4244. * If monitor mode is enabled then mac80211 will
  4245. * set up the SM PS mode to OFF if an HT channel is
  4246. * configured.
  4247. */
  4248. if (il->ops->set_rxon_chain)
  4249. il->ops->set_rxon_chain(il);
  4250. }
  4251. /* during scanning mac80211 will delay channel setting until
  4252. * scan finish with changed = 0
  4253. */
  4254. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  4255. if (scan_active)
  4256. goto set_ch_out;
  4257. ch = channel->hw_value;
  4258. ch_info = il_get_channel_info(il, channel->band, ch);
  4259. if (!il_is_channel_valid(ch_info)) {
  4260. D_MAC80211("leave - invalid channel\n");
  4261. ret = -EINVAL;
  4262. goto set_ch_out;
  4263. }
  4264. if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
  4265. !il_is_channel_ibss(ch_info)) {
  4266. D_MAC80211("leave - not IBSS channel\n");
  4267. ret = -EINVAL;
  4268. goto set_ch_out;
  4269. }
  4270. spin_lock_irqsave(&il->lock, flags);
  4271. /* Configure HT40 channels */
  4272. if (il->ht.enabled != conf_is_ht(conf)) {
  4273. il->ht.enabled = conf_is_ht(conf);
  4274. ht_changed = true;
  4275. }
  4276. if (il->ht.enabled) {
  4277. if (conf_is_ht40_minus(conf)) {
  4278. il->ht.extension_chan_offset =
  4279. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  4280. il->ht.is_40mhz = true;
  4281. } else if (conf_is_ht40_plus(conf)) {
  4282. il->ht.extension_chan_offset =
  4283. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  4284. il->ht.is_40mhz = true;
  4285. } else {
  4286. il->ht.extension_chan_offset =
  4287. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  4288. il->ht.is_40mhz = false;
  4289. }
  4290. } else
  4291. il->ht.is_40mhz = false;
  4292. /*
  4293. * Default to no protection. Protection mode will
  4294. * later be set from BSS config in il_ht_conf
  4295. */
  4296. il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  4297. /* if we are switching from ht to 2.4 clear flags
  4298. * from any ht related info since 2.4 does not
  4299. * support ht */
  4300. if ((le16_to_cpu(il->staging.channel) != ch))
  4301. il->staging.flags = 0;
  4302. il_set_rxon_channel(il, channel);
  4303. il_set_rxon_ht(il, ht_conf);
  4304. il_set_flags_for_band(il, channel->band, il->vif);
  4305. spin_unlock_irqrestore(&il->lock, flags);
  4306. if (il->ops->update_bcast_stations)
  4307. ret = il->ops->update_bcast_stations(il);
  4308. set_ch_out:
  4309. /* The list of supported rates and rate mask can be different
  4310. * for each band; since the band may have changed, reset
  4311. * the rate mask to what mac80211 lists */
  4312. il_set_rate(il);
  4313. }
  4314. if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
  4315. il->power_data.ps_disabled = !(conf->flags & IEEE80211_CONF_PS);
  4316. if (!il->power_data.ps_disabled)
  4317. IL_WARN_ONCE("Enabling power save might cause firmware crashes\n");
  4318. ret = il_power_update_mode(il, false);
  4319. if (ret)
  4320. D_MAC80211("Error setting sleep level\n");
  4321. }
  4322. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  4323. D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
  4324. conf->power_level);
  4325. il_set_tx_power(il, conf->power_level, false);
  4326. }
  4327. if (!il_is_ready(il)) {
  4328. D_MAC80211("leave - not ready\n");
  4329. goto out;
  4330. }
  4331. if (scan_active)
  4332. goto out;
  4333. if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
  4334. il_commit_rxon(il);
  4335. else
  4336. D_INFO("Not re-sending same RXON configuration.\n");
  4337. if (ht_changed)
  4338. il_update_qos(il);
  4339. out:
  4340. D_MAC80211("leave ret %d\n", ret);
  4341. mutex_unlock(&il->mutex);
  4342. return ret;
  4343. }
  4344. EXPORT_SYMBOL(il_mac_config);
  4345. void
  4346. il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4347. {
  4348. struct il_priv *il = hw->priv;
  4349. unsigned long flags;
  4350. mutex_lock(&il->mutex);
  4351. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  4352. spin_lock_irqsave(&il->lock, flags);
  4353. memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
  4354. /* new association get rid of ibss beacon skb */
  4355. dev_consume_skb_irq(il->beacon_skb);
  4356. il->beacon_skb = NULL;
  4357. il->timestamp = 0;
  4358. spin_unlock_irqrestore(&il->lock, flags);
  4359. il_scan_cancel_timeout(il, 100);
  4360. if (!il_is_ready_rf(il)) {
  4361. D_MAC80211("leave - not ready\n");
  4362. mutex_unlock(&il->mutex);
  4363. return;
  4364. }
  4365. /* we are restarting association process */
  4366. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4367. il_commit_rxon(il);
  4368. il_set_rate(il);
  4369. D_MAC80211("leave\n");
  4370. mutex_unlock(&il->mutex);
  4371. }
  4372. EXPORT_SYMBOL(il_mac_reset_tsf);
  4373. static void
  4374. il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
  4375. {
  4376. struct il_ht_config *ht_conf = &il->current_ht_config;
  4377. struct ieee80211_sta *sta;
  4378. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  4379. D_ASSOC("enter:\n");
  4380. if (!il->ht.enabled)
  4381. return;
  4382. il->ht.protection =
  4383. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  4384. il->ht.non_gf_sta_present =
  4385. !!(bss_conf->
  4386. ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  4387. ht_conf->single_chain_sufficient = false;
  4388. switch (vif->type) {
  4389. case NL80211_IFTYPE_STATION:
  4390. rcu_read_lock();
  4391. sta = ieee80211_find_sta(vif, bss_conf->bssid);
  4392. if (sta) {
  4393. struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap;
  4394. int maxstreams;
  4395. maxstreams =
  4396. (ht_cap->mcs.
  4397. tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  4398. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  4399. maxstreams += 1;
  4400. if (ht_cap->mcs.rx_mask[1] == 0 &&
  4401. ht_cap->mcs.rx_mask[2] == 0)
  4402. ht_conf->single_chain_sufficient = true;
  4403. if (maxstreams <= 1)
  4404. ht_conf->single_chain_sufficient = true;
  4405. } else {
  4406. /*
  4407. * If at all, this can only happen through a race
  4408. * when the AP disconnects us while we're still
  4409. * setting up the connection, in that case mac80211
  4410. * will soon tell us about that.
  4411. */
  4412. ht_conf->single_chain_sufficient = true;
  4413. }
  4414. rcu_read_unlock();
  4415. break;
  4416. case NL80211_IFTYPE_ADHOC:
  4417. ht_conf->single_chain_sufficient = true;
  4418. break;
  4419. default:
  4420. break;
  4421. }
  4422. D_ASSOC("leave\n");
  4423. }
  4424. static inline void
  4425. il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
  4426. {
  4427. /*
  4428. * inform the ucode that there is no longer an
  4429. * association and that no more packets should be
  4430. * sent
  4431. */
  4432. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4433. il->staging.assoc_id = 0;
  4434. il_commit_rxon(il);
  4435. }
  4436. static void
  4437. il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4438. {
  4439. struct il_priv *il = hw->priv;
  4440. unsigned long flags;
  4441. __le64 timestamp;
  4442. struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);
  4443. if (!skb)
  4444. return;
  4445. D_MAC80211("enter\n");
  4446. lockdep_assert_held(&il->mutex);
  4447. if (!il->beacon_enabled) {
  4448. IL_ERR("update beacon with no beaconing enabled\n");
  4449. dev_kfree_skb(skb);
  4450. return;
  4451. }
  4452. spin_lock_irqsave(&il->lock, flags);
  4453. dev_consume_skb_irq(il->beacon_skb);
  4454. il->beacon_skb = skb;
  4455. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  4456. il->timestamp = le64_to_cpu(timestamp);
  4457. D_MAC80211("leave\n");
  4458. spin_unlock_irqrestore(&il->lock, flags);
  4459. if (!il_is_ready_rf(il)) {
  4460. D_MAC80211("leave - RF not ready\n");
  4461. return;
  4462. }
  4463. il->ops->post_associate(il);
  4464. }
  4465. void
  4466. il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4467. struct ieee80211_bss_conf *bss_conf, u64 changes)
  4468. {
  4469. struct il_priv *il = hw->priv;
  4470. int ret;
  4471. mutex_lock(&il->mutex);
  4472. D_MAC80211("enter: changes 0x%llx\n", changes);
  4473. if (!il_is_alive(il)) {
  4474. D_MAC80211("leave - not alive\n");
  4475. mutex_unlock(&il->mutex);
  4476. return;
  4477. }
  4478. if (changes & BSS_CHANGED_QOS) {
  4479. unsigned long flags;
  4480. spin_lock_irqsave(&il->lock, flags);
  4481. il->qos_data.qos_active = bss_conf->qos;
  4482. il_update_qos(il);
  4483. spin_unlock_irqrestore(&il->lock, flags);
  4484. }
  4485. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4486. /* FIXME: can we remove beacon_enabled ? */
  4487. if (vif->bss_conf.enable_beacon)
  4488. il->beacon_enabled = true;
  4489. else
  4490. il->beacon_enabled = false;
  4491. }
  4492. if (changes & BSS_CHANGED_BSSID) {
  4493. D_MAC80211("BSSID %pM\n", bss_conf->bssid);
  4494. /*
  4495. * On passive channel we wait with blocked queues to see if
  4496. * there is traffic on that channel. If no frame will be
  4497. * received (what is very unlikely since scan detects AP on
  4498. * that channel, but theoretically possible), mac80211 associate
  4499. * procedure will time out and mac80211 will call us with NULL
  4500. * bssid. We have to unblock queues on such condition.
  4501. */
  4502. if (is_zero_ether_addr(bss_conf->bssid))
  4503. il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
  4504. /*
  4505. * If there is currently a HW scan going on in the background,
  4506. * then we need to cancel it, otherwise sometimes we are not
  4507. * able to authenticate (FIXME: why ?)
  4508. */
  4509. if (il_scan_cancel_timeout(il, 100)) {
  4510. D_MAC80211("leave - scan abort failed\n");
  4511. mutex_unlock(&il->mutex);
  4512. return;
  4513. }
  4514. /* mac80211 only sets assoc when in STATION mode */
  4515. memcpy(il->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
  4516. /* FIXME: currently needed in a few places */
  4517. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4518. }
  4519. /*
  4520. * This needs to be after setting the BSSID in case
  4521. * mac80211 decides to do both changes at once because
  4522. * it will invoke post_associate.
  4523. */
  4524. if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
  4525. il_beacon_update(hw, vif);
  4526. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  4527. D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
  4528. if (bss_conf->use_short_preamble)
  4529. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4530. else
  4531. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4532. }
  4533. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  4534. D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  4535. if (bss_conf->use_cts_prot && il->band != NL80211_BAND_5GHZ)
  4536. il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
  4537. else
  4538. il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  4539. if (bss_conf->use_cts_prot)
  4540. il->staging.flags |= RXON_FLG_SELF_CTS_EN;
  4541. else
  4542. il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
  4543. }
  4544. if (changes & BSS_CHANGED_BASIC_RATES) {
  4545. /* XXX use this information
  4546. *
  4547. * To do that, remove code from il_set_rate() and put something
  4548. * like this here:
  4549. *
  4550. if (A-band)
  4551. il->staging.ofdm_basic_rates =
  4552. bss_conf->basic_rates;
  4553. else
  4554. il->staging.ofdm_basic_rates =
  4555. bss_conf->basic_rates >> 4;
  4556. il->staging.cck_basic_rates =
  4557. bss_conf->basic_rates & 0xF;
  4558. */
  4559. }
  4560. if (changes & BSS_CHANGED_HT) {
  4561. il_ht_conf(il, vif);
  4562. if (il->ops->set_rxon_chain)
  4563. il->ops->set_rxon_chain(il);
  4564. }
  4565. if (changes & BSS_CHANGED_ASSOC) {
  4566. D_MAC80211("ASSOC %d\n", vif->cfg.assoc);
  4567. if (vif->cfg.assoc) {
  4568. il->timestamp = bss_conf->sync_tsf;
  4569. if (!il_is_rfkill(il))
  4570. il->ops->post_associate(il);
  4571. } else
  4572. il_set_no_assoc(il, vif);
  4573. }
  4574. if (changes && il_is_associated(il) && vif->cfg.aid) {
  4575. D_MAC80211("Changes (%#llx) while associated\n", changes);
  4576. ret = il_send_rxon_assoc(il);
  4577. if (!ret) {
  4578. /* Sync active_rxon with latest change. */
  4579. memcpy((void *)&il->active, &il->staging,
  4580. sizeof(struct il_rxon_cmd));
  4581. }
  4582. }
  4583. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4584. if (vif->bss_conf.enable_beacon) {
  4585. memcpy(il->staging.bssid_addr, bss_conf->bssid,
  4586. ETH_ALEN);
  4587. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4588. il->ops->config_ap(il);
  4589. } else
  4590. il_set_no_assoc(il, vif);
  4591. }
  4592. if (changes & BSS_CHANGED_IBSS) {
  4593. ret = il->ops->manage_ibss_station(il, vif,
  4594. vif->cfg.ibss_joined);
  4595. if (ret)
  4596. IL_ERR("failed to %s IBSS station %pM\n",
  4597. vif->cfg.ibss_joined ? "add" : "remove",
  4598. bss_conf->bssid);
  4599. }
  4600. D_MAC80211("leave\n");
  4601. mutex_unlock(&il->mutex);
  4602. }
  4603. EXPORT_SYMBOL(il_mac_bss_info_changed);
  4604. irqreturn_t
  4605. il_isr(int irq, void *data)
  4606. {
  4607. struct il_priv *il = data;
  4608. u32 inta, inta_mask;
  4609. u32 inta_fh;
  4610. unsigned long flags;
  4611. if (!il)
  4612. return IRQ_NONE;
  4613. spin_lock_irqsave(&il->lock, flags);
  4614. /* Disable (but don't clear!) interrupts here to avoid
  4615. * back-to-back ISRs and sporadic interrupts from our NIC.
  4616. * If we have something to service, the tasklet will re-enable ints.
  4617. * If we *don't* have something, we'll re-enable before leaving here. */
  4618. inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
  4619. _il_wr(il, CSR_INT_MASK, 0x00000000);
  4620. /* Discover which interrupts are active/pending */
  4621. inta = _il_rd(il, CSR_INT);
  4622. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  4623. /* Ignore interrupt if there's nothing in NIC to service.
  4624. * This may be due to IRQ shared with another device,
  4625. * or due to sporadic interrupts thrown from our NIC. */
  4626. if (!inta && !inta_fh) {
  4627. D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4628. goto none;
  4629. }
  4630. if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
  4631. /* Hardware disappeared. It might have already raised
  4632. * an interrupt */
  4633. IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  4634. goto unplugged;
  4635. }
  4636. D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
  4637. inta_fh);
  4638. inta &= ~CSR_INT_BIT_SCD;
  4639. /* il_irq_tasklet() will service interrupts and re-enable them */
  4640. if (likely(inta || inta_fh))
  4641. tasklet_schedule(&il->irq_tasklet);
  4642. unplugged:
  4643. spin_unlock_irqrestore(&il->lock, flags);
  4644. return IRQ_HANDLED;
  4645. none:
  4646. /* re-enable interrupts here since we don't have anything to service. */
  4647. /* only Re-enable if disabled by irq */
  4648. if (test_bit(S_INT_ENABLED, &il->status))
  4649. il_enable_interrupts(il);
  4650. spin_unlock_irqrestore(&il->lock, flags);
  4651. return IRQ_NONE;
  4652. }
  4653. EXPORT_SYMBOL(il_isr);
  4654. /*
  4655. * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
  4656. * function.
  4657. */
  4658. void
  4659. il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
  4660. __le16 fc, __le32 *tx_flags)
  4661. {
  4662. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  4663. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  4664. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  4665. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4666. if (!ieee80211_is_mgmt(fc))
  4667. return;
  4668. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4669. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4670. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4671. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4672. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4673. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4674. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4675. break;
  4676. }
  4677. } else if (info->control.rates[0].
  4678. flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  4679. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4680. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4681. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4682. }
  4683. }
  4684. EXPORT_SYMBOL(il_tx_cmd_protection);