mci.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767
  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. if (list_empty(&mci->info))
  27. return NULL;
  28. list_for_each_entry(entry, &mci->info, list) {
  29. if (entry->conn_handle == info->conn_handle)
  30. return entry;
  31. }
  32. return NULL;
  33. }
  34. static bool ath_mci_add_profile(struct ath_common *common,
  35. struct ath_mci_profile *mci,
  36. struct ath_mci_profile_info *info)
  37. {
  38. struct ath_mci_profile_info *entry;
  39. static const u8 voice_priority[] = { 110, 110, 110, 112, 110, 110, 114, 116, 118 };
  40. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  41. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  42. return false;
  43. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  44. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  45. return false;
  46. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  47. if (!entry)
  48. return false;
  49. memcpy(entry, info, 10);
  50. INC_PROF(mci, info);
  51. list_add_tail(&entry->list, &mci->info);
  52. if (info->type == MCI_GPM_COEX_PROFILE_VOICE) {
  53. if (info->voice_type < sizeof(voice_priority))
  54. mci->voice_priority = voice_priority[info->voice_type];
  55. else
  56. mci->voice_priority = 110;
  57. }
  58. return true;
  59. }
  60. static void ath_mci_del_profile(struct ath_common *common,
  61. struct ath_mci_profile *mci,
  62. struct ath_mci_profile_info *entry)
  63. {
  64. if (!entry)
  65. return;
  66. DEC_PROF(mci, entry);
  67. list_del(&entry->list);
  68. kfree(entry);
  69. }
  70. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  71. {
  72. struct ath_mci_profile_info *info, *tinfo;
  73. mci->aggr_limit = 0;
  74. mci->num_mgmt = 0;
  75. if (list_empty(&mci->info))
  76. return;
  77. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  78. list_del(&info->list);
  79. DEC_PROF(mci, info);
  80. kfree(info);
  81. }
  82. }
  83. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  84. {
  85. struct ath_mci_profile *mci = &btcoex->mci;
  86. u32 wlan_airtime = btcoex->btcoex_period *
  87. (100 - btcoex->duty_cycle) / 100;
  88. /*
  89. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  90. * When wlan_airtime is less than 4ms, aggregation limit has to be
  91. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  92. * without collision with BT traffic.
  93. */
  94. if ((wlan_airtime <= 4) &&
  95. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  96. mci->aggr_limit = 2 * wlan_airtime;
  97. }
  98. static void ath_mci_update_scheme(struct ath_softc *sc)
  99. {
  100. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  101. struct ath_btcoex *btcoex = &sc->btcoex;
  102. struct ath_mci_profile *mci = &btcoex->mci;
  103. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  104. struct ath_mci_profile_info *info;
  105. u32 num_profile = NUM_PROF(mci);
  106. if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
  107. goto skip_tuning;
  108. mci->aggr_limit = 0;
  109. btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
  110. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  111. if (NUM_PROF(mci))
  112. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  113. else
  114. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  115. ATH_BTCOEX_STOMP_LOW;
  116. if (num_profile == 1) {
  117. info = list_first_entry(&mci->info,
  118. struct ath_mci_profile_info,
  119. list);
  120. if (mci->num_sco) {
  121. if (info->T == 12)
  122. mci->aggr_limit = 8;
  123. else if (info->T == 6) {
  124. mci->aggr_limit = 6;
  125. btcoex->duty_cycle = 30;
  126. } else
  127. mci->aggr_limit = 6;
  128. ath_dbg(common, MCI,
  129. "Single SCO, aggregation limit %d 1/4 ms\n",
  130. mci->aggr_limit);
  131. } else if (mci->num_pan || mci->num_other_acl) {
  132. /*
  133. * For single PAN/FTP profile, allocate 35% for BT
  134. * to improve WLAN throughput.
  135. */
  136. btcoex->duty_cycle = AR_SREV_9565(sc->sc_ah) ? 40 : 35;
  137. btcoex->btcoex_period = 53;
  138. ath_dbg(common, MCI,
  139. "Single PAN/FTP bt period %d ms dutycycle %d\n",
  140. btcoex->duty_cycle, btcoex->btcoex_period);
  141. } else if (mci->num_hid) {
  142. btcoex->duty_cycle = 30;
  143. mci->aggr_limit = 6;
  144. ath_dbg(common, MCI,
  145. "Multiple attempt/timeout single HID "
  146. "aggregation limit 1.5 ms dutycycle 30%%\n");
  147. }
  148. } else if (num_profile == 2) {
  149. if (mci->num_hid == 2)
  150. btcoex->duty_cycle = 30;
  151. mci->aggr_limit = 6;
  152. ath_dbg(common, MCI,
  153. "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
  154. btcoex->duty_cycle);
  155. } else if (num_profile >= 3) {
  156. mci->aggr_limit = 4;
  157. ath_dbg(common, MCI,
  158. "Three or more profiles aggregation limit 1 ms\n");
  159. }
  160. skip_tuning:
  161. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  162. if (IS_CHAN_HT(sc->sc_ah->curchan))
  163. ath_mci_adjust_aggr_limit(btcoex);
  164. else
  165. btcoex->btcoex_period >>= 1;
  166. }
  167. ath9k_btcoex_timer_pause(sc);
  168. ath9k_hw_btcoex_disable(sc->sc_ah);
  169. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  170. return;
  171. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
  172. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  173. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  174. btcoex->btcoex_no_stomp = btcoex->btcoex_period *
  175. (100 - btcoex->duty_cycle) / 100;
  176. ath9k_hw_btcoex_enable(sc->sc_ah);
  177. ath9k_btcoex_timer_resume(sc);
  178. }
  179. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  180. {
  181. struct ath_hw *ah = sc->sc_ah;
  182. struct ath_common *common = ath9k_hw_common(ah);
  183. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  184. u32 payload[4] = {0, 0, 0, 0};
  185. switch (opcode) {
  186. case MCI_GPM_BT_CAL_REQ:
  187. if (mci_hw->bt_state == MCI_BT_AWAKE) {
  188. mci_hw->bt_state = MCI_BT_CAL_START;
  189. ath9k_queue_reset(sc, RESET_TYPE_MCI);
  190. }
  191. ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
  192. break;
  193. case MCI_GPM_BT_CAL_GRANT:
  194. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  195. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  196. 16, false, true);
  197. break;
  198. default:
  199. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  200. break;
  201. }
  202. }
  203. static void ath9k_mci_work(struct work_struct *work)
  204. {
  205. struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
  206. ath_mci_update_scheme(sc);
  207. }
  208. static void ath_mci_update_stomp_txprio(u8 cur_txprio, u8 *stomp_prio)
  209. {
  210. if (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_NONE])
  211. stomp_prio[ATH_BTCOEX_STOMP_NONE] = cur_txprio;
  212. if (cur_txprio > stomp_prio[ATH_BTCOEX_STOMP_ALL])
  213. stomp_prio[ATH_BTCOEX_STOMP_ALL] = cur_txprio;
  214. if ((cur_txprio > ATH_MCI_HI_PRIO) &&
  215. (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_LOW]))
  216. stomp_prio[ATH_BTCOEX_STOMP_LOW] = cur_txprio;
  217. }
  218. static void ath_mci_set_concur_txprio(struct ath_softc *sc)
  219. {
  220. struct ath_btcoex *btcoex = &sc->btcoex;
  221. struct ath_mci_profile *mci = &btcoex->mci;
  222. u8 stomp_txprio[ATH_BTCOEX_STOMP_MAX];
  223. memset(stomp_txprio, 0, sizeof(stomp_txprio));
  224. if (mci->num_mgmt) {
  225. stomp_txprio[ATH_BTCOEX_STOMP_ALL] = ATH_MCI_INQUIRY_PRIO;
  226. if (!mci->num_pan && !mci->num_other_acl)
  227. stomp_txprio[ATH_BTCOEX_STOMP_NONE] =
  228. ATH_MCI_INQUIRY_PRIO;
  229. } else {
  230. u8 prof_prio[] = { 50, 90, 94, 52 };/* RFCOMM, A2DP, HID, PAN */
  231. stomp_txprio[ATH_BTCOEX_STOMP_LOW] =
  232. stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0xff;
  233. if (mci->num_sco)
  234. ath_mci_update_stomp_txprio(mci->voice_priority,
  235. stomp_txprio);
  236. if (mci->num_other_acl)
  237. ath_mci_update_stomp_txprio(prof_prio[0], stomp_txprio);
  238. if (mci->num_a2dp)
  239. ath_mci_update_stomp_txprio(prof_prio[1], stomp_txprio);
  240. if (mci->num_hid)
  241. ath_mci_update_stomp_txprio(prof_prio[2], stomp_txprio);
  242. if (mci->num_pan)
  243. ath_mci_update_stomp_txprio(prof_prio[3], stomp_txprio);
  244. if (stomp_txprio[ATH_BTCOEX_STOMP_NONE] == 0xff)
  245. stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0;
  246. if (stomp_txprio[ATH_BTCOEX_STOMP_LOW] == 0xff)
  247. stomp_txprio[ATH_BTCOEX_STOMP_LOW] = 0;
  248. }
  249. ath9k_hw_btcoex_set_concur_txprio(sc->sc_ah, stomp_txprio);
  250. }
  251. static u8 ath_mci_process_profile(struct ath_softc *sc,
  252. struct ath_mci_profile_info *info)
  253. {
  254. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  255. struct ath_btcoex *btcoex = &sc->btcoex;
  256. struct ath_mci_profile *mci = &btcoex->mci;
  257. struct ath_mci_profile_info *entry = NULL;
  258. entry = ath_mci_find_profile(mci, info);
  259. if (entry) {
  260. /*
  261. * Two MCI interrupts are generated while connecting to
  262. * headset and A2DP profile, but only one MCI interrupt
  263. * is generated with last added profile type while disconnecting
  264. * both profiles.
  265. * So while adding second profile type decrement
  266. * the first one.
  267. */
  268. if (entry->type != info->type) {
  269. DEC_PROF(mci, entry);
  270. INC_PROF(mci, info);
  271. }
  272. memcpy(entry, info, 10);
  273. }
  274. if (info->start) {
  275. if (!entry && !ath_mci_add_profile(common, mci, info))
  276. return 0;
  277. } else
  278. ath_mci_del_profile(common, mci, entry);
  279. ath_mci_set_concur_txprio(sc);
  280. return 1;
  281. }
  282. static u8 ath_mci_process_status(struct ath_softc *sc,
  283. struct ath_mci_profile_status *status)
  284. {
  285. struct ath_btcoex *btcoex = &sc->btcoex;
  286. struct ath_mci_profile *mci = &btcoex->mci;
  287. struct ath_mci_profile_info info;
  288. int i = 0, old_num_mgmt = mci->num_mgmt;
  289. /* Link status type are not handled */
  290. if (status->is_link)
  291. return 0;
  292. info.conn_handle = status->conn_handle;
  293. if (ath_mci_find_profile(mci, &info))
  294. return 0;
  295. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  296. return 0;
  297. if (status->is_critical)
  298. __set_bit(status->conn_handle, mci->status);
  299. else
  300. __clear_bit(status->conn_handle, mci->status);
  301. mci->num_mgmt = 0;
  302. do {
  303. if (test_bit(i, mci->status))
  304. mci->num_mgmt++;
  305. } while (++i < ATH_MCI_MAX_PROFILE);
  306. ath_mci_set_concur_txprio(sc);
  307. if (old_num_mgmt != mci->num_mgmt)
  308. return 1;
  309. return 0;
  310. }
  311. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  312. {
  313. struct ath_hw *ah = sc->sc_ah;
  314. struct ath_mci_profile_info profile_info;
  315. struct ath_mci_profile_status profile_status;
  316. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  317. u8 major, minor, update_scheme = 0;
  318. u32 seq_num;
  319. if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
  320. ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
  321. ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
  322. ath_mci_flush_profile(&sc->btcoex.mci);
  323. ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
  324. }
  325. switch (opcode) {
  326. case MCI_GPM_COEX_VERSION_QUERY:
  327. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
  328. break;
  329. case MCI_GPM_COEX_VERSION_RESPONSE:
  330. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  331. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  332. ar9003_mci_set_bt_version(ah, major, minor);
  333. break;
  334. case MCI_GPM_COEX_STATUS_QUERY:
  335. ar9003_mci_send_wlan_channels(ah);
  336. break;
  337. case MCI_GPM_COEX_BT_PROFILE_INFO:
  338. memcpy(&profile_info,
  339. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  340. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  341. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  342. ath_dbg(common, MCI,
  343. "Illegal profile type = %d, state = %d\n",
  344. profile_info.type,
  345. profile_info.start);
  346. break;
  347. }
  348. update_scheme += ath_mci_process_profile(sc, &profile_info);
  349. break;
  350. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  351. profile_status.is_link = *(rx_payload +
  352. MCI_GPM_COEX_B_STATUS_TYPE);
  353. profile_status.conn_handle = *(rx_payload +
  354. MCI_GPM_COEX_B_STATUS_LINKID);
  355. profile_status.is_critical = *(rx_payload +
  356. MCI_GPM_COEX_B_STATUS_STATE);
  357. seq_num = *((u32 *)(rx_payload + 12));
  358. ath_dbg(common, MCI,
  359. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
  360. profile_status.is_link, profile_status.conn_handle,
  361. profile_status.is_critical, seq_num);
  362. update_scheme += ath_mci_process_status(sc, &profile_status);
  363. break;
  364. default:
  365. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  366. break;
  367. }
  368. if (update_scheme)
  369. ieee80211_queue_work(sc->hw, &sc->mci_work);
  370. }
  371. int ath_mci_setup(struct ath_softc *sc)
  372. {
  373. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  374. struct ath_mci_coex *mci = &sc->mci_coex;
  375. struct ath_mci_buf *buf = &mci->sched_buf;
  376. int ret;
  377. buf->bf_addr = dmam_alloc_coherent(sc->dev,
  378. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  379. &buf->bf_paddr, GFP_KERNEL);
  380. if (buf->bf_addr == NULL) {
  381. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  382. return -ENOMEM;
  383. }
  384. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  385. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  386. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  387. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  388. mci->gpm_buf.bf_addr = mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  389. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  390. ret = ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  391. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  392. mci->sched_buf.bf_paddr);
  393. if (ret) {
  394. ath_err(common, "Failed to initialize MCI\n");
  395. return ret;
  396. }
  397. INIT_WORK(&sc->mci_work, ath9k_mci_work);
  398. ath_dbg(common, MCI, "MCI Initialized\n");
  399. return 0;
  400. }
  401. void ath_mci_cleanup(struct ath_softc *sc)
  402. {
  403. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  404. struct ath_hw *ah = sc->sc_ah;
  405. ar9003_mci_cleanup(ah);
  406. ath_dbg(common, MCI, "MCI De-Initialized\n");
  407. }
  408. void ath_mci_intr(struct ath_softc *sc)
  409. {
  410. struct ath_mci_coex *mci = &sc->mci_coex;
  411. struct ath_hw *ah = sc->sc_ah;
  412. struct ath_common *common = ath9k_hw_common(ah);
  413. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  414. u32 mci_int, mci_int_rxmsg;
  415. u32 offset, subtype, opcode;
  416. u32 *pgpm;
  417. u32 more_data = MCI_GPM_MORE;
  418. bool skip_gpm = false;
  419. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  420. if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
  421. ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET);
  422. return;
  423. }
  424. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  425. u32 payload[4] = { 0xffffffff, 0xffffffff,
  426. 0xffffffff, 0xffffff00};
  427. /*
  428. * The following REMOTE_RESET and SYS_WAKING used to sent
  429. * only when BT wake up. Now they are always sent, as a
  430. * recovery method to reset BT MCI's RX alignment.
  431. */
  432. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  433. payload, 16, true, false);
  434. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  435. NULL, 0, true, false);
  436. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  437. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
  438. /*
  439. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  440. */
  441. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  442. }
  443. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  444. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  445. if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
  446. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  447. MCI_BT_SLEEP))
  448. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  449. }
  450. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  451. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  452. if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
  453. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  454. MCI_BT_AWAKE))
  455. mci_hw->bt_state = MCI_BT_SLEEP;
  456. }
  457. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  458. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  459. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
  460. skip_gpm = true;
  461. }
  462. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  463. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  464. ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
  465. }
  466. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  467. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  468. while (more_data == MCI_GPM_MORE) {
  469. if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
  470. return;
  471. pgpm = mci->gpm_buf.bf_addr;
  472. offset = ar9003_mci_get_next_gpm_offset(ah, &more_data);
  473. if (offset == MCI_GPM_INVALID)
  474. break;
  475. pgpm += (offset >> 2);
  476. /*
  477. * The first dword is timer.
  478. * The real data starts from 2nd dword.
  479. */
  480. subtype = MCI_GPM_TYPE(pgpm);
  481. opcode = MCI_GPM_OPCODE(pgpm);
  482. if (skip_gpm)
  483. goto recycle;
  484. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  485. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  486. } else {
  487. switch (subtype) {
  488. case MCI_GPM_COEX_AGENT:
  489. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  490. break;
  491. default:
  492. break;
  493. }
  494. }
  495. recycle:
  496. MCI_GPM_RECYCLE(pgpm);
  497. }
  498. }
  499. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  500. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  501. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  502. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  503. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  504. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  505. int value_dbm = MS(mci_hw->cont_status,
  506. AR_MCI_CONT_RSSI_POWER);
  507. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  508. ath_dbg(common, MCI,
  509. "MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
  510. MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
  511. "tx" : "rx",
  512. MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
  513. value_dbm);
  514. }
  515. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  516. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  517. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  518. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  519. }
  520. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  521. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  522. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  523. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  524. ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
  525. }
  526. }
  527. void ath_mci_enable(struct ath_softc *sc)
  528. {
  529. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  530. if (!common->btcoex_enabled)
  531. return;
  532. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  533. sc->sc_ah->imask |= ATH9K_INT_MCI;
  534. }
  535. void ath9k_mci_update_wlan_channels(struct ath_softc *sc, bool allow_all)
  536. {
  537. struct ath_hw *ah = sc->sc_ah;
  538. struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
  539. struct ath9k_channel *chan = ah->curchan;
  540. u32 channelmap[] = {0x00000000, 0xffff0000, 0xffffffff, 0x7fffffff};
  541. int i;
  542. s16 chan_start, chan_end;
  543. u16 wlan_chan;
  544. if (!chan || !IS_CHAN_2GHZ(chan))
  545. return;
  546. if (allow_all)
  547. goto send_wlan_chan;
  548. wlan_chan = chan->channel - 2402;
  549. chan_start = wlan_chan - 10;
  550. chan_end = wlan_chan + 10;
  551. if (IS_CHAN_HT40PLUS(chan))
  552. chan_end += 20;
  553. else if (IS_CHAN_HT40MINUS(chan))
  554. chan_start -= 20;
  555. /* adjust side band */
  556. chan_start -= 7;
  557. chan_end += 7;
  558. if (chan_start <= 0)
  559. chan_start = 0;
  560. if (chan_end >= ATH_MCI_NUM_BT_CHANNELS)
  561. chan_end = ATH_MCI_NUM_BT_CHANNELS - 1;
  562. ath_dbg(ath9k_hw_common(ah), MCI,
  563. "WLAN current channel %d mask BT channel %d - %d\n",
  564. wlan_chan, chan_start, chan_end);
  565. for (i = chan_start; i < chan_end; i++)
  566. MCI_GPM_CLR_CHANNEL_BIT(&channelmap, i);
  567. send_wlan_chan:
  568. /* update and send wlan channels info to BT */
  569. for (i = 0; i < 4; i++)
  570. mci->wlan_channels[i] = channelmap[i];
  571. ar9003_mci_send_wlan_channels(ah);
  572. ar9003_mci_state(ah, MCI_STATE_SEND_VERSION_QUERY);
  573. }
  574. void ath9k_mci_set_txpower(struct ath_softc *sc, bool setchannel,
  575. bool concur_tx)
  576. {
  577. struct ath_hw *ah = sc->sc_ah;
  578. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  579. bool old_concur_tx = mci_hw->concur_tx;
  580. if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX)) {
  581. mci_hw->concur_tx = false;
  582. return;
  583. }
  584. if (!IS_CHAN_2GHZ(ah->curchan))
  585. return;
  586. if (setchannel) {
  587. struct ath9k_hw_cal_data *caldata = &sc->cur_chan->caldata;
  588. if (IS_CHAN_HT40PLUS(ah->curchan) &&
  589. (ah->curchan->channel > caldata->channel) &&
  590. (ah->curchan->channel <= caldata->channel + 20))
  591. return;
  592. if (IS_CHAN_HT40MINUS(ah->curchan) &&
  593. (ah->curchan->channel < caldata->channel) &&
  594. (ah->curchan->channel >= caldata->channel - 20))
  595. return;
  596. mci_hw->concur_tx = false;
  597. } else
  598. mci_hw->concur_tx = concur_tx;
  599. if (old_concur_tx != mci_hw->concur_tx)
  600. ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
  601. }
  602. static void ath9k_mci_stomp_audio(struct ath_softc *sc)
  603. {
  604. struct ath_hw *ah = sc->sc_ah;
  605. struct ath_btcoex *btcoex = &sc->btcoex;
  606. struct ath_mci_profile *mci = &btcoex->mci;
  607. if (!mci->num_sco && !mci->num_a2dp)
  608. return;
  609. if (ah->stats.avgbrssi > 25) {
  610. btcoex->stomp_audio = 0;
  611. return;
  612. }
  613. btcoex->stomp_audio++;
  614. }
  615. void ath9k_mci_update_rssi(struct ath_softc *sc)
  616. {
  617. struct ath_hw *ah = sc->sc_ah;
  618. struct ath_btcoex *btcoex = &sc->btcoex;
  619. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  620. ath9k_mci_stomp_audio(sc);
  621. if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX))
  622. return;
  623. if (ah->stats.avgbrssi >= 40) {
  624. if (btcoex->rssi_count < 0)
  625. btcoex->rssi_count = 0;
  626. if (++btcoex->rssi_count >= ATH_MCI_CONCUR_TX_SWITCH) {
  627. btcoex->rssi_count = 0;
  628. ath9k_mci_set_txpower(sc, false, true);
  629. }
  630. } else {
  631. if (btcoex->rssi_count > 0)
  632. btcoex->rssi_count = 0;
  633. if (--btcoex->rssi_count <= -ATH_MCI_CONCUR_TX_SWITCH) {
  634. btcoex->rssi_count = 0;
  635. ath9k_mci_set_txpower(sc, false, false);
  636. }
  637. }
  638. }