main.c 68 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  21. u32 queues, bool drop);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
  57. bool sw_pending)
  58. {
  59. bool pending = false;
  60. spin_lock_bh(&txq->axq_lock);
  61. if (txq->axq_depth) {
  62. pending = true;
  63. goto out;
  64. }
  65. if (!sw_pending)
  66. goto out;
  67. if (txq->mac80211_qnum >= 0) {
  68. struct ath_acq *acq;
  69. acq = &sc->cur_chan->acq[txq->mac80211_qnum];
  70. if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
  71. pending = true;
  72. }
  73. out:
  74. spin_unlock_bh(&txq->axq_lock);
  75. return pending;
  76. }
  77. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  78. {
  79. unsigned long flags;
  80. bool ret;
  81. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  82. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  83. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  84. return ret;
  85. }
  86. void ath_ps_full_sleep(struct timer_list *t)
  87. {
  88. struct ath_softc *sc = from_timer(sc, t, sleep_timer);
  89. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  90. unsigned long flags;
  91. bool reset;
  92. spin_lock_irqsave(&common->cc_lock, flags);
  93. ath_hw_cycle_counters_update(common);
  94. spin_unlock_irqrestore(&common->cc_lock, flags);
  95. ath9k_hw_setrxabort(sc->sc_ah, 1);
  96. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  97. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  98. }
  99. void ath9k_ps_wakeup(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. unsigned long flags;
  103. enum ath9k_power_mode power_mode;
  104. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  105. if (++sc->ps_usecount != 1)
  106. goto unlock;
  107. del_timer_sync(&sc->sleep_timer);
  108. power_mode = sc->sc_ah->power_mode;
  109. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  110. /*
  111. * While the hardware is asleep, the cycle counters contain no
  112. * useful data. Better clear them now so that they don't mess up
  113. * survey data results.
  114. */
  115. if (power_mode != ATH9K_PM_AWAKE) {
  116. spin_lock(&common->cc_lock);
  117. ath_hw_cycle_counters_update(common);
  118. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  119. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  120. spin_unlock(&common->cc_lock);
  121. }
  122. unlock:
  123. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  124. }
  125. void ath9k_ps_restore(struct ath_softc *sc)
  126. {
  127. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  128. enum ath9k_power_mode mode;
  129. unsigned long flags;
  130. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  131. if (--sc->ps_usecount != 0)
  132. goto unlock;
  133. if (sc->ps_idle) {
  134. mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
  135. goto unlock;
  136. }
  137. if (sc->ps_enabled &&
  138. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  139. PS_WAIT_FOR_CAB |
  140. PS_WAIT_FOR_PSPOLL_DATA |
  141. PS_WAIT_FOR_TX_ACK |
  142. PS_WAIT_FOR_ANI))) {
  143. mode = ATH9K_PM_NETWORK_SLEEP;
  144. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  145. ath9k_btcoex_stop_gen_timer(sc);
  146. } else {
  147. goto unlock;
  148. }
  149. spin_lock(&common->cc_lock);
  150. ath_hw_cycle_counters_update(common);
  151. spin_unlock(&common->cc_lock);
  152. ath9k_hw_setpower(sc->sc_ah, mode);
  153. unlock:
  154. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  155. }
  156. static void __ath_cancel_work(struct ath_softc *sc)
  157. {
  158. cancel_work_sync(&sc->paprd_work);
  159. cancel_delayed_work_sync(&sc->hw_check_work);
  160. cancel_delayed_work_sync(&sc->hw_pll_work);
  161. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  162. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  163. cancel_work_sync(&sc->mci_work);
  164. #endif
  165. }
  166. void ath_cancel_work(struct ath_softc *sc)
  167. {
  168. __ath_cancel_work(sc);
  169. cancel_work_sync(&sc->hw_reset_work);
  170. }
  171. void ath_restart_work(struct ath_softc *sc)
  172. {
  173. ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
  174. msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
  175. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
  176. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  177. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  178. ath_start_ani(sc);
  179. }
  180. static bool ath_prepare_reset(struct ath_softc *sc)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. bool ret = true;
  184. ieee80211_stop_queues(sc->hw);
  185. ath_stop_ani(sc);
  186. ath9k_hw_disable_interrupts(ah);
  187. if (AR_SREV_9300_20_OR_LATER(ah)) {
  188. ret &= ath_stoprecv(sc);
  189. ret &= ath_drain_all_txq(sc);
  190. } else {
  191. ret &= ath_drain_all_txq(sc);
  192. ret &= ath_stoprecv(sc);
  193. }
  194. return ret;
  195. }
  196. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  197. {
  198. struct ath_hw *ah = sc->sc_ah;
  199. struct ath_common *common = ath9k_hw_common(ah);
  200. unsigned long flags;
  201. ath9k_calculate_summary_state(sc, sc->cur_chan);
  202. ath_startrecv(sc);
  203. ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
  204. sc->cur_chan->txpower,
  205. &sc->cur_chan->cur_txpower);
  206. clear_bit(ATH_OP_HW_RESET, &common->op_flags);
  207. if (!sc->cur_chan->offchannel && start) {
  208. /* restore per chanctx TSF timer */
  209. if (sc->cur_chan->tsf_val) {
  210. u32 offset;
  211. offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
  212. NULL);
  213. ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
  214. }
  215. if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
  216. goto work;
  217. if (ah->opmode == NL80211_IFTYPE_STATION &&
  218. test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
  219. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  220. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  221. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  222. } else {
  223. ath9k_set_beacon(sc);
  224. }
  225. work:
  226. ath_restart_work(sc);
  227. ath_txq_schedule_all(sc);
  228. }
  229. sc->gtt_cnt = 0;
  230. ath9k_hw_set_interrupts(ah);
  231. ath9k_hw_enable_interrupts(ah);
  232. ieee80211_wake_queues(sc->hw);
  233. ath9k_p2p_ps_timer(sc);
  234. return true;
  235. }
  236. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  237. {
  238. struct ath_hw *ah = sc->sc_ah;
  239. struct ath_common *common = ath9k_hw_common(ah);
  240. struct ath9k_hw_cal_data *caldata = NULL;
  241. bool fastcc = true;
  242. int r;
  243. __ath_cancel_work(sc);
  244. disable_irq(sc->irq);
  245. tasklet_disable(&sc->intr_tq);
  246. tasklet_disable(&sc->bcon_tasklet);
  247. spin_lock_bh(&sc->sc_pcu_lock);
  248. if (!sc->cur_chan->offchannel) {
  249. fastcc = false;
  250. caldata = &sc->cur_chan->caldata;
  251. }
  252. if (!hchan) {
  253. fastcc = false;
  254. hchan = ah->curchan;
  255. }
  256. if (!hchan) {
  257. fastcc = false;
  258. hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
  259. }
  260. if (!ath_prepare_reset(sc))
  261. fastcc = false;
  262. if (ath9k_is_chanctx_enabled())
  263. fastcc = false;
  264. spin_lock_bh(&sc->chan_lock);
  265. sc->cur_chandef = sc->cur_chan->chandef;
  266. spin_unlock_bh(&sc->chan_lock);
  267. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  268. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  269. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  270. if (r) {
  271. ath_err(common,
  272. "Unable to reset channel, reset status %d\n", r);
  273. ath9k_hw_enable_interrupts(ah);
  274. ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
  275. goto out;
  276. }
  277. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  278. sc->cur_chan->offchannel)
  279. ath9k_mci_set_txpower(sc, true, false);
  280. if (!ath_complete_reset(sc, true))
  281. r = -EIO;
  282. out:
  283. enable_irq(sc->irq);
  284. spin_unlock_bh(&sc->sc_pcu_lock);
  285. tasklet_enable(&sc->bcon_tasklet);
  286. tasklet_enable(&sc->intr_tq);
  287. return r;
  288. }
  289. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  290. struct ieee80211_vif *vif)
  291. {
  292. struct ath_node *an;
  293. an = (struct ath_node *)sta->drv_priv;
  294. an->sc = sc;
  295. an->sta = sta;
  296. an->vif = vif;
  297. memset(&an->key_idx, 0, sizeof(an->key_idx));
  298. ath_tx_node_init(sc, an);
  299. ath_dynack_node_init(sc->sc_ah, an);
  300. }
  301. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  302. {
  303. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  304. ath_tx_node_cleanup(sc, an);
  305. ath_dynack_node_deinit(sc->sc_ah, an);
  306. }
  307. void ath9k_tasklet(struct tasklet_struct *t)
  308. {
  309. struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
  310. struct ath_hw *ah = sc->sc_ah;
  311. struct ath_common *common = ath9k_hw_common(ah);
  312. enum ath_reset_type type;
  313. unsigned long flags;
  314. u32 status;
  315. u32 rxmask;
  316. spin_lock_irqsave(&sc->intr_lock, flags);
  317. status = sc->intrstatus;
  318. sc->intrstatus = 0;
  319. spin_unlock_irqrestore(&sc->intr_lock, flags);
  320. ath9k_ps_wakeup(sc);
  321. spin_lock(&sc->sc_pcu_lock);
  322. if (status & ATH9K_INT_FATAL) {
  323. type = RESET_TYPE_FATAL_INT;
  324. ath9k_queue_reset(sc, type);
  325. ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
  326. goto out;
  327. }
  328. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  329. (status & ATH9K_INT_BB_WATCHDOG)) {
  330. spin_lock_irqsave(&common->cc_lock, flags);
  331. ath_hw_cycle_counters_update(common);
  332. ar9003_hw_bb_watchdog_dbg_info(ah);
  333. spin_unlock_irqrestore(&common->cc_lock, flags);
  334. if (ar9003_hw_bb_watchdog_check(ah)) {
  335. type = RESET_TYPE_BB_WATCHDOG;
  336. ath9k_queue_reset(sc, type);
  337. ath_dbg(common, RESET,
  338. "BB_WATCHDOG: Skipping interrupts\n");
  339. goto out;
  340. }
  341. }
  342. if (status & ATH9K_INT_GTT) {
  343. sc->gtt_cnt++;
  344. if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
  345. type = RESET_TYPE_TX_GTT;
  346. ath9k_queue_reset(sc, type);
  347. ath_dbg(common, RESET,
  348. "GTT: Skipping interrupts\n");
  349. goto out;
  350. }
  351. }
  352. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  353. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  354. /*
  355. * TSF sync does not look correct; remain awake to sync with
  356. * the next Beacon.
  357. */
  358. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  359. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  360. }
  361. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  362. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  363. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  364. ATH9K_INT_RXORN);
  365. else
  366. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  367. if (status & rxmask) {
  368. /* Check for high priority Rx first */
  369. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  370. (status & ATH9K_INT_RXHP))
  371. ath_rx_tasklet(sc, 0, true);
  372. ath_rx_tasklet(sc, 0, false);
  373. }
  374. if (status & ATH9K_INT_TX) {
  375. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  376. /*
  377. * For EDMA chips, TX completion is enabled for the
  378. * beacon queue, so if a beacon has been transmitted
  379. * successfully after a GTT interrupt, the GTT counter
  380. * gets reset to zero here.
  381. */
  382. sc->gtt_cnt = 0;
  383. ath_tx_edma_tasklet(sc);
  384. } else {
  385. ath_tx_tasklet(sc);
  386. }
  387. wake_up(&sc->tx_wait);
  388. }
  389. if (status & ATH9K_INT_GENTIMER)
  390. ath_gen_timer_isr(sc->sc_ah);
  391. ath9k_btcoex_handle_interrupt(sc, status);
  392. /* re-enable hardware interrupt */
  393. ath9k_hw_resume_interrupts(ah);
  394. out:
  395. spin_unlock(&sc->sc_pcu_lock);
  396. ath9k_ps_restore(sc);
  397. }
  398. irqreturn_t ath_isr(int irq, void *dev)
  399. {
  400. #define SCHED_INTR ( \
  401. ATH9K_INT_FATAL | \
  402. ATH9K_INT_BB_WATCHDOG | \
  403. ATH9K_INT_RXORN | \
  404. ATH9K_INT_RXEOL | \
  405. ATH9K_INT_RX | \
  406. ATH9K_INT_RXLP | \
  407. ATH9K_INT_RXHP | \
  408. ATH9K_INT_TX | \
  409. ATH9K_INT_BMISS | \
  410. ATH9K_INT_CST | \
  411. ATH9K_INT_GTT | \
  412. ATH9K_INT_TSFOOR | \
  413. ATH9K_INT_GENTIMER | \
  414. ATH9K_INT_MCI)
  415. struct ath_softc *sc = dev;
  416. struct ath_hw *ah = sc->sc_ah;
  417. struct ath_common *common = ath9k_hw_common(ah);
  418. enum ath9k_int status;
  419. u32 sync_cause = 0;
  420. bool sched = false;
  421. /*
  422. * The hardware is not ready/present, don't
  423. * touch anything. Note this can happen early
  424. * on if the IRQ is shared.
  425. */
  426. if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
  427. return IRQ_NONE;
  428. /* shared irq, not for us */
  429. if (!ath9k_hw_intrpend(ah))
  430. return IRQ_NONE;
  431. /*
  432. * Figure out the reason(s) for the interrupt. Note
  433. * that the hal returns a pseudo-ISR that may include
  434. * bits we haven't explicitly enabled so we mask the
  435. * value to insure we only process bits we requested.
  436. */
  437. ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
  438. ath9k_debug_sync_cause(sc, sync_cause);
  439. status &= ah->imask; /* discard unasked-for bits */
  440. if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
  441. ath9k_hw_kill_interrupts(sc->sc_ah);
  442. return IRQ_HANDLED;
  443. }
  444. /*
  445. * If there are no status bits set, then this interrupt was not
  446. * for me (should have been caught above).
  447. */
  448. if (!status)
  449. return IRQ_NONE;
  450. /* Cache the status */
  451. spin_lock(&sc->intr_lock);
  452. sc->intrstatus |= status;
  453. spin_unlock(&sc->intr_lock);
  454. if (status & SCHED_INTR)
  455. sched = true;
  456. /*
  457. * If a FATAL interrupt is received, we have to reset the chip
  458. * immediately.
  459. */
  460. if (status & ATH9K_INT_FATAL)
  461. goto chip_reset;
  462. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  463. (status & ATH9K_INT_BB_WATCHDOG))
  464. goto chip_reset;
  465. if (status & ATH9K_INT_SWBA)
  466. tasklet_schedule(&sc->bcon_tasklet);
  467. if (status & ATH9K_INT_TXURN)
  468. ath9k_hw_updatetxtriglevel(ah, true);
  469. if (status & ATH9K_INT_RXEOL) {
  470. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  471. ath9k_hw_set_interrupts(ah);
  472. }
  473. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  474. if (status & ATH9K_INT_TIM_TIMER) {
  475. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  476. goto chip_reset;
  477. /* Clear RxAbort bit so that we can
  478. * receive frames */
  479. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  480. spin_lock(&sc->sc_pm_lock);
  481. ath9k_hw_setrxabort(sc->sc_ah, 0);
  482. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  483. spin_unlock(&sc->sc_pm_lock);
  484. }
  485. chip_reset:
  486. ath_debug_stat_interrupt(sc, status);
  487. if (sched) {
  488. /* turn off every interrupt */
  489. ath9k_hw_kill_interrupts(ah);
  490. tasklet_schedule(&sc->intr_tq);
  491. }
  492. return IRQ_HANDLED;
  493. #undef SCHED_INTR
  494. }
  495. /*
  496. * This function is called when a HW reset cannot be deferred
  497. * and has to be immediate.
  498. */
  499. int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
  500. {
  501. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  502. int r;
  503. ath9k_hw_kill_interrupts(sc->sc_ah);
  504. set_bit(ATH_OP_HW_RESET, &common->op_flags);
  505. ath9k_ps_wakeup(sc);
  506. r = ath_reset_internal(sc, hchan);
  507. ath9k_ps_restore(sc);
  508. return r;
  509. }
  510. /*
  511. * When a HW reset can be deferred, it is added to the
  512. * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
  513. * queueing.
  514. */
  515. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  516. {
  517. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  518. #ifdef CONFIG_ATH9K_DEBUGFS
  519. RESET_STAT_INC(sc, type);
  520. #endif
  521. ath9k_hw_kill_interrupts(sc->sc_ah);
  522. set_bit(ATH_OP_HW_RESET, &common->op_flags);
  523. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  524. }
  525. void ath_reset_work(struct work_struct *work)
  526. {
  527. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  528. ath9k_ps_wakeup(sc);
  529. ath_reset_internal(sc, NULL);
  530. ath9k_ps_restore(sc);
  531. }
  532. /**********************/
  533. /* mac80211 callbacks */
  534. /**********************/
  535. static int ath9k_start(struct ieee80211_hw *hw)
  536. {
  537. struct ath_softc *sc = hw->priv;
  538. struct ath_hw *ah = sc->sc_ah;
  539. struct ath_common *common = ath9k_hw_common(ah);
  540. struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
  541. struct ath_chanctx *ctx = sc->cur_chan;
  542. struct ath9k_channel *init_channel;
  543. int r;
  544. ath_dbg(common, CONFIG,
  545. "Starting driver with initial channel: %d MHz\n",
  546. curchan->center_freq);
  547. ath9k_ps_wakeup(sc);
  548. mutex_lock(&sc->mutex);
  549. init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
  550. sc->cur_chandef = hw->conf.chandef;
  551. /* Reset SERDES registers */
  552. ath9k_hw_configpcipowersave(ah, false);
  553. /*
  554. * The basic interface to setting the hardware in a good
  555. * state is ``reset''. On return the hardware is known to
  556. * be powered up and with interrupts disabled. This must
  557. * be followed by initialization of the appropriate bits
  558. * and then setup of the interrupt mask.
  559. */
  560. spin_lock_bh(&sc->sc_pcu_lock);
  561. atomic_set(&ah->intr_ref_cnt, -1);
  562. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  563. if (r) {
  564. ath_err(common,
  565. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  566. r, curchan->center_freq);
  567. ah->reset_power_on = false;
  568. }
  569. /* Setup our intr mask. */
  570. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  571. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  572. ATH9K_INT_GLOBAL;
  573. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  574. ah->imask |= ATH9K_INT_RXHP |
  575. ATH9K_INT_RXLP;
  576. else
  577. ah->imask |= ATH9K_INT_RX;
  578. if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
  579. ah->imask |= ATH9K_INT_BB_WATCHDOG;
  580. /*
  581. * Enable GTT interrupts only for AR9003/AR9004 chips
  582. * for now.
  583. */
  584. if (AR_SREV_9300_20_OR_LATER(ah))
  585. ah->imask |= ATH9K_INT_GTT;
  586. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  587. ah->imask |= ATH9K_INT_CST;
  588. ath_mci_enable(sc);
  589. clear_bit(ATH_OP_INVALID, &common->op_flags);
  590. sc->sc_ah->is_monitoring = false;
  591. if (!ath_complete_reset(sc, false))
  592. ah->reset_power_on = false;
  593. if (ah->led_pin >= 0) {
  594. ath9k_hw_set_gpio(ah, ah->led_pin,
  595. (ah->config.led_active_high) ? 1 : 0);
  596. ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
  597. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  598. }
  599. /*
  600. * Reset key cache to sane defaults (all entries cleared) instead of
  601. * semi-random values after suspend/resume.
  602. */
  603. ath9k_cmn_init_crypto(sc->sc_ah);
  604. ath9k_hw_reset_tsf(ah);
  605. spin_unlock_bh(&sc->sc_pcu_lock);
  606. ath9k_rng_start(sc);
  607. mutex_unlock(&sc->mutex);
  608. ath9k_ps_restore(sc);
  609. return 0;
  610. }
  611. static void ath9k_tx(struct ieee80211_hw *hw,
  612. struct ieee80211_tx_control *control,
  613. struct sk_buff *skb)
  614. {
  615. struct ath_softc *sc = hw->priv;
  616. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  617. struct ath_tx_control txctl;
  618. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  619. unsigned long flags;
  620. if (sc->ps_enabled) {
  621. /*
  622. * mac80211 does not set PM field for normal data frames, so we
  623. * need to update that based on the current PS mode.
  624. */
  625. if (ieee80211_is_data(hdr->frame_control) &&
  626. !ieee80211_is_nullfunc(hdr->frame_control) &&
  627. !ieee80211_has_pm(hdr->frame_control)) {
  628. ath_dbg(common, PS,
  629. "Add PM=1 for a TX frame while in PS mode\n");
  630. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  631. }
  632. }
  633. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  634. /*
  635. * We are using PS-Poll and mac80211 can request TX while in
  636. * power save mode. Need to wake up hardware for the TX to be
  637. * completed and if needed, also for RX of buffered frames.
  638. */
  639. ath9k_ps_wakeup(sc);
  640. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  641. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  642. ath9k_hw_setrxabort(sc->sc_ah, 0);
  643. if (ieee80211_is_pspoll(hdr->frame_control)) {
  644. ath_dbg(common, PS,
  645. "Sending PS-Poll to pick a buffered frame\n");
  646. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  647. } else {
  648. ath_dbg(common, PS, "Wake up to complete TX\n");
  649. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  650. }
  651. /*
  652. * The actual restore operation will happen only after
  653. * the ps_flags bit is cleared. We are just dropping
  654. * the ps_usecount here.
  655. */
  656. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  657. ath9k_ps_restore(sc);
  658. }
  659. /*
  660. * Cannot tx while the hardware is in full sleep, it first needs a full
  661. * chip reset to recover from that
  662. */
  663. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  664. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  665. goto exit;
  666. }
  667. memset(&txctl, 0, sizeof(struct ath_tx_control));
  668. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  669. txctl.sta = control->sta;
  670. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  671. if (ath_tx_start(hw, skb, &txctl) != 0) {
  672. ath_dbg(common, XMIT, "TX failed\n");
  673. TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
  674. goto exit;
  675. }
  676. return;
  677. exit:
  678. ieee80211_free_txskb(hw, skb);
  679. }
  680. static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
  681. {
  682. struct ath_buf *bf;
  683. struct ieee80211_tx_info *txinfo;
  684. struct ath_frame_info *fi;
  685. list_for_each_entry(bf, txq_list, list) {
  686. if (bf->bf_state.stale || !bf->bf_mpdu)
  687. continue;
  688. txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
  689. fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];
  690. if (fi->keyix == keyix)
  691. return true;
  692. }
  693. return false;
  694. }
  695. static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
  696. {
  697. struct ath_hw *ah = sc->sc_ah;
  698. int i, j;
  699. struct ath_txq *txq;
  700. bool key_in_use = false;
  701. for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
  702. if (!ATH_TXQ_SETUP(sc, i))
  703. continue;
  704. txq = &sc->tx.txq[i];
  705. if (!txq->axq_depth)
  706. continue;
  707. if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
  708. continue;
  709. ath_txq_lock(sc, txq);
  710. key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
  711. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  712. int idx = txq->txq_tailidx;
  713. for (j = 0; !key_in_use &&
  714. !list_empty(&txq->txq_fifo[idx]) &&
  715. j < ATH_TXFIFO_DEPTH; j++) {
  716. key_in_use = ath9k_txq_list_has_key(
  717. &txq->txq_fifo[idx], keyix);
  718. INCR(idx, ATH_TXFIFO_DEPTH);
  719. }
  720. }
  721. ath_txq_unlock(sc, txq);
  722. }
  723. return key_in_use;
  724. }
  725. static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
  726. {
  727. struct ath_hw *ah = sc->sc_ah;
  728. struct ath_common *common = ath9k_hw_common(ah);
  729. if (!test_bit(keyix, ah->pending_del_keymap) ||
  730. ath9k_txq_has_key(sc, keyix))
  731. return;
  732. /* No more TXQ frames point to this key cache entry, so delete it. */
  733. clear_bit(keyix, ah->pending_del_keymap);
  734. ath_key_delete(common, keyix);
  735. }
  736. static void ath9k_stop(struct ieee80211_hw *hw)
  737. {
  738. struct ath_softc *sc = hw->priv;
  739. struct ath_hw *ah = sc->sc_ah;
  740. struct ath_common *common = ath9k_hw_common(ah);
  741. bool prev_idle;
  742. int i;
  743. ath9k_deinit_channel_context(sc);
  744. mutex_lock(&sc->mutex);
  745. ath9k_rng_stop(sc);
  746. ath_cancel_work(sc);
  747. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  748. ath_dbg(common, ANY, "Device not present\n");
  749. mutex_unlock(&sc->mutex);
  750. return;
  751. }
  752. /* Ensure HW is awake when we try to shut it down. */
  753. ath9k_ps_wakeup(sc);
  754. spin_lock_bh(&sc->sc_pcu_lock);
  755. /* prevent tasklets to enable interrupts once we disable them */
  756. ah->imask &= ~ATH9K_INT_GLOBAL;
  757. /* make sure h/w will not generate any interrupt
  758. * before setting the invalid flag. */
  759. ath9k_hw_disable_interrupts(ah);
  760. spin_unlock_bh(&sc->sc_pcu_lock);
  761. /* we can now sync irq and kill any running tasklets, since we already
  762. * disabled interrupts and not holding a spin lock */
  763. synchronize_irq(sc->irq);
  764. tasklet_kill(&sc->intr_tq);
  765. tasklet_kill(&sc->bcon_tasklet);
  766. prev_idle = sc->ps_idle;
  767. sc->ps_idle = true;
  768. spin_lock_bh(&sc->sc_pcu_lock);
  769. if (ah->led_pin >= 0) {
  770. ath9k_hw_set_gpio(ah, ah->led_pin,
  771. (ah->config.led_active_high) ? 0 : 1);
  772. ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
  773. }
  774. ath_prepare_reset(sc);
  775. if (sc->rx.frag) {
  776. dev_kfree_skb_any(sc->rx.frag);
  777. sc->rx.frag = NULL;
  778. }
  779. if (!ah->curchan)
  780. ah->curchan = ath9k_cmn_get_channel(hw, ah,
  781. &sc->cur_chan->chandef);
  782. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  783. set_bit(ATH_OP_INVALID, &common->op_flags);
  784. ath9k_hw_phy_disable(ah);
  785. ath9k_hw_configpcipowersave(ah, true);
  786. spin_unlock_bh(&sc->sc_pcu_lock);
  787. for (i = 0; i < ATH_KEYMAX; i++)
  788. ath9k_pending_key_del(sc, i);
  789. /* Clear key cache entries explicitly to get rid of any potentially
  790. * remaining keys.
  791. */
  792. ath9k_cmn_init_crypto(sc->sc_ah);
  793. ath9k_ps_restore(sc);
  794. sc->ps_idle = prev_idle;
  795. mutex_unlock(&sc->mutex);
  796. ath_dbg(common, CONFIG, "Driver halt\n");
  797. }
  798. static bool ath9k_uses_beacons(int type)
  799. {
  800. switch (type) {
  801. case NL80211_IFTYPE_AP:
  802. case NL80211_IFTYPE_ADHOC:
  803. case NL80211_IFTYPE_MESH_POINT:
  804. return true;
  805. default:
  806. return false;
  807. }
  808. }
  809. static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
  810. struct ieee80211_vif *vif)
  811. {
  812. /* Use the first (configured) interface, but prefering AP interfaces. */
  813. if (!iter_data->primary_beacon_vif) {
  814. iter_data->primary_beacon_vif = vif;
  815. } else {
  816. if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
  817. vif->type == NL80211_IFTYPE_AP)
  818. iter_data->primary_beacon_vif = vif;
  819. }
  820. iter_data->beacons = true;
  821. iter_data->nbcnvifs += 1;
  822. }
  823. static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
  824. u8 *mac, struct ieee80211_vif *vif)
  825. {
  826. struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
  827. int i;
  828. if (iter_data->has_hw_macaddr) {
  829. for (i = 0; i < ETH_ALEN; i++)
  830. iter_data->mask[i] &=
  831. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  832. } else {
  833. memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
  834. iter_data->has_hw_macaddr = true;
  835. }
  836. if (!vif->bss_conf.use_short_slot)
  837. iter_data->slottime = 20;
  838. switch (vif->type) {
  839. case NL80211_IFTYPE_AP:
  840. iter_data->naps++;
  841. if (vif->bss_conf.enable_beacon)
  842. ath9k_vif_iter_set_beacon(iter_data, vif);
  843. break;
  844. case NL80211_IFTYPE_STATION:
  845. iter_data->nstations++;
  846. if (avp->assoc && !iter_data->primary_sta)
  847. iter_data->primary_sta = vif;
  848. break;
  849. case NL80211_IFTYPE_OCB:
  850. iter_data->nocbs++;
  851. break;
  852. case NL80211_IFTYPE_ADHOC:
  853. iter_data->nadhocs++;
  854. if (vif->bss_conf.enable_beacon)
  855. ath9k_vif_iter_set_beacon(iter_data, vif);
  856. break;
  857. case NL80211_IFTYPE_MESH_POINT:
  858. iter_data->nmeshes++;
  859. if (vif->bss_conf.enable_beacon)
  860. ath9k_vif_iter_set_beacon(iter_data, vif);
  861. break;
  862. default:
  863. break;
  864. }
  865. }
  866. static void ath9k_update_bssid_mask(struct ath_softc *sc,
  867. struct ath_chanctx *ctx,
  868. struct ath9k_vif_iter_data *iter_data)
  869. {
  870. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  871. struct ath_vif *avp;
  872. int i;
  873. if (!ath9k_is_chanctx_enabled())
  874. return;
  875. list_for_each_entry(avp, &ctx->vifs, list) {
  876. if (ctx->nvifs_assigned != 1)
  877. continue;
  878. if (!iter_data->has_hw_macaddr)
  879. continue;
  880. ether_addr_copy(common->curbssid, avp->bssid);
  881. /* perm_addr will be used as the p2p device address. */
  882. for (i = 0; i < ETH_ALEN; i++)
  883. iter_data->mask[i] &=
  884. ~(iter_data->hw_macaddr[i] ^
  885. sc->hw->wiphy->perm_addr[i]);
  886. }
  887. }
  888. /* Called with sc->mutex held. */
  889. void ath9k_calculate_iter_data(struct ath_softc *sc,
  890. struct ath_chanctx *ctx,
  891. struct ath9k_vif_iter_data *iter_data)
  892. {
  893. struct ath_vif *avp;
  894. /*
  895. * The hardware will use primary station addr together with the
  896. * BSSID mask when matching addresses.
  897. */
  898. memset(iter_data, 0, sizeof(*iter_data));
  899. eth_broadcast_addr(iter_data->mask);
  900. iter_data->slottime = 9;
  901. list_for_each_entry(avp, &ctx->vifs, list)
  902. ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
  903. ath9k_update_bssid_mask(sc, ctx, iter_data);
  904. }
  905. static void ath9k_set_assoc_state(struct ath_softc *sc,
  906. struct ieee80211_vif *vif, bool changed)
  907. {
  908. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  909. struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
  910. unsigned long flags;
  911. set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  912. ether_addr_copy(common->curbssid, avp->bssid);
  913. common->curaid = avp->aid;
  914. ath9k_hw_write_associd(sc->sc_ah);
  915. if (changed) {
  916. common->last_rssi = ATH_RSSI_DUMMY_MARKER;
  917. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  918. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  919. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  920. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  921. }
  922. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  923. ath9k_mci_update_wlan_channels(sc, false);
  924. ath_dbg(common, CONFIG,
  925. "Primary Station interface: %pM, BSSID: %pM\n",
  926. vif->addr, common->curbssid);
  927. }
  928. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  929. static void ath9k_set_offchannel_state(struct ath_softc *sc)
  930. {
  931. struct ath_hw *ah = sc->sc_ah;
  932. struct ath_common *common = ath9k_hw_common(ah);
  933. struct ieee80211_vif *vif = NULL;
  934. ath9k_ps_wakeup(sc);
  935. if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
  936. vif = sc->offchannel.scan_vif;
  937. else
  938. vif = sc->offchannel.roc_vif;
  939. if (WARN_ON(!vif))
  940. goto exit;
  941. eth_zero_addr(common->curbssid);
  942. eth_broadcast_addr(common->bssidmask);
  943. memcpy(common->macaddr, vif->addr, ETH_ALEN);
  944. common->curaid = 0;
  945. ah->opmode = vif->type;
  946. ah->imask &= ~ATH9K_INT_SWBA;
  947. ah->imask &= ~ATH9K_INT_TSFOOR;
  948. ah->slottime = 9;
  949. ath_hw_setbssidmask(common);
  950. ath9k_hw_setopmode(ah);
  951. ath9k_hw_write_associd(sc->sc_ah);
  952. ath9k_hw_set_interrupts(ah);
  953. ath9k_hw_init_global_settings(ah);
  954. exit:
  955. ath9k_ps_restore(sc);
  956. }
  957. #endif
  958. /* Called with sc->mutex held. */
  959. void ath9k_calculate_summary_state(struct ath_softc *sc,
  960. struct ath_chanctx *ctx)
  961. {
  962. struct ath_hw *ah = sc->sc_ah;
  963. struct ath_common *common = ath9k_hw_common(ah);
  964. struct ath9k_vif_iter_data iter_data;
  965. ath_chanctx_check_active(sc, ctx);
  966. if (ctx != sc->cur_chan)
  967. return;
  968. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  969. if (ctx == &sc->offchannel.chan)
  970. return ath9k_set_offchannel_state(sc);
  971. #endif
  972. ath9k_ps_wakeup(sc);
  973. ath9k_calculate_iter_data(sc, ctx, &iter_data);
  974. if (iter_data.has_hw_macaddr)
  975. memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
  976. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  977. ath_hw_setbssidmask(common);
  978. if (iter_data.naps > 0) {
  979. ath9k_hw_set_tsfadjust(ah, true);
  980. ah->opmode = NL80211_IFTYPE_AP;
  981. } else {
  982. ath9k_hw_set_tsfadjust(ah, false);
  983. if (iter_data.beacons)
  984. ath9k_beacon_ensure_primary_slot(sc);
  985. if (iter_data.nmeshes)
  986. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  987. else if (iter_data.nocbs)
  988. ah->opmode = NL80211_IFTYPE_OCB;
  989. else if (iter_data.nadhocs)
  990. ah->opmode = NL80211_IFTYPE_ADHOC;
  991. else
  992. ah->opmode = NL80211_IFTYPE_STATION;
  993. }
  994. ath9k_hw_setopmode(ah);
  995. ctx->switch_after_beacon = false;
  996. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  997. ah->imask |= ATH9K_INT_TSFOOR;
  998. else {
  999. ah->imask &= ~ATH9K_INT_TSFOOR;
  1000. if (iter_data.naps == 1 && iter_data.beacons)
  1001. ctx->switch_after_beacon = true;
  1002. }
  1003. if (ah->opmode == NL80211_IFTYPE_STATION) {
  1004. bool changed = (iter_data.primary_sta != ctx->primary_sta);
  1005. if (iter_data.primary_sta) {
  1006. iter_data.primary_beacon_vif = iter_data.primary_sta;
  1007. iter_data.beacons = true;
  1008. ath9k_set_assoc_state(sc, iter_data.primary_sta,
  1009. changed);
  1010. ctx->primary_sta = iter_data.primary_sta;
  1011. } else {
  1012. ctx->primary_sta = NULL;
  1013. eth_zero_addr(common->curbssid);
  1014. common->curaid = 0;
  1015. ath9k_hw_write_associd(sc->sc_ah);
  1016. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1017. ath9k_mci_update_wlan_channels(sc, true);
  1018. }
  1019. }
  1020. sc->nbcnvifs = iter_data.nbcnvifs;
  1021. ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
  1022. iter_data.beacons);
  1023. ath9k_hw_set_interrupts(ah);
  1024. if (ah->slottime != iter_data.slottime) {
  1025. ah->slottime = iter_data.slottime;
  1026. ath9k_hw_init_global_settings(ah);
  1027. }
  1028. if (iter_data.primary_sta)
  1029. set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  1030. else
  1031. clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  1032. ath_dbg(common, CONFIG,
  1033. "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
  1034. common->macaddr, common->curbssid, common->bssidmask);
  1035. ath9k_ps_restore(sc);
  1036. }
  1037. static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1038. {
  1039. int *power = data;
  1040. if (vif->bss_conf.txpower == INT_MIN)
  1041. return;
  1042. if (*power < vif->bss_conf.txpower)
  1043. *power = vif->bss_conf.txpower;
  1044. }
  1045. /* Called with sc->mutex held. */
  1046. void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
  1047. {
  1048. int power;
  1049. struct ath_hw *ah = sc->sc_ah;
  1050. struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
  1051. ath9k_ps_wakeup(sc);
  1052. if (ah->tpc_enabled) {
  1053. power = (vif) ? vif->bss_conf.txpower : -1;
  1054. ieee80211_iterate_active_interfaces_atomic(
  1055. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1056. ath9k_tpc_vif_iter, &power);
  1057. if (power == -1)
  1058. power = sc->hw->conf.power_level;
  1059. } else {
  1060. power = sc->hw->conf.power_level;
  1061. }
  1062. sc->cur_chan->txpower = 2 * power;
  1063. ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
  1064. sc->cur_chan->cur_txpower = reg->max_power_level;
  1065. ath9k_ps_restore(sc);
  1066. }
  1067. static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
  1068. struct ieee80211_vif *vif)
  1069. {
  1070. int i;
  1071. if (!ath9k_is_chanctx_enabled())
  1072. return;
  1073. for (i = 0; i < IEEE80211_NUM_ACS; i++)
  1074. vif->hw_queue[i] = i;
  1075. if (vif->type == NL80211_IFTYPE_AP ||
  1076. vif->type == NL80211_IFTYPE_MESH_POINT)
  1077. vif->cab_queue = hw->queues - 2;
  1078. else
  1079. vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
  1080. }
  1081. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1082. struct ieee80211_vif *vif)
  1083. {
  1084. struct ath_softc *sc = hw->priv;
  1085. struct ath_hw *ah = sc->sc_ah;
  1086. struct ath_common *common = ath9k_hw_common(ah);
  1087. struct ath_vif *avp = (void *)vif->drv_priv;
  1088. struct ath_node *an = &avp->mcast_node;
  1089. mutex_lock(&sc->mutex);
  1090. if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
  1091. if (sc->cur_chan->nvifs >= 1) {
  1092. mutex_unlock(&sc->mutex);
  1093. return -EOPNOTSUPP;
  1094. }
  1095. sc->tx99_vif = vif;
  1096. }
  1097. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  1098. sc->cur_chan->nvifs++;
  1099. if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
  1100. vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
  1101. if (ath9k_uses_beacons(vif->type))
  1102. ath9k_beacon_assign_slot(sc, vif);
  1103. avp->vif = vif;
  1104. if (!ath9k_is_chanctx_enabled()) {
  1105. avp->chanctx = sc->cur_chan;
  1106. list_add_tail(&avp->list, &avp->chanctx->vifs);
  1107. }
  1108. ath9k_calculate_summary_state(sc, avp->chanctx);
  1109. ath9k_assign_hw_queues(hw, vif);
  1110. ath9k_set_txpower(sc, vif);
  1111. an->sc = sc;
  1112. an->sta = NULL;
  1113. an->vif = vif;
  1114. an->no_ps_filter = true;
  1115. ath_tx_node_init(sc, an);
  1116. mutex_unlock(&sc->mutex);
  1117. return 0;
  1118. }
  1119. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1120. struct ieee80211_vif *vif,
  1121. enum nl80211_iftype new_type,
  1122. bool p2p)
  1123. {
  1124. struct ath_softc *sc = hw->priv;
  1125. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1126. struct ath_vif *avp = (void *)vif->drv_priv;
  1127. mutex_lock(&sc->mutex);
  1128. if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
  1129. mutex_unlock(&sc->mutex);
  1130. return -EOPNOTSUPP;
  1131. }
  1132. ath_dbg(common, CONFIG, "Change Interface\n");
  1133. if (ath9k_uses_beacons(vif->type))
  1134. ath9k_beacon_remove_slot(sc, vif);
  1135. vif->type = new_type;
  1136. vif->p2p = p2p;
  1137. if (ath9k_uses_beacons(vif->type))
  1138. ath9k_beacon_assign_slot(sc, vif);
  1139. ath9k_assign_hw_queues(hw, vif);
  1140. ath9k_calculate_summary_state(sc, avp->chanctx);
  1141. ath9k_set_txpower(sc, vif);
  1142. mutex_unlock(&sc->mutex);
  1143. return 0;
  1144. }
  1145. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1146. struct ieee80211_vif *vif)
  1147. {
  1148. struct ath_softc *sc = hw->priv;
  1149. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1150. struct ath_vif *avp = (void *)vif->drv_priv;
  1151. ath_dbg(common, CONFIG, "Detach Interface\n");
  1152. mutex_lock(&sc->mutex);
  1153. ath9k_p2p_remove_vif(sc, vif);
  1154. sc->cur_chan->nvifs--;
  1155. sc->tx99_vif = NULL;
  1156. if (!ath9k_is_chanctx_enabled())
  1157. list_del(&avp->list);
  1158. if (ath9k_uses_beacons(vif->type))
  1159. ath9k_beacon_remove_slot(sc, vif);
  1160. ath_tx_node_cleanup(sc, &avp->mcast_node);
  1161. ath9k_calculate_summary_state(sc, avp->chanctx);
  1162. ath9k_set_txpower(sc, NULL);
  1163. mutex_unlock(&sc->mutex);
  1164. }
  1165. static void ath9k_enable_ps(struct ath_softc *sc)
  1166. {
  1167. struct ath_hw *ah = sc->sc_ah;
  1168. struct ath_common *common = ath9k_hw_common(ah);
  1169. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1170. return;
  1171. sc->ps_enabled = true;
  1172. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1173. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1174. ah->imask |= ATH9K_INT_TIM_TIMER;
  1175. ath9k_hw_set_interrupts(ah);
  1176. }
  1177. ath9k_hw_setrxabort(ah, 1);
  1178. }
  1179. ath_dbg(common, PS, "PowerSave enabled\n");
  1180. }
  1181. static void ath9k_disable_ps(struct ath_softc *sc)
  1182. {
  1183. struct ath_hw *ah = sc->sc_ah;
  1184. struct ath_common *common = ath9k_hw_common(ah);
  1185. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1186. return;
  1187. sc->ps_enabled = false;
  1188. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1189. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1190. ath9k_hw_setrxabort(ah, 0);
  1191. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1192. PS_WAIT_FOR_CAB |
  1193. PS_WAIT_FOR_PSPOLL_DATA |
  1194. PS_WAIT_FOR_TX_ACK);
  1195. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1196. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1197. ath9k_hw_set_interrupts(ah);
  1198. }
  1199. }
  1200. ath_dbg(common, PS, "PowerSave disabled\n");
  1201. }
  1202. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1203. {
  1204. struct ath_softc *sc = hw->priv;
  1205. struct ath_hw *ah = sc->sc_ah;
  1206. struct ath_common *common = ath9k_hw_common(ah);
  1207. struct ieee80211_conf *conf = &hw->conf;
  1208. struct ath_chanctx *ctx = sc->cur_chan;
  1209. ath9k_ps_wakeup(sc);
  1210. mutex_lock(&sc->mutex);
  1211. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1212. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1213. if (sc->ps_idle) {
  1214. ath_cancel_work(sc);
  1215. ath9k_stop_btcoex(sc);
  1216. } else {
  1217. ath9k_start_btcoex(sc);
  1218. /*
  1219. * The chip needs a reset to properly wake up from
  1220. * full sleep
  1221. */
  1222. ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
  1223. }
  1224. }
  1225. /*
  1226. * We just prepare to enable PS. We have to wait until our AP has
  1227. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1228. * those ACKs and end up retransmitting the same null data frames.
  1229. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1230. */
  1231. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1232. unsigned long flags;
  1233. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1234. if (conf->flags & IEEE80211_CONF_PS)
  1235. ath9k_enable_ps(sc);
  1236. else
  1237. ath9k_disable_ps(sc);
  1238. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1239. }
  1240. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1241. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1242. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1243. sc->sc_ah->is_monitoring = true;
  1244. } else {
  1245. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1246. sc->sc_ah->is_monitoring = false;
  1247. }
  1248. }
  1249. if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  1250. ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
  1251. ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
  1252. }
  1253. if (changed & IEEE80211_CONF_CHANGE_POWER)
  1254. ath9k_set_txpower(sc, NULL);
  1255. mutex_unlock(&sc->mutex);
  1256. ath9k_ps_restore(sc);
  1257. return 0;
  1258. }
  1259. #define SUPPORTED_FILTERS \
  1260. (FIF_ALLMULTI | \
  1261. FIF_CONTROL | \
  1262. FIF_PSPOLL | \
  1263. FIF_OTHER_BSS | \
  1264. FIF_BCN_PRBRESP_PROMISC | \
  1265. FIF_PROBE_REQ | \
  1266. FIF_MCAST_ACTION | \
  1267. FIF_FCSFAIL)
  1268. /* FIXME: sc->sc_full_reset ? */
  1269. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1270. unsigned int changed_flags,
  1271. unsigned int *total_flags,
  1272. u64 multicast)
  1273. {
  1274. struct ath_softc *sc = hw->priv;
  1275. struct ath_chanctx *ctx;
  1276. u32 rfilt;
  1277. changed_flags &= SUPPORTED_FILTERS;
  1278. *total_flags &= SUPPORTED_FILTERS;
  1279. spin_lock_bh(&sc->chan_lock);
  1280. ath_for_each_chanctx(sc, ctx)
  1281. ctx->rxfilter = *total_flags;
  1282. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  1283. sc->offchannel.chan.rxfilter = *total_flags;
  1284. #endif
  1285. spin_unlock_bh(&sc->chan_lock);
  1286. ath9k_ps_wakeup(sc);
  1287. rfilt = ath_calcrxfilter(sc);
  1288. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1289. ath9k_ps_restore(sc);
  1290. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1291. rfilt);
  1292. }
  1293. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1294. struct ieee80211_vif *vif,
  1295. struct ieee80211_sta *sta)
  1296. {
  1297. struct ath_softc *sc = hw->priv;
  1298. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1299. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1300. struct ieee80211_key_conf ps_key = { };
  1301. int key;
  1302. ath_node_attach(sc, sta, vif);
  1303. if (vif->type != NL80211_IFTYPE_AP &&
  1304. vif->type != NL80211_IFTYPE_AP_VLAN)
  1305. return 0;
  1306. key = ath_key_config(common, vif, sta, &ps_key);
  1307. if (key > 0) {
  1308. an->ps_key = key;
  1309. an->key_idx[0] = key;
  1310. }
  1311. return 0;
  1312. }
  1313. static void ath9k_del_ps_key(struct ath_softc *sc,
  1314. struct ieee80211_vif *vif,
  1315. struct ieee80211_sta *sta)
  1316. {
  1317. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1318. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1319. if (!an->ps_key)
  1320. return;
  1321. ath_key_delete(common, an->ps_key);
  1322. an->ps_key = 0;
  1323. an->key_idx[0] = 0;
  1324. }
  1325. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1326. struct ieee80211_vif *vif,
  1327. struct ieee80211_sta *sta)
  1328. {
  1329. struct ath_softc *sc = hw->priv;
  1330. ath9k_del_ps_key(sc, vif, sta);
  1331. ath_node_detach(sc, sta);
  1332. return 0;
  1333. }
  1334. static int ath9k_sta_state(struct ieee80211_hw *hw,
  1335. struct ieee80211_vif *vif,
  1336. struct ieee80211_sta *sta,
  1337. enum ieee80211_sta_state old_state,
  1338. enum ieee80211_sta_state new_state)
  1339. {
  1340. struct ath_softc *sc = hw->priv;
  1341. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1342. int ret = 0;
  1343. if (old_state == IEEE80211_STA_NOTEXIST &&
  1344. new_state == IEEE80211_STA_NONE) {
  1345. ret = ath9k_sta_add(hw, vif, sta);
  1346. ath_dbg(common, CONFIG,
  1347. "Add station: %pM\n", sta->addr);
  1348. } else if (old_state == IEEE80211_STA_NONE &&
  1349. new_state == IEEE80211_STA_NOTEXIST) {
  1350. ret = ath9k_sta_remove(hw, vif, sta);
  1351. ath_dbg(common, CONFIG,
  1352. "Remove station: %pM\n", sta->addr);
  1353. }
  1354. if (ath9k_is_chanctx_enabled()) {
  1355. if (vif->type == NL80211_IFTYPE_STATION) {
  1356. if (old_state == IEEE80211_STA_ASSOC &&
  1357. new_state == IEEE80211_STA_AUTHORIZED)
  1358. ath_chanctx_event(sc, vif,
  1359. ATH_CHANCTX_EVENT_AUTHORIZED);
  1360. }
  1361. }
  1362. return ret;
  1363. }
  1364. static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
  1365. struct ath_node *an,
  1366. bool set)
  1367. {
  1368. int i;
  1369. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1370. if (!an->key_idx[i])
  1371. continue;
  1372. ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
  1373. }
  1374. }
  1375. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1376. struct ieee80211_vif *vif,
  1377. enum sta_notify_cmd cmd,
  1378. struct ieee80211_sta *sta)
  1379. {
  1380. struct ath_softc *sc = hw->priv;
  1381. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1382. switch (cmd) {
  1383. case STA_NOTIFY_SLEEP:
  1384. an->sleeping = true;
  1385. ath_tx_aggr_sleep(sta, sc, an);
  1386. ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
  1387. break;
  1388. case STA_NOTIFY_AWAKE:
  1389. ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
  1390. an->sleeping = false;
  1391. ath_tx_aggr_wakeup(sc, an);
  1392. break;
  1393. }
  1394. }
  1395. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1396. struct ieee80211_vif *vif,
  1397. unsigned int link_id, u16 queue,
  1398. const struct ieee80211_tx_queue_params *params)
  1399. {
  1400. struct ath_softc *sc = hw->priv;
  1401. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1402. struct ath_txq *txq;
  1403. struct ath9k_tx_queue_info qi;
  1404. int ret = 0;
  1405. if (queue >= IEEE80211_NUM_ACS)
  1406. return 0;
  1407. txq = sc->tx.txq_map[queue];
  1408. ath9k_ps_wakeup(sc);
  1409. mutex_lock(&sc->mutex);
  1410. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1411. qi.tqi_aifs = params->aifs;
  1412. qi.tqi_cwmin = params->cw_min;
  1413. qi.tqi_cwmax = params->cw_max;
  1414. qi.tqi_burstTime = params->txop * 32;
  1415. ath_dbg(common, CONFIG,
  1416. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1417. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1418. params->cw_max, params->txop);
  1419. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1420. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1421. if (ret)
  1422. ath_err(common, "TXQ Update failed\n");
  1423. mutex_unlock(&sc->mutex);
  1424. ath9k_ps_restore(sc);
  1425. return ret;
  1426. }
  1427. static int ath9k_set_key(struct ieee80211_hw *hw,
  1428. enum set_key_cmd cmd,
  1429. struct ieee80211_vif *vif,
  1430. struct ieee80211_sta *sta,
  1431. struct ieee80211_key_conf *key)
  1432. {
  1433. struct ath_softc *sc = hw->priv;
  1434. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1435. struct ath_node *an = NULL;
  1436. int ret = 0, i;
  1437. if (ath9k_modparam_nohwcrypt)
  1438. return -ENOSPC;
  1439. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1440. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1441. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1442. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1443. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1444. /*
  1445. * For now, disable hw crypto for the RSN IBSS group keys. This
  1446. * could be optimized in the future to use a modified key cache
  1447. * design to support per-STA RX GTK, but until that gets
  1448. * implemented, use of software crypto for group addressed
  1449. * frames is a acceptable to allow RSN IBSS to be used.
  1450. */
  1451. return -EOPNOTSUPP;
  1452. }
  1453. /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
  1454. * make sure these are not send unencrypted or with a wrong (new) key
  1455. */
  1456. if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
  1457. ieee80211_stop_queues(hw);
  1458. ath9k_flush(hw, vif, 0, true);
  1459. ieee80211_wake_queues(hw);
  1460. }
  1461. mutex_lock(&sc->mutex);
  1462. ath9k_ps_wakeup(sc);
  1463. ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
  1464. if (sta)
  1465. an = (struct ath_node *)sta->drv_priv;
  1466. /* Delete pending key cache entries if no more frames are pointing to
  1467. * them in TXQs.
  1468. */
  1469. for (i = 0; i < ATH_KEYMAX; i++)
  1470. ath9k_pending_key_del(sc, i);
  1471. switch (cmd) {
  1472. case SET_KEY:
  1473. if (sta)
  1474. ath9k_del_ps_key(sc, vif, sta);
  1475. key->hw_key_idx = 0;
  1476. ret = ath_key_config(common, vif, sta, key);
  1477. if (ret >= 0) {
  1478. key->hw_key_idx = ret;
  1479. /* push IV and Michael MIC generation to stack */
  1480. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1481. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1482. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1483. if (sc->sc_ah->sw_mgmt_crypto_tx &&
  1484. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1485. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1486. ret = 0;
  1487. }
  1488. if (an && key->hw_key_idx) {
  1489. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1490. if (an->key_idx[i])
  1491. continue;
  1492. an->key_idx[i] = key->hw_key_idx;
  1493. break;
  1494. }
  1495. WARN_ON(i == ARRAY_SIZE(an->key_idx));
  1496. }
  1497. break;
  1498. case DISABLE_KEY:
  1499. if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
  1500. /* Delay key cache entry deletion until there are no
  1501. * remaining TXQ frames pointing to this entry.
  1502. */
  1503. set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
  1504. ath_hw_keysetmac(common, key->hw_key_idx, NULL);
  1505. } else {
  1506. ath_key_delete(common, key->hw_key_idx);
  1507. }
  1508. if (an) {
  1509. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1510. if (an->key_idx[i] != key->hw_key_idx)
  1511. continue;
  1512. an->key_idx[i] = 0;
  1513. break;
  1514. }
  1515. }
  1516. key->hw_key_idx = 0;
  1517. break;
  1518. default:
  1519. ret = -EINVAL;
  1520. }
  1521. ath9k_ps_restore(sc);
  1522. mutex_unlock(&sc->mutex);
  1523. return ret;
  1524. }
  1525. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1526. struct ieee80211_vif *vif,
  1527. struct ieee80211_bss_conf *bss_conf,
  1528. u64 changed)
  1529. {
  1530. #define CHECK_ANI \
  1531. (BSS_CHANGED_ASSOC | \
  1532. BSS_CHANGED_IBSS | \
  1533. BSS_CHANGED_BEACON_ENABLED)
  1534. struct ath_softc *sc = hw->priv;
  1535. struct ath_hw *ah = sc->sc_ah;
  1536. struct ath_common *common = ath9k_hw_common(ah);
  1537. struct ath_vif *avp = (void *)vif->drv_priv;
  1538. int slottime;
  1539. ath9k_ps_wakeup(sc);
  1540. mutex_lock(&sc->mutex);
  1541. if (changed & BSS_CHANGED_ASSOC) {
  1542. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1543. bss_conf->bssid, vif->cfg.assoc);
  1544. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1545. avp->aid = vif->cfg.aid;
  1546. avp->assoc = vif->cfg.assoc;
  1547. ath9k_calculate_summary_state(sc, avp->chanctx);
  1548. }
  1549. if ((changed & BSS_CHANGED_IBSS) ||
  1550. (changed & BSS_CHANGED_OCB)) {
  1551. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1552. common->curaid = vif->cfg.aid;
  1553. ath9k_hw_write_associd(sc->sc_ah);
  1554. }
  1555. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1556. (changed & BSS_CHANGED_BEACON_INT) ||
  1557. (changed & BSS_CHANGED_BEACON_INFO)) {
  1558. ath9k_calculate_summary_state(sc, avp->chanctx);
  1559. }
  1560. if ((avp->chanctx == sc->cur_chan) &&
  1561. (changed & BSS_CHANGED_ERP_SLOT)) {
  1562. if (bss_conf->use_short_slot)
  1563. slottime = 9;
  1564. else
  1565. slottime = 20;
  1566. if (vif->type == NL80211_IFTYPE_AP) {
  1567. /*
  1568. * Defer update, so that connected stations can adjust
  1569. * their settings at the same time.
  1570. * See beacon.c for more details
  1571. */
  1572. sc->beacon.slottime = slottime;
  1573. sc->beacon.updateslot = UPDATE;
  1574. } else {
  1575. ah->slottime = slottime;
  1576. ath9k_hw_init_global_settings(ah);
  1577. }
  1578. }
  1579. if (changed & BSS_CHANGED_P2P_PS)
  1580. ath9k_p2p_bss_info_changed(sc, vif);
  1581. if (changed & CHECK_ANI)
  1582. ath_check_ani(sc);
  1583. if (changed & BSS_CHANGED_TXPOWER) {
  1584. ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
  1585. vif->addr, bss_conf->txpower, bss_conf->txpower_type);
  1586. ath9k_set_txpower(sc, vif);
  1587. }
  1588. mutex_unlock(&sc->mutex);
  1589. ath9k_ps_restore(sc);
  1590. #undef CHECK_ANI
  1591. }
  1592. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1593. {
  1594. struct ath_softc *sc = hw->priv;
  1595. struct ath_vif *avp = (void *)vif->drv_priv;
  1596. u64 tsf;
  1597. mutex_lock(&sc->mutex);
  1598. ath9k_ps_wakeup(sc);
  1599. /* Get current TSF either from HW or kernel time. */
  1600. if (sc->cur_chan == avp->chanctx) {
  1601. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1602. } else {
  1603. tsf = sc->cur_chan->tsf_val +
  1604. ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
  1605. }
  1606. tsf += le64_to_cpu(avp->tsf_adjust);
  1607. ath9k_ps_restore(sc);
  1608. mutex_unlock(&sc->mutex);
  1609. return tsf;
  1610. }
  1611. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1612. struct ieee80211_vif *vif,
  1613. u64 tsf)
  1614. {
  1615. struct ath_softc *sc = hw->priv;
  1616. struct ath_vif *avp = (void *)vif->drv_priv;
  1617. mutex_lock(&sc->mutex);
  1618. ath9k_ps_wakeup(sc);
  1619. tsf -= le64_to_cpu(avp->tsf_adjust);
  1620. ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
  1621. if (sc->cur_chan == avp->chanctx)
  1622. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1623. avp->chanctx->tsf_val = tsf;
  1624. ath9k_ps_restore(sc);
  1625. mutex_unlock(&sc->mutex);
  1626. }
  1627. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1628. {
  1629. struct ath_softc *sc = hw->priv;
  1630. struct ath_vif *avp = (void *)vif->drv_priv;
  1631. mutex_lock(&sc->mutex);
  1632. ath9k_ps_wakeup(sc);
  1633. ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
  1634. if (sc->cur_chan == avp->chanctx)
  1635. ath9k_hw_reset_tsf(sc->sc_ah);
  1636. avp->chanctx->tsf_val = 0;
  1637. ath9k_ps_restore(sc);
  1638. mutex_unlock(&sc->mutex);
  1639. }
  1640. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1641. struct ieee80211_vif *vif,
  1642. struct ieee80211_ampdu_params *params)
  1643. {
  1644. struct ath_softc *sc = hw->priv;
  1645. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1646. bool flush = false;
  1647. int ret = 0;
  1648. struct ieee80211_sta *sta = params->sta;
  1649. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  1650. enum ieee80211_ampdu_mlme_action action = params->action;
  1651. u16 tid = params->tid;
  1652. u16 *ssn = &params->ssn;
  1653. struct ath_atx_tid *atid;
  1654. mutex_lock(&sc->mutex);
  1655. switch (action) {
  1656. case IEEE80211_AMPDU_RX_START:
  1657. break;
  1658. case IEEE80211_AMPDU_RX_STOP:
  1659. break;
  1660. case IEEE80211_AMPDU_TX_START:
  1661. if (ath9k_is_chanctx_enabled()) {
  1662. if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
  1663. ret = -EBUSY;
  1664. break;
  1665. }
  1666. }
  1667. ath9k_ps_wakeup(sc);
  1668. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1669. if (!ret)
  1670. ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
  1671. ath9k_ps_restore(sc);
  1672. break;
  1673. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1674. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1675. flush = true;
  1676. fallthrough;
  1677. case IEEE80211_AMPDU_TX_STOP_CONT:
  1678. ath9k_ps_wakeup(sc);
  1679. ath_tx_aggr_stop(sc, sta, tid);
  1680. if (!flush)
  1681. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1682. ath9k_ps_restore(sc);
  1683. break;
  1684. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1685. atid = ath_node_to_tid(an, tid);
  1686. atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
  1687. sta->deflink.ht_cap.ampdu_factor;
  1688. break;
  1689. default:
  1690. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1691. }
  1692. mutex_unlock(&sc->mutex);
  1693. return ret;
  1694. }
  1695. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1696. struct survey_info *survey)
  1697. {
  1698. struct ath_softc *sc = hw->priv;
  1699. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1700. struct ieee80211_supported_band *sband;
  1701. struct ieee80211_channel *chan;
  1702. unsigned long flags;
  1703. int pos;
  1704. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1705. return -EOPNOTSUPP;
  1706. spin_lock_irqsave(&common->cc_lock, flags);
  1707. if (idx == 0)
  1708. ath_update_survey_stats(sc);
  1709. sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
  1710. if (sband && idx >= sband->n_channels) {
  1711. idx -= sband->n_channels;
  1712. sband = NULL;
  1713. }
  1714. if (!sband)
  1715. sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
  1716. if (!sband || idx >= sband->n_channels) {
  1717. spin_unlock_irqrestore(&common->cc_lock, flags);
  1718. return -ENOENT;
  1719. }
  1720. chan = &sband->channels[idx];
  1721. pos = chan->hw_value;
  1722. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1723. survey->channel = chan;
  1724. spin_unlock_irqrestore(&common->cc_lock, flags);
  1725. return 0;
  1726. }
  1727. static void ath9k_enable_dynack(struct ath_softc *sc)
  1728. {
  1729. #ifdef CONFIG_ATH9K_DYNACK
  1730. u32 rfilt;
  1731. struct ath_hw *ah = sc->sc_ah;
  1732. ath_dynack_reset(ah);
  1733. ah->dynack.enabled = true;
  1734. rfilt = ath_calcrxfilter(sc);
  1735. ath9k_hw_setrxfilter(ah, rfilt);
  1736. #endif
  1737. }
  1738. static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
  1739. s16 coverage_class)
  1740. {
  1741. struct ath_softc *sc = hw->priv;
  1742. struct ath_hw *ah = sc->sc_ah;
  1743. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1744. return;
  1745. mutex_lock(&sc->mutex);
  1746. if (coverage_class >= 0) {
  1747. ah->coverage_class = coverage_class;
  1748. if (ah->dynack.enabled) {
  1749. u32 rfilt;
  1750. ah->dynack.enabled = false;
  1751. rfilt = ath_calcrxfilter(sc);
  1752. ath9k_hw_setrxfilter(ah, rfilt);
  1753. }
  1754. ath9k_ps_wakeup(sc);
  1755. ath9k_hw_init_global_settings(ah);
  1756. ath9k_ps_restore(sc);
  1757. } else if (!ah->dynack.enabled) {
  1758. ath9k_enable_dynack(sc);
  1759. }
  1760. mutex_unlock(&sc->mutex);
  1761. }
  1762. static bool ath9k_has_tx_pending(struct ath_softc *sc,
  1763. bool sw_pending)
  1764. {
  1765. int i, npend = 0;
  1766. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1767. if (!ATH_TXQ_SETUP(sc, i))
  1768. continue;
  1769. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
  1770. sw_pending);
  1771. if (npend)
  1772. break;
  1773. }
  1774. return !!npend;
  1775. }
  1776. static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1777. u32 queues, bool drop)
  1778. {
  1779. struct ath_softc *sc = hw->priv;
  1780. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1781. if (ath9k_is_chanctx_enabled()) {
  1782. if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
  1783. goto flush;
  1784. /*
  1785. * If MCC is active, extend the flush timeout
  1786. * and wait for the HW/SW queues to become
  1787. * empty. This needs to be done outside the
  1788. * sc->mutex lock to allow the channel scheduler
  1789. * to switch channel contexts.
  1790. *
  1791. * The vif queues have been stopped in mac80211,
  1792. * so there won't be any incoming frames.
  1793. */
  1794. __ath9k_flush(hw, queues, drop, true, true);
  1795. return;
  1796. }
  1797. flush:
  1798. mutex_lock(&sc->mutex);
  1799. __ath9k_flush(hw, queues, drop, true, false);
  1800. mutex_unlock(&sc->mutex);
  1801. }
  1802. void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
  1803. bool sw_pending, bool timeout_override)
  1804. {
  1805. struct ath_softc *sc = hw->priv;
  1806. struct ath_hw *ah = sc->sc_ah;
  1807. struct ath_common *common = ath9k_hw_common(ah);
  1808. int timeout;
  1809. bool drain_txq;
  1810. cancel_delayed_work_sync(&sc->hw_check_work);
  1811. if (ah->ah_flags & AH_UNPLUGGED) {
  1812. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1813. return;
  1814. }
  1815. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  1816. ath_dbg(common, ANY, "Device not present\n");
  1817. return;
  1818. }
  1819. spin_lock_bh(&sc->chan_lock);
  1820. if (timeout_override)
  1821. timeout = HZ / 5;
  1822. else
  1823. timeout = sc->cur_chan->flush_timeout;
  1824. spin_unlock_bh(&sc->chan_lock);
  1825. ath_dbg(common, CHAN_CTX,
  1826. "Flush timeout: %d\n", jiffies_to_msecs(timeout));
  1827. if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
  1828. timeout) > 0)
  1829. drop = false;
  1830. if (drop) {
  1831. ath9k_ps_wakeup(sc);
  1832. spin_lock_bh(&sc->sc_pcu_lock);
  1833. drain_txq = ath_drain_all_txq(sc);
  1834. spin_unlock_bh(&sc->sc_pcu_lock);
  1835. if (!drain_txq)
  1836. ath_reset(sc, NULL);
  1837. ath9k_ps_restore(sc);
  1838. }
  1839. ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
  1840. msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
  1841. }
  1842. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1843. {
  1844. struct ath_softc *sc = hw->priv;
  1845. return ath9k_has_tx_pending(sc, true);
  1846. }
  1847. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1848. {
  1849. struct ath_softc *sc = hw->priv;
  1850. struct ath_hw *ah = sc->sc_ah;
  1851. struct ieee80211_vif *vif;
  1852. struct ath_vif *avp;
  1853. struct ath_buf *bf;
  1854. struct ath_tx_status ts;
  1855. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1856. int status;
  1857. vif = sc->beacon.bslot[0];
  1858. if (!vif)
  1859. return 0;
  1860. if (!vif->bss_conf.enable_beacon)
  1861. return 0;
  1862. avp = (void *)vif->drv_priv;
  1863. if (!sc->beacon.tx_processed && !edma) {
  1864. tasklet_disable(&sc->bcon_tasklet);
  1865. bf = avp->av_bcbuf;
  1866. if (!bf || !bf->bf_mpdu)
  1867. goto skip;
  1868. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1869. if (status == -EINPROGRESS)
  1870. goto skip;
  1871. sc->beacon.tx_processed = true;
  1872. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1873. skip:
  1874. tasklet_enable(&sc->bcon_tasklet);
  1875. }
  1876. return sc->beacon.tx_last;
  1877. }
  1878. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1879. struct ieee80211_low_level_stats *stats)
  1880. {
  1881. struct ath_softc *sc = hw->priv;
  1882. struct ath_hw *ah = sc->sc_ah;
  1883. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1884. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1885. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1886. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1887. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1888. return 0;
  1889. }
  1890. static u32 fill_chainmask(u32 cap, u32 new)
  1891. {
  1892. u32 filled = 0;
  1893. int i;
  1894. for (i = 0; cap && new; i++, cap >>= 1) {
  1895. if (!(cap & BIT(0)))
  1896. continue;
  1897. if (new & BIT(0))
  1898. filled |= BIT(i);
  1899. new >>= 1;
  1900. }
  1901. return filled;
  1902. }
  1903. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1904. {
  1905. if (AR_SREV_9300_20_OR_LATER(ah))
  1906. return true;
  1907. switch (val & 0x7) {
  1908. case 0x1:
  1909. case 0x3:
  1910. case 0x7:
  1911. return true;
  1912. case 0x2:
  1913. return (ah->caps.rx_chainmask == 1);
  1914. default:
  1915. return false;
  1916. }
  1917. }
  1918. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1919. {
  1920. struct ath_softc *sc = hw->priv;
  1921. struct ath_hw *ah = sc->sc_ah;
  1922. if (ah->caps.rx_chainmask != 1)
  1923. rx_ant |= tx_ant;
  1924. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1925. return -EINVAL;
  1926. sc->ant_rx = rx_ant;
  1927. sc->ant_tx = tx_ant;
  1928. if (ah->caps.rx_chainmask == 1)
  1929. return 0;
  1930. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1931. if (AR_SREV_9100(ah))
  1932. ah->rxchainmask = 0x7;
  1933. else
  1934. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1935. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1936. ath9k_cmn_reload_chainmask(ah);
  1937. return 0;
  1938. }
  1939. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1940. {
  1941. struct ath_softc *sc = hw->priv;
  1942. *tx_ant = sc->ant_tx;
  1943. *rx_ant = sc->ant_rx;
  1944. return 0;
  1945. }
  1946. static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
  1947. struct ieee80211_vif *vif,
  1948. const u8 *mac_addr)
  1949. {
  1950. struct ath_softc *sc = hw->priv;
  1951. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1952. set_bit(ATH_OP_SCANNING, &common->op_flags);
  1953. }
  1954. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
  1955. struct ieee80211_vif *vif)
  1956. {
  1957. struct ath_softc *sc = hw->priv;
  1958. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1959. clear_bit(ATH_OP_SCANNING, &common->op_flags);
  1960. }
  1961. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  1962. static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
  1963. {
  1964. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1965. if (sc->offchannel.roc_vif) {
  1966. ath_dbg(common, CHAN_CTX,
  1967. "%s: Aborting RoC\n", __func__);
  1968. del_timer_sync(&sc->offchannel.timer);
  1969. if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
  1970. ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
  1971. }
  1972. if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
  1973. ath_dbg(common, CHAN_CTX,
  1974. "%s: Aborting HW scan\n", __func__);
  1975. del_timer_sync(&sc->offchannel.timer);
  1976. ath_scan_complete(sc, true);
  1977. }
  1978. }
  1979. static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1980. struct ieee80211_scan_request *hw_req)
  1981. {
  1982. struct cfg80211_scan_request *req = &hw_req->req;
  1983. struct ath_softc *sc = hw->priv;
  1984. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1985. int ret = 0;
  1986. mutex_lock(&sc->mutex);
  1987. if (WARN_ON(sc->offchannel.scan_req)) {
  1988. ret = -EBUSY;
  1989. goto out;
  1990. }
  1991. ath9k_ps_wakeup(sc);
  1992. set_bit(ATH_OP_SCANNING, &common->op_flags);
  1993. sc->offchannel.scan_vif = vif;
  1994. sc->offchannel.scan_req = req;
  1995. sc->offchannel.scan_idx = 0;
  1996. ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
  1997. vif->addr);
  1998. if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
  1999. ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
  2000. ath_offchannel_next(sc);
  2001. }
  2002. out:
  2003. mutex_unlock(&sc->mutex);
  2004. return ret;
  2005. }
  2006. static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
  2007. struct ieee80211_vif *vif)
  2008. {
  2009. struct ath_softc *sc = hw->priv;
  2010. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2011. ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
  2012. mutex_lock(&sc->mutex);
  2013. del_timer_sync(&sc->offchannel.timer);
  2014. ath_scan_complete(sc, true);
  2015. mutex_unlock(&sc->mutex);
  2016. }
  2017. static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
  2018. struct ieee80211_vif *vif,
  2019. struct ieee80211_channel *chan, int duration,
  2020. enum ieee80211_roc_type type)
  2021. {
  2022. struct ath_softc *sc = hw->priv;
  2023. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2024. int ret = 0;
  2025. mutex_lock(&sc->mutex);
  2026. if (WARN_ON(sc->offchannel.roc_vif)) {
  2027. ret = -EBUSY;
  2028. goto out;
  2029. }
  2030. ath9k_ps_wakeup(sc);
  2031. sc->offchannel.roc_vif = vif;
  2032. sc->offchannel.roc_chan = chan;
  2033. sc->offchannel.roc_duration = duration;
  2034. ath_dbg(common, CHAN_CTX,
  2035. "RoC request on vif: %pM, type: %d duration: %d\n",
  2036. vif->addr, type, duration);
  2037. if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
  2038. ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
  2039. ath_offchannel_next(sc);
  2040. }
  2041. out:
  2042. mutex_unlock(&sc->mutex);
  2043. return ret;
  2044. }
  2045. static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
  2046. struct ieee80211_vif *vif)
  2047. {
  2048. struct ath_softc *sc = hw->priv;
  2049. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2050. mutex_lock(&sc->mutex);
  2051. ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
  2052. del_timer_sync(&sc->offchannel.timer);
  2053. if (sc->offchannel.roc_vif) {
  2054. if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
  2055. ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
  2056. }
  2057. mutex_unlock(&sc->mutex);
  2058. return 0;
  2059. }
  2060. static int ath9k_add_chanctx(struct ieee80211_hw *hw,
  2061. struct ieee80211_chanctx_conf *conf)
  2062. {
  2063. struct ath_softc *sc = hw->priv;
  2064. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2065. struct ath_chanctx *ctx, **ptr;
  2066. int pos;
  2067. mutex_lock(&sc->mutex);
  2068. ath_for_each_chanctx(sc, ctx) {
  2069. if (ctx->assigned)
  2070. continue;
  2071. ptr = (void *) conf->drv_priv;
  2072. *ptr = ctx;
  2073. ctx->assigned = true;
  2074. pos = ctx - &sc->chanctx[0];
  2075. ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
  2076. ath_dbg(common, CHAN_CTX,
  2077. "Add channel context: %d MHz\n",
  2078. conf->def.chan->center_freq);
  2079. ath_chanctx_set_channel(sc, ctx, &conf->def);
  2080. mutex_unlock(&sc->mutex);
  2081. return 0;
  2082. }
  2083. mutex_unlock(&sc->mutex);
  2084. return -ENOSPC;
  2085. }
  2086. static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
  2087. struct ieee80211_chanctx_conf *conf)
  2088. {
  2089. struct ath_softc *sc = hw->priv;
  2090. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2091. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2092. mutex_lock(&sc->mutex);
  2093. ath_dbg(common, CHAN_CTX,
  2094. "Remove channel context: %d MHz\n",
  2095. conf->def.chan->center_freq);
  2096. ctx->assigned = false;
  2097. ctx->hw_queue_base = 0;
  2098. ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
  2099. mutex_unlock(&sc->mutex);
  2100. }
  2101. static void ath9k_change_chanctx(struct ieee80211_hw *hw,
  2102. struct ieee80211_chanctx_conf *conf,
  2103. u32 changed)
  2104. {
  2105. struct ath_softc *sc = hw->priv;
  2106. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2107. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2108. mutex_lock(&sc->mutex);
  2109. ath_dbg(common, CHAN_CTX,
  2110. "Change channel context: %d MHz\n",
  2111. conf->def.chan->center_freq);
  2112. ath_chanctx_set_channel(sc, ctx, &conf->def);
  2113. mutex_unlock(&sc->mutex);
  2114. }
  2115. static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
  2116. struct ieee80211_vif *vif,
  2117. struct ieee80211_bss_conf *link_conf,
  2118. struct ieee80211_chanctx_conf *conf)
  2119. {
  2120. struct ath_softc *sc = hw->priv;
  2121. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2122. struct ath_vif *avp = (void *)vif->drv_priv;
  2123. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2124. int i;
  2125. ath9k_cancel_pending_offchannel(sc);
  2126. mutex_lock(&sc->mutex);
  2127. ath_dbg(common, CHAN_CTX,
  2128. "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
  2129. vif->addr, vif->type, vif->p2p,
  2130. conf->def.chan->center_freq);
  2131. avp->chanctx = ctx;
  2132. ctx->nvifs_assigned++;
  2133. list_add_tail(&avp->list, &ctx->vifs);
  2134. ath9k_calculate_summary_state(sc, ctx);
  2135. for (i = 0; i < IEEE80211_NUM_ACS; i++)
  2136. vif->hw_queue[i] = ctx->hw_queue_base + i;
  2137. mutex_unlock(&sc->mutex);
  2138. return 0;
  2139. }
  2140. static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
  2141. struct ieee80211_vif *vif,
  2142. struct ieee80211_bss_conf *link_conf,
  2143. struct ieee80211_chanctx_conf *conf)
  2144. {
  2145. struct ath_softc *sc = hw->priv;
  2146. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2147. struct ath_vif *avp = (void *)vif->drv_priv;
  2148. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2149. int ac;
  2150. ath9k_cancel_pending_offchannel(sc);
  2151. mutex_lock(&sc->mutex);
  2152. ath_dbg(common, CHAN_CTX,
  2153. "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
  2154. vif->addr, vif->type, vif->p2p,
  2155. conf->def.chan->center_freq);
  2156. avp->chanctx = NULL;
  2157. ctx->nvifs_assigned--;
  2158. list_del(&avp->list);
  2159. ath9k_calculate_summary_state(sc, ctx);
  2160. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  2161. vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
  2162. mutex_unlock(&sc->mutex);
  2163. }
  2164. static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
  2165. struct ieee80211_vif *vif,
  2166. struct ieee80211_prep_tx_info *info)
  2167. {
  2168. struct ath_softc *sc = hw->priv;
  2169. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2170. struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
  2171. struct ath_beacon_config *cur_conf;
  2172. struct ath_chanctx *go_ctx;
  2173. unsigned long timeout;
  2174. bool changed = false;
  2175. u32 beacon_int;
  2176. if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
  2177. return;
  2178. if (!avp->chanctx)
  2179. return;
  2180. mutex_lock(&sc->mutex);
  2181. spin_lock_bh(&sc->chan_lock);
  2182. if (sc->next_chan || (sc->cur_chan != avp->chanctx))
  2183. changed = true;
  2184. spin_unlock_bh(&sc->chan_lock);
  2185. if (!changed)
  2186. goto out;
  2187. ath9k_cancel_pending_offchannel(sc);
  2188. go_ctx = ath_is_go_chanctx_present(sc);
  2189. if (go_ctx) {
  2190. /*
  2191. * Wait till the GO interface gets a chance
  2192. * to send out an NoA.
  2193. */
  2194. spin_lock_bh(&sc->chan_lock);
  2195. sc->sched.mgd_prepare_tx = true;
  2196. cur_conf = &go_ctx->beacon;
  2197. beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
  2198. spin_unlock_bh(&sc->chan_lock);
  2199. timeout = usecs_to_jiffies(beacon_int * 2);
  2200. init_completion(&sc->go_beacon);
  2201. mutex_unlock(&sc->mutex);
  2202. if (wait_for_completion_timeout(&sc->go_beacon,
  2203. timeout) == 0) {
  2204. ath_dbg(common, CHAN_CTX,
  2205. "Failed to send new NoA\n");
  2206. spin_lock_bh(&sc->chan_lock);
  2207. sc->sched.mgd_prepare_tx = false;
  2208. spin_unlock_bh(&sc->chan_lock);
  2209. }
  2210. mutex_lock(&sc->mutex);
  2211. }
  2212. ath_dbg(common, CHAN_CTX,
  2213. "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
  2214. __func__, vif->addr);
  2215. spin_lock_bh(&sc->chan_lock);
  2216. sc->next_chan = avp->chanctx;
  2217. sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
  2218. spin_unlock_bh(&sc->chan_lock);
  2219. ath_chanctx_set_next(sc, true);
  2220. out:
  2221. mutex_unlock(&sc->mutex);
  2222. }
  2223. void ath9k_fill_chanctx_ops(void)
  2224. {
  2225. if (!ath9k_is_chanctx_enabled())
  2226. return;
  2227. ath9k_ops.hw_scan = ath9k_hw_scan;
  2228. ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
  2229. ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
  2230. ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
  2231. ath9k_ops.add_chanctx = ath9k_add_chanctx;
  2232. ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
  2233. ath9k_ops.change_chanctx = ath9k_change_chanctx;
  2234. ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
  2235. ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
  2236. ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
  2237. }
  2238. #endif
  2239. static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2240. int *dbm)
  2241. {
  2242. struct ath_softc *sc = hw->priv;
  2243. struct ath_vif *avp = (void *)vif->drv_priv;
  2244. mutex_lock(&sc->mutex);
  2245. if (avp->chanctx)
  2246. *dbm = avp->chanctx->cur_txpower;
  2247. else
  2248. *dbm = sc->cur_chan->cur_txpower;
  2249. mutex_unlock(&sc->mutex);
  2250. *dbm /= 2;
  2251. return 0;
  2252. }
  2253. struct ieee80211_ops ath9k_ops = {
  2254. .tx = ath9k_tx,
  2255. .start = ath9k_start,
  2256. .stop = ath9k_stop,
  2257. .add_interface = ath9k_add_interface,
  2258. .change_interface = ath9k_change_interface,
  2259. .remove_interface = ath9k_remove_interface,
  2260. .config = ath9k_config,
  2261. .configure_filter = ath9k_configure_filter,
  2262. .sta_state = ath9k_sta_state,
  2263. .sta_notify = ath9k_sta_notify,
  2264. .conf_tx = ath9k_conf_tx,
  2265. .bss_info_changed = ath9k_bss_info_changed,
  2266. .set_key = ath9k_set_key,
  2267. .get_tsf = ath9k_get_tsf,
  2268. .set_tsf = ath9k_set_tsf,
  2269. .reset_tsf = ath9k_reset_tsf,
  2270. .ampdu_action = ath9k_ampdu_action,
  2271. .get_survey = ath9k_get_survey,
  2272. .rfkill_poll = ath9k_rfkill_poll_state,
  2273. .set_coverage_class = ath9k_set_coverage_class,
  2274. .flush = ath9k_flush,
  2275. .tx_frames_pending = ath9k_tx_frames_pending,
  2276. .tx_last_beacon = ath9k_tx_last_beacon,
  2277. .release_buffered_frames = ath9k_release_buffered_frames,
  2278. .get_stats = ath9k_get_stats,
  2279. .set_antenna = ath9k_set_antenna,
  2280. .get_antenna = ath9k_get_antenna,
  2281. #ifdef CONFIG_ATH9K_WOW
  2282. .suspend = ath9k_suspend,
  2283. .resume = ath9k_resume,
  2284. .set_wakeup = ath9k_set_wakeup,
  2285. #endif
  2286. #ifdef CONFIG_ATH9K_DEBUGFS
  2287. .get_et_sset_count = ath9k_get_et_sset_count,
  2288. .get_et_stats = ath9k_get_et_stats,
  2289. .get_et_strings = ath9k_get_et_strings,
  2290. #endif
  2291. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
  2292. .sta_add_debugfs = ath9k_sta_add_debugfs,
  2293. #endif
  2294. .sw_scan_start = ath9k_sw_scan_start,
  2295. .sw_scan_complete = ath9k_sw_scan_complete,
  2296. .get_txpower = ath9k_get_txpower,
  2297. .wake_tx_queue = ath9k_wake_tx_queue,
  2298. };