dynack.c 9.5 KB

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  1. /*
  2. * Copyright (c) 2014, Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "ath9k.h"
  17. #include "hw.h"
  18. #include "dynack.h"
  19. #define COMPUTE_TO (5 * HZ)
  20. #define LATEACK_DELAY (10 * HZ)
  21. #define EWMA_LEVEL 96
  22. #define EWMA_DIV 128
  23. /**
  24. * ath_dynack_get_max_to - set max timeout according to channel width
  25. * @ah: ath hw
  26. *
  27. */
  28. static u32 ath_dynack_get_max_to(struct ath_hw *ah)
  29. {
  30. const struct ath9k_channel *chan = ah->curchan;
  31. if (!chan)
  32. return 300;
  33. if (IS_CHAN_HT40(chan))
  34. return 300;
  35. if (IS_CHAN_HALF_RATE(chan))
  36. return 750;
  37. if (IS_CHAN_QUARTER_RATE(chan))
  38. return 1500;
  39. return 600;
  40. }
  41. /*
  42. * ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
  43. */
  44. static inline int ath_dynack_ewma(int old, int new)
  45. {
  46. if (old > 0)
  47. return (new * (EWMA_DIV - EWMA_LEVEL) +
  48. old * EWMA_LEVEL) / EWMA_DIV;
  49. else
  50. return new;
  51. }
  52. /**
  53. * ath_dynack_get_sifs - get sifs time based on phy used
  54. * @ah: ath hw
  55. * @phy: phy used
  56. *
  57. */
  58. static inline u32 ath_dynack_get_sifs(struct ath_hw *ah, int phy)
  59. {
  60. u32 sifs = CCK_SIFS_TIME;
  61. if (phy == WLAN_RC_PHY_OFDM) {
  62. if (IS_CHAN_QUARTER_RATE(ah->curchan))
  63. sifs = OFDM_SIFS_TIME_QUARTER;
  64. else if (IS_CHAN_HALF_RATE(ah->curchan))
  65. sifs = OFDM_SIFS_TIME_HALF;
  66. else
  67. sifs = OFDM_SIFS_TIME;
  68. }
  69. return sifs;
  70. }
  71. /**
  72. * ath_dynack_bssidmask - filter out ACK frames based on BSSID mask
  73. * @ah: ath hw
  74. * @mac: receiver address
  75. */
  76. static inline bool ath_dynack_bssidmask(struct ath_hw *ah, const u8 *mac)
  77. {
  78. int i;
  79. struct ath_common *common = ath9k_hw_common(ah);
  80. for (i = 0; i < ETH_ALEN; i++) {
  81. if ((common->macaddr[i] & common->bssidmask[i]) !=
  82. (mac[i] & common->bssidmask[i]))
  83. return false;
  84. }
  85. return true;
  86. }
  87. /**
  88. * ath_dynack_set_timeout - configure timeouts/slottime registers
  89. * @ah: ath hw
  90. * @to: timeout value
  91. *
  92. */
  93. static void ath_dynack_set_timeout(struct ath_hw *ah, int to)
  94. {
  95. struct ath_common *common = ath9k_hw_common(ah);
  96. int slottime = (to - 3) / 2;
  97. ath_dbg(common, DYNACK, "ACK timeout %u slottime %u\n",
  98. to, slottime);
  99. ath9k_hw_setslottime(ah, slottime);
  100. ath9k_hw_set_ack_timeout(ah, to);
  101. ath9k_hw_set_cts_timeout(ah, to);
  102. }
  103. /**
  104. * ath_dynack_compute_ackto - compute ACK timeout as the maximum STA timeout
  105. * @ah: ath hw
  106. *
  107. * should be called while holding qlock
  108. */
  109. static void ath_dynack_compute_ackto(struct ath_hw *ah)
  110. {
  111. struct ath_dynack *da = &ah->dynack;
  112. struct ath_node *an;
  113. int to = 0;
  114. list_for_each_entry(an, &da->nodes, list)
  115. if (an->ackto > to)
  116. to = an->ackto;
  117. if (to && da->ackto != to) {
  118. ath_dynack_set_timeout(ah, to);
  119. da->ackto = to;
  120. }
  121. }
  122. /**
  123. * ath_dynack_compute_to - compute STA ACK timeout
  124. * @ah: ath hw
  125. *
  126. * should be called while holding qlock
  127. */
  128. static void ath_dynack_compute_to(struct ath_hw *ah)
  129. {
  130. struct ath_dynack *da = &ah->dynack;
  131. u32 ackto, ack_ts, max_to;
  132. struct ieee80211_sta *sta;
  133. struct ts_info *st_ts;
  134. struct ath_node *an;
  135. u8 *dst, *src;
  136. rcu_read_lock();
  137. max_to = ath_dynack_get_max_to(ah);
  138. while (da->st_rbf.h_rb != da->st_rbf.t_rb &&
  139. da->ack_rbf.h_rb != da->ack_rbf.t_rb) {
  140. ack_ts = da->ack_rbf.tstamp[da->ack_rbf.h_rb];
  141. st_ts = &da->st_rbf.ts[da->st_rbf.h_rb];
  142. dst = da->st_rbf.addr[da->st_rbf.h_rb].h_dest;
  143. src = da->st_rbf.addr[da->st_rbf.h_rb].h_src;
  144. ath_dbg(ath9k_hw_common(ah), DYNACK,
  145. "ack_ts %u st_ts %u st_dur %u [%u-%u]\n",
  146. ack_ts, st_ts->tstamp, st_ts->dur,
  147. da->ack_rbf.h_rb, da->st_rbf.h_rb);
  148. if (ack_ts > st_ts->tstamp + st_ts->dur) {
  149. ackto = ack_ts - st_ts->tstamp - st_ts->dur;
  150. if (ackto < max_to) {
  151. sta = ieee80211_find_sta_by_ifaddr(ah->hw, dst,
  152. src);
  153. if (sta) {
  154. an = (struct ath_node *)sta->drv_priv;
  155. an->ackto = ath_dynack_ewma(an->ackto,
  156. ackto);
  157. ath_dbg(ath9k_hw_common(ah), DYNACK,
  158. "%pM to %d [%u]\n", dst,
  159. an->ackto, ackto);
  160. if (time_is_before_jiffies(da->lto)) {
  161. ath_dynack_compute_ackto(ah);
  162. da->lto = jiffies + COMPUTE_TO;
  163. }
  164. }
  165. INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
  166. }
  167. INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
  168. } else {
  169. INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
  170. }
  171. }
  172. rcu_read_unlock();
  173. }
  174. /**
  175. * ath_dynack_sample_tx_ts - status timestamp sampling method
  176. * @ah: ath hw
  177. * @skb: socket buffer
  178. * @ts: tx status info
  179. * @sta: station pointer
  180. *
  181. */
  182. void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
  183. struct ath_tx_status *ts,
  184. struct ieee80211_sta *sta)
  185. {
  186. struct ieee80211_hdr *hdr;
  187. struct ath_dynack *da = &ah->dynack;
  188. struct ath_common *common = ath9k_hw_common(ah);
  189. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  190. u32 dur = ts->duration;
  191. u8 ridx;
  192. if (!da->enabled || (info->flags & IEEE80211_TX_CTL_NO_ACK))
  193. return;
  194. spin_lock_bh(&da->qlock);
  195. hdr = (struct ieee80211_hdr *)skb->data;
  196. /* late ACK */
  197. if (ts->ts_status & ATH9K_TXERR_XRETRY) {
  198. if (ieee80211_is_assoc_req(hdr->frame_control) ||
  199. ieee80211_is_assoc_resp(hdr->frame_control) ||
  200. ieee80211_is_auth(hdr->frame_control)) {
  201. u32 max_to = ath_dynack_get_max_to(ah);
  202. ath_dbg(common, DYNACK, "late ack\n");
  203. ath_dynack_set_timeout(ah, max_to);
  204. if (sta) {
  205. struct ath_node *an;
  206. an = (struct ath_node *)sta->drv_priv;
  207. an->ackto = -1;
  208. }
  209. da->lto = jiffies + LATEACK_DELAY;
  210. }
  211. spin_unlock_bh(&da->qlock);
  212. return;
  213. }
  214. ridx = ts->ts_rateindex;
  215. da->st_rbf.ts[da->st_rbf.t_rb].tstamp = ts->ts_tstamp;
  216. /* ether_addr_copy() gives a false warning on gcc-10 so use memcpy()
  217. * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97490
  218. */
  219. memcpy(da->st_rbf.addr[da->st_rbf.t_rb].h_dest, hdr->addr1, ETH_ALEN);
  220. memcpy(da->st_rbf.addr[da->st_rbf.t_rb].h_src, hdr->addr2, ETH_ALEN);
  221. if (!(info->status.rates[ridx].flags & IEEE80211_TX_RC_MCS)) {
  222. const struct ieee80211_rate *rate;
  223. struct ieee80211_tx_rate *rates = info->status.rates;
  224. u32 phy;
  225. rate = &common->sbands[info->band].bitrates[rates[ridx].idx];
  226. if (info->band == NL80211_BAND_2GHZ &&
  227. !(rate->flags & IEEE80211_RATE_ERP_G))
  228. phy = WLAN_RC_PHY_CCK;
  229. else
  230. phy = WLAN_RC_PHY_OFDM;
  231. dur -= ath_dynack_get_sifs(ah, phy);
  232. }
  233. da->st_rbf.ts[da->st_rbf.t_rb].dur = dur;
  234. INCR(da->st_rbf.t_rb, ATH_DYN_BUF);
  235. if (da->st_rbf.t_rb == da->st_rbf.h_rb)
  236. INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
  237. ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
  238. hdr->addr1, ts->ts_tstamp, dur, da->st_rbf.h_rb,
  239. da->st_rbf.t_rb);
  240. ath_dynack_compute_to(ah);
  241. spin_unlock_bh(&da->qlock);
  242. }
  243. EXPORT_SYMBOL(ath_dynack_sample_tx_ts);
  244. /**
  245. * ath_dynack_sample_ack_ts - ACK timestamp sampling method
  246. * @ah: ath hw
  247. * @skb: socket buffer
  248. * @ts: rx timestamp
  249. *
  250. */
  251. void ath_dynack_sample_ack_ts(struct ath_hw *ah, struct sk_buff *skb,
  252. u32 ts)
  253. {
  254. struct ath_dynack *da = &ah->dynack;
  255. struct ath_common *common = ath9k_hw_common(ah);
  256. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  257. if (!da->enabled || !ath_dynack_bssidmask(ah, hdr->addr1))
  258. return;
  259. spin_lock_bh(&da->qlock);
  260. da->ack_rbf.tstamp[da->ack_rbf.t_rb] = ts;
  261. INCR(da->ack_rbf.t_rb, ATH_DYN_BUF);
  262. if (da->ack_rbf.t_rb == da->ack_rbf.h_rb)
  263. INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
  264. ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
  265. ts, da->ack_rbf.h_rb, da->ack_rbf.t_rb);
  266. ath_dynack_compute_to(ah);
  267. spin_unlock_bh(&da->qlock);
  268. }
  269. EXPORT_SYMBOL(ath_dynack_sample_ack_ts);
  270. /**
  271. * ath_dynack_node_init - init ath_node related info
  272. * @ah: ath hw
  273. * @an: ath node
  274. *
  275. */
  276. void ath_dynack_node_init(struct ath_hw *ah, struct ath_node *an)
  277. {
  278. struct ath_dynack *da = &ah->dynack;
  279. an->ackto = da->ackto;
  280. spin_lock_bh(&da->qlock);
  281. list_add_tail(&an->list, &da->nodes);
  282. spin_unlock_bh(&da->qlock);
  283. }
  284. EXPORT_SYMBOL(ath_dynack_node_init);
  285. /**
  286. * ath_dynack_node_deinit - deinit ath_node related info
  287. * @ah: ath hw
  288. * @an: ath node
  289. *
  290. */
  291. void ath_dynack_node_deinit(struct ath_hw *ah, struct ath_node *an)
  292. {
  293. struct ath_dynack *da = &ah->dynack;
  294. spin_lock_bh(&da->qlock);
  295. list_del(&an->list);
  296. spin_unlock_bh(&da->qlock);
  297. }
  298. EXPORT_SYMBOL(ath_dynack_node_deinit);
  299. /**
  300. * ath_dynack_reset - reset dynack processing
  301. * @ah: ath hw
  302. *
  303. */
  304. void ath_dynack_reset(struct ath_hw *ah)
  305. {
  306. struct ath_dynack *da = &ah->dynack;
  307. struct ath_node *an;
  308. spin_lock_bh(&da->qlock);
  309. da->lto = jiffies + COMPUTE_TO;
  310. da->st_rbf.t_rb = 0;
  311. da->st_rbf.h_rb = 0;
  312. da->ack_rbf.t_rb = 0;
  313. da->ack_rbf.h_rb = 0;
  314. da->ackto = ath_dynack_get_max_to(ah);
  315. list_for_each_entry(an, &da->nodes, list)
  316. an->ackto = da->ackto;
  317. /* init acktimeout */
  318. ath_dynack_set_timeout(ah, da->ackto);
  319. spin_unlock_bh(&da->qlock);
  320. }
  321. EXPORT_SYMBOL(ath_dynack_reset);
  322. /**
  323. * ath_dynack_init - init dynack data structure
  324. * @ah: ath hw
  325. *
  326. */
  327. void ath_dynack_init(struct ath_hw *ah)
  328. {
  329. struct ath_dynack *da = &ah->dynack;
  330. memset(da, 0, sizeof(struct ath_dynack));
  331. spin_lock_init(&da->qlock);
  332. INIT_LIST_HEAD(&da->nodes);
  333. /* ackto = slottime + sifs + air delay */
  334. da->ackto = 9 + 16 + 64;
  335. ah->hw->wiphy->features |= NL80211_FEATURE_ACKTO_ESTIMATION;
  336. }