bmi.h 6.9 KB

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  1. /* SPDX-License-Identifier: ISC */
  2. /*
  3. * Copyright (c) 2005-2011 Atheros Communications Inc.
  4. * Copyright (c) 2011-2015,2017 Qualcomm Atheros, Inc.
  5. */
  6. #ifndef _BMI_H_
  7. #define _BMI_H_
  8. #include "core.h"
  9. /*
  10. * Bootloader Messaging Interface (BMI)
  11. *
  12. * BMI is a very simple messaging interface used during initialization
  13. * to read memory, write memory, execute code, and to define an
  14. * application entry PC.
  15. *
  16. * It is used to download an application to QCA988x, to provide
  17. * patches to code that is already resident on QCA988x, and generally
  18. * to examine and modify state. The Host has an opportunity to use
  19. * BMI only once during bootup. Once the Host issues a BMI_DONE
  20. * command, this opportunity ends.
  21. *
  22. * The Host writes BMI requests to mailbox0, and reads BMI responses
  23. * from mailbox0. BMI requests all begin with a command
  24. * (see below for specific commands), and are followed by
  25. * command-specific data.
  26. *
  27. * Flow control:
  28. * The Host can only issue a command once the Target gives it a
  29. * "BMI Command Credit", using AR8K Counter #4. As soon as the
  30. * Target has completed a command, it issues another BMI Command
  31. * Credit (so the Host can issue the next command).
  32. *
  33. * BMI handles all required Target-side cache flushing.
  34. */
  35. /* Maximum data size used for BMI transfers */
  36. #define BMI_MAX_DATA_SIZE 256
  37. /* len = cmd + addr + length */
  38. #define BMI_MAX_CMDBUF_SIZE (BMI_MAX_DATA_SIZE + \
  39. sizeof(u32) + \
  40. sizeof(u32) + \
  41. sizeof(u32))
  42. /* Maximum data size used for large BMI transfers */
  43. #define BMI_MAX_LARGE_DATA_SIZE 2048
  44. /* len = cmd + addr + length */
  45. #define BMI_MAX_LARGE_CMDBUF_SIZE (BMI_MAX_LARGE_DATA_SIZE + \
  46. sizeof(u32) + \
  47. sizeof(u32) + \
  48. sizeof(u32))
  49. /* BMI Commands */
  50. enum bmi_cmd_id {
  51. BMI_NO_COMMAND = 0,
  52. BMI_DONE = 1,
  53. BMI_READ_MEMORY = 2,
  54. BMI_WRITE_MEMORY = 3,
  55. BMI_EXECUTE = 4,
  56. BMI_SET_APP_START = 5,
  57. BMI_READ_SOC_REGISTER = 6,
  58. BMI_READ_SOC_WORD = 6,
  59. BMI_WRITE_SOC_REGISTER = 7,
  60. BMI_WRITE_SOC_WORD = 7,
  61. BMI_GET_TARGET_ID = 8,
  62. BMI_GET_TARGET_INFO = 8,
  63. BMI_ROMPATCH_INSTALL = 9,
  64. BMI_ROMPATCH_UNINSTALL = 10,
  65. BMI_ROMPATCH_ACTIVATE = 11,
  66. BMI_ROMPATCH_DEACTIVATE = 12,
  67. BMI_LZ_STREAM_START = 13, /* should be followed by LZ_DATA */
  68. BMI_LZ_DATA = 14,
  69. BMI_NVRAM_PROCESS = 15,
  70. };
  71. #define BMI_NVRAM_SEG_NAME_SZ 16
  72. #define BMI_PARAM_GET_EEPROM_BOARD_ID 0x10
  73. #define BMI_PARAM_GET_FLASH_BOARD_ID 0x8000
  74. #define BMI_PARAM_FLASH_SECTION_ALL 0x10000
  75. /* Dual-band Extended Board ID */
  76. #define BMI_PARAM_GET_EXT_BOARD_ID 0x40000
  77. #define ATH10K_BMI_EXT_BOARD_ID_SUPPORT 0x40000
  78. #define ATH10K_BMI_BOARD_ID_FROM_OTP_MASK 0x7c00
  79. #define ATH10K_BMI_BOARD_ID_FROM_OTP_LSB 10
  80. #define ATH10K_BMI_CHIP_ID_FROM_OTP_MASK 0x18000
  81. #define ATH10K_BMI_CHIP_ID_FROM_OTP_LSB 15
  82. #define ATH10K_BMI_BOARD_ID_STATUS_MASK 0xff
  83. #define ATH10K_BMI_EBOARD_ID_STATUS_MASK 0xff
  84. struct bmi_cmd {
  85. __le32 id; /* enum bmi_cmd_id */
  86. union {
  87. struct {
  88. } done;
  89. struct {
  90. __le32 addr;
  91. __le32 len;
  92. } read_mem;
  93. struct {
  94. __le32 addr;
  95. __le32 len;
  96. u8 payload[];
  97. } write_mem;
  98. struct {
  99. __le32 addr;
  100. __le32 param;
  101. } execute;
  102. struct {
  103. __le32 addr;
  104. } set_app_start;
  105. struct {
  106. __le32 addr;
  107. } read_soc_reg;
  108. struct {
  109. __le32 addr;
  110. __le32 value;
  111. } write_soc_reg;
  112. struct {
  113. } get_target_info;
  114. struct {
  115. __le32 rom_addr;
  116. __le32 ram_addr; /* or value */
  117. __le32 size;
  118. __le32 activate; /* 0=install, but dont activate */
  119. } rompatch_install;
  120. struct {
  121. __le32 patch_id;
  122. } rompatch_uninstall;
  123. struct {
  124. __le32 count;
  125. __le32 patch_ids[]; /* length of @count */
  126. } rompatch_activate;
  127. struct {
  128. __le32 count;
  129. __le32 patch_ids[]; /* length of @count */
  130. } rompatch_deactivate;
  131. struct {
  132. __le32 addr;
  133. } lz_start;
  134. struct {
  135. __le32 len; /* max BMI_MAX_DATA_SIZE */
  136. u8 payload[]; /* length of @len */
  137. } lz_data;
  138. struct {
  139. u8 name[BMI_NVRAM_SEG_NAME_SZ];
  140. } nvram_process;
  141. u8 payload[BMI_MAX_CMDBUF_SIZE];
  142. };
  143. } __packed;
  144. union bmi_resp {
  145. struct {
  146. DECLARE_FLEX_ARRAY(u8, payload);
  147. } read_mem;
  148. struct {
  149. __le32 result;
  150. } execute;
  151. struct {
  152. __le32 value;
  153. } read_soc_reg;
  154. struct {
  155. __le32 len;
  156. __le32 version;
  157. __le32 type;
  158. } get_target_info;
  159. struct {
  160. __le32 patch_id;
  161. } rompatch_install;
  162. struct {
  163. __le32 patch_id;
  164. } rompatch_uninstall;
  165. struct {
  166. /* 0 = nothing executed
  167. * otherwise = NVRAM segment return value
  168. */
  169. __le32 result;
  170. } nvram_process;
  171. u8 payload[BMI_MAX_CMDBUF_SIZE];
  172. } __packed;
  173. struct bmi_target_info {
  174. u32 version;
  175. u32 type;
  176. };
  177. struct bmi_segmented_file_header {
  178. __le32 magic_num;
  179. __le32 file_flags;
  180. u8 data[];
  181. };
  182. struct bmi_segmented_metadata {
  183. __le32 addr;
  184. __le32 length;
  185. u8 data[];
  186. };
  187. #define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */
  188. #define BMI_SGMTFILE_FLAG_COMPRESS 1
  189. /* Special values for bmi_segmented_metadata.length (all have high bit set) */
  190. /* end of segmented data */
  191. #define BMI_SGMTFILE_DONE 0xffffffff
  192. /* Board Data segment */
  193. #define BMI_SGMTFILE_BDDATA 0xfffffffe
  194. /* set beginning address */
  195. #define BMI_SGMTFILE_BEGINADDR 0xfffffffd
  196. /* immediate function execution */
  197. #define BMI_SGMTFILE_EXEC 0xfffffffc
  198. /* in jiffies */
  199. #define BMI_COMMUNICATION_TIMEOUT_HZ (3 * HZ)
  200. #define BMI_CE_NUM_TO_TARG 0
  201. #define BMI_CE_NUM_TO_HOST 1
  202. void ath10k_bmi_start(struct ath10k *ar);
  203. int ath10k_bmi_done(struct ath10k *ar);
  204. int ath10k_bmi_get_target_info(struct ath10k *ar,
  205. struct bmi_target_info *target_info);
  206. int ath10k_bmi_get_target_info_sdio(struct ath10k *ar,
  207. struct bmi_target_info *target_info);
  208. int ath10k_bmi_read_memory(struct ath10k *ar, u32 address,
  209. void *buffer, u32 length);
  210. int ath10k_bmi_write_memory(struct ath10k *ar, u32 address,
  211. const void *buffer, u32 length);
  212. #define ath10k_bmi_read32(ar, item, val) \
  213. ({ \
  214. int ret; \
  215. u32 addr; \
  216. __le32 tmp; \
  217. \
  218. addr = host_interest_item_address(HI_ITEM(item)); \
  219. ret = ath10k_bmi_read_memory(ar, addr, (u8 *)&tmp, 4); \
  220. if (!ret) \
  221. *val = __le32_to_cpu(tmp); \
  222. ret; \
  223. })
  224. #define ath10k_bmi_write32(ar, item, val) \
  225. ({ \
  226. int ret; \
  227. u32 address; \
  228. __le32 v = __cpu_to_le32(val); \
  229. \
  230. address = host_interest_item_address(HI_ITEM(item)); \
  231. ret = ath10k_bmi_write_memory(ar, address, \
  232. (u8 *)&v, sizeof(v)); \
  233. ret; \
  234. })
  235. int ath10k_bmi_execute(struct ath10k *ar, u32 address, u32 param, u32 *result);
  236. int ath10k_bmi_lz_stream_start(struct ath10k *ar, u32 address);
  237. int ath10k_bmi_lz_data(struct ath10k *ar, const void *buffer, u32 length);
  238. int ath10k_bmi_fast_download(struct ath10k *ar, u32 address,
  239. const void *buffer, u32 length);
  240. int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val);
  241. int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val);
  242. int ath10k_bmi_set_start(struct ath10k *ar, u32 address);
  243. #endif /* _BMI_H_ */