slic_ds26522.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * drivers/net/wan/slic_ds26522.c
  4. *
  5. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  6. *
  7. * Author:Zhao Qiang<[email protected]>
  8. */
  9. #include <linux/bitrev.h>
  10. #include <linux/module.h>
  11. #include <linux/device.h>
  12. #include <linux/kernel.h>
  13. #include <linux/sched.h>
  14. #include <linux/kthread.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/wait.h>
  17. #include <linux/param.h>
  18. #include <linux/delay.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/io.h>
  22. #include "slic_ds26522.h"
  23. #define SLIC_TRANS_LEN 1
  24. #define SLIC_TWO_LEN 2
  25. #define SLIC_THREE_LEN 3
  26. static struct spi_device *g_spi;
  27. MODULE_LICENSE("GPL");
  28. MODULE_AUTHOR("Zhao Qiang<[email protected]>");
  29. /* the read/write format of address is
  30. * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x
  31. */
  32. static void slic_write(struct spi_device *spi, u16 addr,
  33. u8 data)
  34. {
  35. u8 temp[3];
  36. addr = bitrev16(addr) >> 1;
  37. data = bitrev8(data);
  38. temp[0] = (u8)((addr >> 8) & 0x7f);
  39. temp[1] = (u8)(addr & 0xfe);
  40. temp[2] = data;
  41. /* write spi addr and value */
  42. spi_write(spi, &temp[0], SLIC_THREE_LEN);
  43. }
  44. static u8 slic_read(struct spi_device *spi, u16 addr)
  45. {
  46. u8 temp[2];
  47. u8 data;
  48. addr = bitrev16(addr) >> 1;
  49. temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80);
  50. temp[1] = (u8)(addr & 0xfe);
  51. spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data,
  52. SLIC_TRANS_LEN);
  53. data = bitrev8(data);
  54. return data;
  55. }
  56. static bool get_slic_product_code(struct spi_device *spi)
  57. {
  58. u8 device_id;
  59. device_id = slic_read(spi, DS26522_IDR_ADDR);
  60. if ((device_id & 0xf8) == 0x68)
  61. return true;
  62. else
  63. return false;
  64. }
  65. static void ds26522_e1_spec_config(struct spi_device *spi)
  66. {
  67. /* Receive E1 Mode, Framer Disabled */
  68. slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
  69. /* Transmit E1 Mode, Framer Disable */
  70. slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
  71. /* Receive E1 Mode Framer Enable */
  72. slic_write(spi, DS26522_RMMR_ADDR,
  73. slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN);
  74. /* Transmit E1 Mode Framer Enable */
  75. slic_write(spi, DS26522_TMMR_ADDR,
  76. slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN);
  77. /* RCR1, receive E1 B8zs & ESF */
  78. slic_write(spi, DS26522_RCR1_ADDR,
  79. DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS);
  80. /* RSYSCLK=2.048MHz, RSYNC-Output */
  81. slic_write(spi, DS26522_RIOCR_ADDR,
  82. DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT);
  83. /* TCR1 Transmit E1 b8zs */
  84. slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
  85. /* TSYSCLK=2.048MHz, TSYNC-Output */
  86. slic_write(spi, DS26522_TIOCR_ADDR,
  87. DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT);
  88. /* Set E1TAF */
  89. slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
  90. /* Set E1TNAF register */
  91. slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
  92. /* Receive E1 Mode Framer Enable & init Done */
  93. slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
  94. DS26522_RMMR_INIT_DONE);
  95. /* Transmit E1 Mode Framer Enable & init Done */
  96. slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
  97. DS26522_TMMR_INIT_DONE);
  98. /* Configure LIU E1 mode */
  99. slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
  100. /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */
  101. slic_write(spi, DS26522_LTITSR_ADDR,
  102. DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM);
  103. /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */
  104. slic_write(spi, DS26522_LRISMR_ADDR,
  105. DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX);
  106. /* Enable Transmit output */
  107. slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
  108. }
  109. static int slic_ds26522_init_configure(struct spi_device *spi)
  110. {
  111. u16 addr;
  112. /* set clock */
  113. slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
  114. DS26522_GTCCR_BFREQSEL_2048KHZ |
  115. DS26522_GTCCR_FREQSEL_2048KHZ);
  116. slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
  117. slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
  118. /* set gtcr */
  119. slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
  120. /* Global LIU Software Reset Register */
  121. slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
  122. /* Global Framer and BERT Software Reset Register */
  123. slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
  124. usleep_range(100, 120);
  125. slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
  126. slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
  127. /* Perform RX/TX SRESET,Reset receiver */
  128. slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
  129. /* Reset tranceiver */
  130. slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
  131. usleep_range(100, 120);
  132. /* Zero all Framer Registers */
  133. for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END;
  134. addr++)
  135. slic_write(spi, addr, 0);
  136. for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END;
  137. addr++)
  138. slic_write(spi, addr, 0);
  139. for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END;
  140. addr++)
  141. slic_write(spi, addr, 0);
  142. for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END;
  143. addr++)
  144. slic_write(spi, addr, 0);
  145. /* setup ds26522 for E1 specification */
  146. ds26522_e1_spec_config(spi);
  147. slic_write(spi, DS26522_GTCR1_ADDR, 0x00);
  148. return 0;
  149. }
  150. static void slic_ds26522_remove(struct spi_device *spi)
  151. {
  152. pr_info("DS26522 module uninstalled\n");
  153. }
  154. static int slic_ds26522_probe(struct spi_device *spi)
  155. {
  156. int ret = 0;
  157. g_spi = spi;
  158. spi->bits_per_word = 8;
  159. if (!get_slic_product_code(spi))
  160. return ret;
  161. ret = slic_ds26522_init_configure(spi);
  162. if (ret == 0)
  163. pr_info("DS26522 cs%d configured\n", spi->chip_select);
  164. return ret;
  165. }
  166. static const struct spi_device_id slic_ds26522_id[] = {
  167. { .name = "ds26522" },
  168. { /* sentinel */ },
  169. };
  170. MODULE_DEVICE_TABLE(spi, slic_ds26522_id);
  171. static const struct of_device_id slic_ds26522_match[] = {
  172. {
  173. .compatible = "maxim,ds26522",
  174. },
  175. {},
  176. };
  177. MODULE_DEVICE_TABLE(of, slic_ds26522_match);
  178. static struct spi_driver slic_ds26522_driver = {
  179. .driver = {
  180. .name = "ds26522",
  181. .bus = &spi_bus_type,
  182. .of_match_table = slic_ds26522_match,
  183. },
  184. .probe = slic_ds26522_probe,
  185. .remove = slic_ds26522_remove,
  186. .id_table = slic_ds26522_id,
  187. };
  188. module_spi_driver(slic_ds26522_driver);