smsc75xx.c 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /***************************************************************************
  3. *
  4. * Copyright (C) 2007-2010 SMSC
  5. *
  6. *****************************************************************************/
  7. #include <linux/module.h>
  8. #include <linux/kmod.h>
  9. #include <linux/netdevice.h>
  10. #include <linux/etherdevice.h>
  11. #include <linux/ethtool.h>
  12. #include <linux/mii.h>
  13. #include <linux/usb.h>
  14. #include <linux/bitrev.h>
  15. #include <linux/crc16.h>
  16. #include <linux/crc32.h>
  17. #include <linux/usb/usbnet.h>
  18. #include <linux/slab.h>
  19. #include <linux/of_net.h>
  20. #include "smsc75xx.h"
  21. #define SMSC_CHIPNAME "smsc75xx"
  22. #define SMSC_DRIVER_VERSION "1.0.0"
  23. #define HS_USB_PKT_SIZE (512)
  24. #define FS_USB_PKT_SIZE (64)
  25. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  26. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  27. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  28. #define MAX_SINGLE_PACKET_SIZE (9000)
  29. #define LAN75XX_EEPROM_MAGIC (0x7500)
  30. #define EEPROM_MAC_OFFSET (0x01)
  31. #define DEFAULT_TX_CSUM_ENABLE (true)
  32. #define DEFAULT_RX_CSUM_ENABLE (true)
  33. #define SMSC75XX_INTERNAL_PHY_ID (1)
  34. #define SMSC75XX_TX_OVERHEAD (8)
  35. #define MAX_RX_FIFO_SIZE (20 * 1024)
  36. #define MAX_TX_FIFO_SIZE (12 * 1024)
  37. #define USB_VENDOR_ID_SMSC (0x0424)
  38. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  39. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  40. #define RXW_PADDING 2
  41. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  42. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  43. #define SUSPEND_SUSPEND0 (0x01)
  44. #define SUSPEND_SUSPEND1 (0x02)
  45. #define SUSPEND_SUSPEND2 (0x04)
  46. #define SUSPEND_SUSPEND3 (0x08)
  47. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  48. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  49. struct smsc75xx_priv {
  50. struct usbnet *dev;
  51. u32 rfe_ctl;
  52. u32 wolopts;
  53. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  54. struct mutex dataport_mutex;
  55. spinlock_t rfe_ctl_lock;
  56. struct work_struct set_multicast;
  57. u8 suspend_flags;
  58. };
  59. struct usb_context {
  60. struct usb_ctrlrequest req;
  61. struct usbnet *dev;
  62. };
  63. static bool turbo_mode = true;
  64. module_param(turbo_mode, bool, 0644);
  65. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  66. static int smsc75xx_link_ok_nopm(struct usbnet *dev);
  67. static int smsc75xx_phy_gig_workaround(struct usbnet *dev);
  68. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  69. u32 *data, int in_pm)
  70. {
  71. u32 buf;
  72. int ret;
  73. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  74. BUG_ON(!dev);
  75. if (!in_pm)
  76. fn = usbnet_read_cmd;
  77. else
  78. fn = usbnet_read_cmd_nopm;
  79. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  80. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  81. 0, index, &buf, 4);
  82. if (unlikely(ret < 4)) {
  83. ret = ret < 0 ? ret : -ENODATA;
  84. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  85. index, ret);
  86. return ret;
  87. }
  88. le32_to_cpus(&buf);
  89. *data = buf;
  90. return ret;
  91. }
  92. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  93. u32 data, int in_pm)
  94. {
  95. u32 buf;
  96. int ret;
  97. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  98. BUG_ON(!dev);
  99. if (!in_pm)
  100. fn = usbnet_write_cmd;
  101. else
  102. fn = usbnet_write_cmd_nopm;
  103. buf = data;
  104. cpu_to_le32s(&buf);
  105. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  106. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  107. 0, index, &buf, 4);
  108. if (unlikely(ret < 0))
  109. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  110. index, ret);
  111. return ret;
  112. }
  113. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  114. u32 *data)
  115. {
  116. return __smsc75xx_read_reg(dev, index, data, 1);
  117. }
  118. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  119. u32 data)
  120. {
  121. return __smsc75xx_write_reg(dev, index, data, 1);
  122. }
  123. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  124. u32 *data)
  125. {
  126. return __smsc75xx_read_reg(dev, index, data, 0);
  127. }
  128. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  129. u32 data)
  130. {
  131. return __smsc75xx_write_reg(dev, index, data, 0);
  132. }
  133. /* Loop until the read is completed with timeout
  134. * called with phy_mutex held */
  135. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  136. int in_pm)
  137. {
  138. unsigned long start_time = jiffies;
  139. u32 val;
  140. int ret;
  141. do {
  142. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  143. if (ret < 0) {
  144. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  145. return ret;
  146. }
  147. if (!(val & MII_ACCESS_BUSY))
  148. return 0;
  149. } while (!time_after(jiffies, start_time + HZ));
  150. return -EIO;
  151. }
  152. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  153. int in_pm)
  154. {
  155. struct usbnet *dev = netdev_priv(netdev);
  156. u32 val, addr;
  157. int ret;
  158. mutex_lock(&dev->phy_mutex);
  159. /* confirm MII not busy */
  160. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  161. if (ret < 0) {
  162. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  163. goto done;
  164. }
  165. /* set the address, index & direction (read from PHY) */
  166. phy_id &= dev->mii.phy_id_mask;
  167. idx &= dev->mii.reg_num_mask;
  168. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  169. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  170. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  171. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  172. if (ret < 0) {
  173. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  174. goto done;
  175. }
  176. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  177. if (ret < 0) {
  178. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  179. goto done;
  180. }
  181. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  182. if (ret < 0) {
  183. netdev_warn(dev->net, "Error reading MII_DATA\n");
  184. goto done;
  185. }
  186. ret = (u16)(val & 0xFFFF);
  187. done:
  188. mutex_unlock(&dev->phy_mutex);
  189. return ret;
  190. }
  191. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  192. int idx, int regval, int in_pm)
  193. {
  194. struct usbnet *dev = netdev_priv(netdev);
  195. u32 val, addr;
  196. int ret;
  197. mutex_lock(&dev->phy_mutex);
  198. /* confirm MII not busy */
  199. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  200. if (ret < 0) {
  201. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  202. goto done;
  203. }
  204. val = regval;
  205. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  206. if (ret < 0) {
  207. netdev_warn(dev->net, "Error writing MII_DATA\n");
  208. goto done;
  209. }
  210. /* set the address, index & direction (write to PHY) */
  211. phy_id &= dev->mii.phy_id_mask;
  212. idx &= dev->mii.reg_num_mask;
  213. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  214. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  215. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  216. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  217. if (ret < 0) {
  218. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  219. goto done;
  220. }
  221. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  222. if (ret < 0) {
  223. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  224. goto done;
  225. }
  226. done:
  227. mutex_unlock(&dev->phy_mutex);
  228. }
  229. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  230. int idx)
  231. {
  232. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  233. }
  234. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  235. int idx, int regval)
  236. {
  237. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  238. }
  239. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  240. {
  241. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  242. }
  243. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  244. int regval)
  245. {
  246. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  247. }
  248. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  249. {
  250. unsigned long start_time = jiffies;
  251. u32 val;
  252. int ret;
  253. do {
  254. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  255. if (ret < 0) {
  256. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  257. return ret;
  258. }
  259. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  260. break;
  261. udelay(40);
  262. } while (!time_after(jiffies, start_time + HZ));
  263. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  264. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  265. return -EIO;
  266. }
  267. return 0;
  268. }
  269. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  270. {
  271. unsigned long start_time = jiffies;
  272. u32 val;
  273. int ret;
  274. do {
  275. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  276. if (ret < 0) {
  277. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  278. return ret;
  279. }
  280. if (!(val & E2P_CMD_BUSY))
  281. return 0;
  282. udelay(40);
  283. } while (!time_after(jiffies, start_time + HZ));
  284. netdev_warn(dev->net, "EEPROM is busy\n");
  285. return -EIO;
  286. }
  287. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  288. u8 *data)
  289. {
  290. u32 val;
  291. int i, ret;
  292. BUG_ON(!dev);
  293. BUG_ON(!data);
  294. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  295. if (ret)
  296. return ret;
  297. for (i = 0; i < length; i++) {
  298. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  299. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  300. if (ret < 0) {
  301. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  302. return ret;
  303. }
  304. ret = smsc75xx_wait_eeprom(dev);
  305. if (ret < 0)
  306. return ret;
  307. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  308. if (ret < 0) {
  309. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  310. return ret;
  311. }
  312. data[i] = val & 0xFF;
  313. offset++;
  314. }
  315. return 0;
  316. }
  317. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  318. u8 *data)
  319. {
  320. u32 val;
  321. int i, ret;
  322. BUG_ON(!dev);
  323. BUG_ON(!data);
  324. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  325. if (ret)
  326. return ret;
  327. /* Issue write/erase enable command */
  328. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  329. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  330. if (ret < 0) {
  331. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  332. return ret;
  333. }
  334. ret = smsc75xx_wait_eeprom(dev);
  335. if (ret < 0)
  336. return ret;
  337. for (i = 0; i < length; i++) {
  338. /* Fill data register */
  339. val = data[i];
  340. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  341. if (ret < 0) {
  342. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  343. return ret;
  344. }
  345. /* Send "write" command */
  346. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  347. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  348. if (ret < 0) {
  349. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  350. return ret;
  351. }
  352. ret = smsc75xx_wait_eeprom(dev);
  353. if (ret < 0)
  354. return ret;
  355. offset++;
  356. }
  357. return 0;
  358. }
  359. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  360. {
  361. int i, ret;
  362. for (i = 0; i < 100; i++) {
  363. u32 dp_sel;
  364. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  365. if (ret < 0) {
  366. netdev_warn(dev->net, "Error reading DP_SEL\n");
  367. return ret;
  368. }
  369. if (dp_sel & DP_SEL_DPRDY)
  370. return 0;
  371. udelay(40);
  372. }
  373. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  374. return -EIO;
  375. }
  376. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  377. u32 length, u32 *buf)
  378. {
  379. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  380. u32 dp_sel;
  381. int i, ret;
  382. mutex_lock(&pdata->dataport_mutex);
  383. ret = smsc75xx_dataport_wait_not_busy(dev);
  384. if (ret < 0) {
  385. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  386. goto done;
  387. }
  388. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  389. if (ret < 0) {
  390. netdev_warn(dev->net, "Error reading DP_SEL\n");
  391. goto done;
  392. }
  393. dp_sel &= ~DP_SEL_RSEL;
  394. dp_sel |= ram_select;
  395. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  396. if (ret < 0) {
  397. netdev_warn(dev->net, "Error writing DP_SEL\n");
  398. goto done;
  399. }
  400. for (i = 0; i < length; i++) {
  401. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  402. if (ret < 0) {
  403. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  404. goto done;
  405. }
  406. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  407. if (ret < 0) {
  408. netdev_warn(dev->net, "Error writing DP_DATA\n");
  409. goto done;
  410. }
  411. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  412. if (ret < 0) {
  413. netdev_warn(dev->net, "Error writing DP_CMD\n");
  414. goto done;
  415. }
  416. ret = smsc75xx_dataport_wait_not_busy(dev);
  417. if (ret < 0) {
  418. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  419. goto done;
  420. }
  421. }
  422. done:
  423. mutex_unlock(&pdata->dataport_mutex);
  424. return ret;
  425. }
  426. /* returns hash bit number for given MAC address */
  427. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  428. {
  429. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  430. }
  431. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  432. {
  433. struct smsc75xx_priv *pdata =
  434. container_of(param, struct smsc75xx_priv, set_multicast);
  435. struct usbnet *dev = pdata->dev;
  436. int ret;
  437. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  438. pdata->rfe_ctl);
  439. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  440. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  441. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  442. if (ret < 0)
  443. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  444. }
  445. static void smsc75xx_set_multicast(struct net_device *netdev)
  446. {
  447. struct usbnet *dev = netdev_priv(netdev);
  448. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  449. unsigned long flags;
  450. int i;
  451. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  452. pdata->rfe_ctl &=
  453. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  454. pdata->rfe_ctl |= RFE_CTL_AB;
  455. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  456. pdata->multicast_hash_table[i] = 0;
  457. if (dev->net->flags & IFF_PROMISC) {
  458. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  459. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  460. } else if (dev->net->flags & IFF_ALLMULTI) {
  461. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  462. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  463. } else if (!netdev_mc_empty(dev->net)) {
  464. struct netdev_hw_addr *ha;
  465. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  466. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  467. netdev_for_each_mc_addr(ha, netdev) {
  468. u32 bitnum = smsc75xx_hash(ha->addr);
  469. pdata->multicast_hash_table[bitnum / 32] |=
  470. (1 << (bitnum % 32));
  471. }
  472. } else {
  473. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  474. pdata->rfe_ctl |= RFE_CTL_DPF;
  475. }
  476. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  477. /* defer register writes to a sleepable context */
  478. schedule_work(&pdata->set_multicast);
  479. }
  480. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  481. u16 lcladv, u16 rmtadv)
  482. {
  483. u32 flow = 0, fct_flow = 0;
  484. int ret;
  485. if (duplex == DUPLEX_FULL) {
  486. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  487. if (cap & FLOW_CTRL_TX) {
  488. flow = (FLOW_TX_FCEN | 0xFFFF);
  489. /* set fct_flow thresholds to 20% and 80% */
  490. fct_flow = (8 << 8) | 32;
  491. }
  492. if (cap & FLOW_CTRL_RX)
  493. flow |= FLOW_RX_FCEN;
  494. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  495. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  496. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  497. } else {
  498. netif_dbg(dev, link, dev->net, "half duplex\n");
  499. }
  500. ret = smsc75xx_write_reg(dev, FLOW, flow);
  501. if (ret < 0) {
  502. netdev_warn(dev->net, "Error writing FLOW\n");
  503. return ret;
  504. }
  505. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  506. if (ret < 0) {
  507. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  508. return ret;
  509. }
  510. return 0;
  511. }
  512. static int smsc75xx_link_reset(struct usbnet *dev)
  513. {
  514. struct mii_if_info *mii = &dev->mii;
  515. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  516. u16 lcladv, rmtadv;
  517. int ret;
  518. /* write to clear phy interrupt status */
  519. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  520. PHY_INT_SRC_CLEAR_ALL);
  521. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  522. if (ret < 0) {
  523. netdev_warn(dev->net, "Error writing INT_STS\n");
  524. return ret;
  525. }
  526. mii_check_media(mii, 1, 1);
  527. mii_ethtool_gset(&dev->mii, &ecmd);
  528. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  529. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  530. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  531. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  532. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  533. }
  534. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  535. {
  536. u32 intdata;
  537. if (urb->actual_length != 4) {
  538. netdev_warn(dev->net, "unexpected urb length %d\n",
  539. urb->actual_length);
  540. return;
  541. }
  542. intdata = get_unaligned_le32(urb->transfer_buffer);
  543. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  544. if (intdata & INT_ENP_PHY_INT)
  545. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  546. else
  547. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  548. intdata);
  549. }
  550. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  551. {
  552. return MAX_EEPROM_SIZE;
  553. }
  554. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  555. struct ethtool_eeprom *ee, u8 *data)
  556. {
  557. struct usbnet *dev = netdev_priv(netdev);
  558. ee->magic = LAN75XX_EEPROM_MAGIC;
  559. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  560. }
  561. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  562. struct ethtool_eeprom *ee, u8 *data)
  563. {
  564. struct usbnet *dev = netdev_priv(netdev);
  565. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  566. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  567. ee->magic);
  568. return -EINVAL;
  569. }
  570. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  571. }
  572. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  573. struct ethtool_wolinfo *wolinfo)
  574. {
  575. struct usbnet *dev = netdev_priv(net);
  576. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  577. wolinfo->supported = SUPPORTED_WAKE;
  578. wolinfo->wolopts = pdata->wolopts;
  579. }
  580. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  581. struct ethtool_wolinfo *wolinfo)
  582. {
  583. struct usbnet *dev = netdev_priv(net);
  584. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  585. int ret;
  586. if (wolinfo->wolopts & ~SUPPORTED_WAKE)
  587. return -EINVAL;
  588. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  589. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  590. if (ret < 0)
  591. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  592. return ret;
  593. }
  594. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  595. .get_link = usbnet_get_link,
  596. .nway_reset = usbnet_nway_reset,
  597. .get_drvinfo = usbnet_get_drvinfo,
  598. .get_msglevel = usbnet_get_msglevel,
  599. .set_msglevel = usbnet_set_msglevel,
  600. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  601. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  602. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  603. .get_wol = smsc75xx_ethtool_get_wol,
  604. .set_wol = smsc75xx_ethtool_set_wol,
  605. .get_link_ksettings = usbnet_get_link_ksettings_mii,
  606. .set_link_ksettings = usbnet_set_link_ksettings_mii,
  607. };
  608. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  609. {
  610. struct usbnet *dev = netdev_priv(netdev);
  611. if (!netif_running(netdev))
  612. return -EINVAL;
  613. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  614. }
  615. static void smsc75xx_init_mac_address(struct usbnet *dev)
  616. {
  617. u8 addr[ETH_ALEN];
  618. /* maybe the boot loader passed the MAC address in devicetree */
  619. if (!platform_get_ethdev_address(&dev->udev->dev, dev->net)) {
  620. if (is_valid_ether_addr(dev->net->dev_addr)) {
  621. /* device tree values are valid so use them */
  622. netif_dbg(dev, ifup, dev->net, "MAC address read from the device tree\n");
  623. return;
  624. }
  625. }
  626. /* try reading mac address from EEPROM */
  627. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, addr) == 0) {
  628. eth_hw_addr_set(dev->net, addr);
  629. if (is_valid_ether_addr(dev->net->dev_addr)) {
  630. /* eeprom values are valid so use them */
  631. netif_dbg(dev, ifup, dev->net,
  632. "MAC address read from EEPROM\n");
  633. return;
  634. }
  635. }
  636. /* no useful static MAC address found. generate a random one */
  637. eth_hw_addr_random(dev->net);
  638. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  639. }
  640. static int smsc75xx_set_mac_address(struct usbnet *dev)
  641. {
  642. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  643. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  644. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  645. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  646. if (ret < 0) {
  647. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  648. return ret;
  649. }
  650. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  651. if (ret < 0) {
  652. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  653. return ret;
  654. }
  655. addr_hi |= ADDR_FILTX_FB_VALID;
  656. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  657. if (ret < 0) {
  658. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  659. return ret;
  660. }
  661. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  662. if (ret < 0)
  663. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  664. return ret;
  665. }
  666. static int smsc75xx_phy_initialize(struct usbnet *dev)
  667. {
  668. int bmcr, ret, timeout = 0;
  669. /* Initialize MII structure */
  670. dev->mii.dev = dev->net;
  671. dev->mii.mdio_read = smsc75xx_mdio_read;
  672. dev->mii.mdio_write = smsc75xx_mdio_write;
  673. dev->mii.phy_id_mask = 0x1f;
  674. dev->mii.reg_num_mask = 0x1f;
  675. dev->mii.supports_gmii = 1;
  676. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  677. /* reset phy and wait for reset to complete */
  678. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  679. do {
  680. msleep(10);
  681. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  682. if (bmcr < 0) {
  683. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  684. return bmcr;
  685. }
  686. timeout++;
  687. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  688. if (timeout >= 100) {
  689. netdev_warn(dev->net, "timeout on PHY Reset\n");
  690. return -EIO;
  691. }
  692. /* phy workaround for gig link */
  693. smsc75xx_phy_gig_workaround(dev);
  694. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  695. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  696. ADVERTISE_PAUSE_ASYM);
  697. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  698. ADVERTISE_1000FULL);
  699. /* read and write to clear phy interrupt status */
  700. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  701. if (ret < 0) {
  702. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  703. return ret;
  704. }
  705. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  706. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  707. PHY_INT_MASK_DEFAULT);
  708. mii_nway_restart(&dev->mii);
  709. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  710. return 0;
  711. }
  712. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  713. {
  714. int ret = 0;
  715. u32 buf;
  716. bool rxenabled;
  717. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  718. if (ret < 0) {
  719. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  720. return ret;
  721. }
  722. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  723. if (rxenabled) {
  724. buf &= ~MAC_RX_RXEN;
  725. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  726. if (ret < 0) {
  727. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  728. return ret;
  729. }
  730. }
  731. /* add 4 to size for FCS */
  732. buf &= ~MAC_RX_MAX_SIZE;
  733. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  734. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  735. if (ret < 0) {
  736. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  737. return ret;
  738. }
  739. if (rxenabled) {
  740. buf |= MAC_RX_RXEN;
  741. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  742. if (ret < 0) {
  743. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  744. return ret;
  745. }
  746. }
  747. return 0;
  748. }
  749. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  750. {
  751. struct usbnet *dev = netdev_priv(netdev);
  752. int ret;
  753. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  754. if (ret < 0) {
  755. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  756. return ret;
  757. }
  758. return usbnet_change_mtu(netdev, new_mtu);
  759. }
  760. /* Enable or disable Rx checksum offload engine */
  761. static int smsc75xx_set_features(struct net_device *netdev,
  762. netdev_features_t features)
  763. {
  764. struct usbnet *dev = netdev_priv(netdev);
  765. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  766. unsigned long flags;
  767. int ret;
  768. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  769. if (features & NETIF_F_RXCSUM)
  770. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  771. else
  772. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  773. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  774. /* it's racing here! */
  775. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  776. if (ret < 0) {
  777. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  778. return ret;
  779. }
  780. return 0;
  781. }
  782. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  783. {
  784. int timeout = 0;
  785. do {
  786. u32 buf;
  787. int ret;
  788. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  789. if (ret < 0) {
  790. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  791. return ret;
  792. }
  793. if (buf & PMT_CTL_DEV_RDY)
  794. return 0;
  795. msleep(10);
  796. timeout++;
  797. } while (timeout < 100);
  798. netdev_warn(dev->net, "timeout waiting for device ready\n");
  799. return -EIO;
  800. }
  801. static int smsc75xx_phy_gig_workaround(struct usbnet *dev)
  802. {
  803. struct mii_if_info *mii = &dev->mii;
  804. int ret = 0, timeout = 0;
  805. u32 buf, link_up = 0;
  806. /* Set the phy in Gig loopback */
  807. smsc75xx_mdio_write(dev->net, mii->phy_id, MII_BMCR, 0x4040);
  808. /* Wait for the link up */
  809. do {
  810. link_up = smsc75xx_link_ok_nopm(dev);
  811. usleep_range(10000, 20000);
  812. timeout++;
  813. } while ((!link_up) && (timeout < 1000));
  814. if (timeout >= 1000) {
  815. netdev_warn(dev->net, "Timeout waiting for PHY link up\n");
  816. return -EIO;
  817. }
  818. /* phy reset */
  819. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  820. if (ret < 0) {
  821. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  822. return ret;
  823. }
  824. buf |= PMT_CTL_PHY_RST;
  825. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  826. if (ret < 0) {
  827. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  828. return ret;
  829. }
  830. timeout = 0;
  831. do {
  832. usleep_range(10000, 20000);
  833. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  834. if (ret < 0) {
  835. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n",
  836. ret);
  837. return ret;
  838. }
  839. timeout++;
  840. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  841. if (timeout >= 100) {
  842. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  843. return -EIO;
  844. }
  845. return 0;
  846. }
  847. static int smsc75xx_reset(struct usbnet *dev)
  848. {
  849. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  850. u32 buf;
  851. int ret = 0, timeout;
  852. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  853. ret = smsc75xx_wait_ready(dev, 0);
  854. if (ret < 0) {
  855. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  856. return ret;
  857. }
  858. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  859. if (ret < 0) {
  860. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  861. return ret;
  862. }
  863. buf |= HW_CFG_LRST;
  864. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  865. if (ret < 0) {
  866. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  867. return ret;
  868. }
  869. timeout = 0;
  870. do {
  871. msleep(10);
  872. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  873. if (ret < 0) {
  874. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  875. return ret;
  876. }
  877. timeout++;
  878. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  879. if (timeout >= 100) {
  880. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  881. return -EIO;
  882. }
  883. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  884. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  885. if (ret < 0) {
  886. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  887. return ret;
  888. }
  889. buf |= PMT_CTL_PHY_RST;
  890. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  891. if (ret < 0) {
  892. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  893. return ret;
  894. }
  895. timeout = 0;
  896. do {
  897. msleep(10);
  898. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  899. if (ret < 0) {
  900. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  901. return ret;
  902. }
  903. timeout++;
  904. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  905. if (timeout >= 100) {
  906. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  907. return -EIO;
  908. }
  909. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  910. ret = smsc75xx_set_mac_address(dev);
  911. if (ret < 0) {
  912. netdev_warn(dev->net, "Failed to set mac address\n");
  913. return ret;
  914. }
  915. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  916. dev->net->dev_addr);
  917. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  918. if (ret < 0) {
  919. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  920. return ret;
  921. }
  922. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  923. buf);
  924. buf |= HW_CFG_BIR;
  925. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  926. if (ret < 0) {
  927. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  928. return ret;
  929. }
  930. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  931. if (ret < 0) {
  932. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  933. return ret;
  934. }
  935. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  936. buf);
  937. if (!turbo_mode) {
  938. buf = 0;
  939. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  940. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  941. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  942. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  943. } else {
  944. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  945. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  946. }
  947. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  948. (ulong)dev->rx_urb_size);
  949. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  950. if (ret < 0) {
  951. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  952. return ret;
  953. }
  954. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  955. if (ret < 0) {
  956. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  957. return ret;
  958. }
  959. netif_dbg(dev, ifup, dev->net,
  960. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  961. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  962. if (ret < 0) {
  963. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  964. return ret;
  965. }
  966. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  967. if (ret < 0) {
  968. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  969. return ret;
  970. }
  971. netif_dbg(dev, ifup, dev->net,
  972. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  973. if (turbo_mode) {
  974. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  975. if (ret < 0) {
  976. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  977. return ret;
  978. }
  979. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  980. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  981. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  982. if (ret < 0) {
  983. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  984. return ret;
  985. }
  986. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  987. if (ret < 0) {
  988. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  989. return ret;
  990. }
  991. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  992. }
  993. /* set FIFO sizes */
  994. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  995. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  996. if (ret < 0) {
  997. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  998. return ret;
  999. }
  1000. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  1001. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  1002. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  1003. if (ret < 0) {
  1004. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  1005. return ret;
  1006. }
  1007. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  1008. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  1009. if (ret < 0) {
  1010. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  1011. return ret;
  1012. }
  1013. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  1014. if (ret < 0) {
  1015. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  1016. return ret;
  1017. }
  1018. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  1019. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  1020. if (ret < 0) {
  1021. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  1022. return ret;
  1023. }
  1024. /* only set default GPIO/LED settings if no EEPROM is detected */
  1025. if (!(buf & E2P_CMD_LOADED)) {
  1026. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  1027. if (ret < 0) {
  1028. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  1029. return ret;
  1030. }
  1031. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  1032. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  1033. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  1034. if (ret < 0) {
  1035. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  1036. return ret;
  1037. }
  1038. }
  1039. ret = smsc75xx_write_reg(dev, FLOW, 0);
  1040. if (ret < 0) {
  1041. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  1042. return ret;
  1043. }
  1044. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  1045. if (ret < 0) {
  1046. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  1047. return ret;
  1048. }
  1049. /* Don't need rfe_ctl_lock during initialisation */
  1050. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1051. if (ret < 0) {
  1052. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1053. return ret;
  1054. }
  1055. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1056. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1057. if (ret < 0) {
  1058. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1059. return ret;
  1060. }
  1061. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1062. if (ret < 0) {
  1063. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1064. return ret;
  1065. }
  1066. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1067. pdata->rfe_ctl);
  1068. /* Enable or disable checksum offload engines */
  1069. smsc75xx_set_features(dev->net, dev->net->features);
  1070. smsc75xx_set_multicast(dev->net);
  1071. ret = smsc75xx_phy_initialize(dev);
  1072. if (ret < 0) {
  1073. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1074. return ret;
  1075. }
  1076. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1077. if (ret < 0) {
  1078. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1079. return ret;
  1080. }
  1081. /* enable PHY interrupts */
  1082. buf |= INT_ENP_PHY_INT;
  1083. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1084. if (ret < 0) {
  1085. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1086. return ret;
  1087. }
  1088. /* allow mac to detect speed and duplex from phy */
  1089. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1090. if (ret < 0) {
  1091. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1092. return ret;
  1093. }
  1094. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1095. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1096. if (ret < 0) {
  1097. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1098. return ret;
  1099. }
  1100. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1101. if (ret < 0) {
  1102. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1103. return ret;
  1104. }
  1105. buf |= MAC_TX_TXEN;
  1106. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1107. if (ret < 0) {
  1108. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1109. return ret;
  1110. }
  1111. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1112. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1113. if (ret < 0) {
  1114. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1115. return ret;
  1116. }
  1117. buf |= FCT_TX_CTL_EN;
  1118. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1119. if (ret < 0) {
  1120. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1121. return ret;
  1122. }
  1123. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1124. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1125. if (ret < 0) {
  1126. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1127. return ret;
  1128. }
  1129. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1130. if (ret < 0) {
  1131. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1132. return ret;
  1133. }
  1134. buf |= MAC_RX_RXEN;
  1135. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1136. if (ret < 0) {
  1137. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1138. return ret;
  1139. }
  1140. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1141. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1142. if (ret < 0) {
  1143. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1144. return ret;
  1145. }
  1146. buf |= FCT_RX_CTL_EN;
  1147. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1148. if (ret < 0) {
  1149. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1150. return ret;
  1151. }
  1152. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1153. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1154. return 0;
  1155. }
  1156. static const struct net_device_ops smsc75xx_netdev_ops = {
  1157. .ndo_open = usbnet_open,
  1158. .ndo_stop = usbnet_stop,
  1159. .ndo_start_xmit = usbnet_start_xmit,
  1160. .ndo_tx_timeout = usbnet_tx_timeout,
  1161. .ndo_get_stats64 = dev_get_tstats64,
  1162. .ndo_change_mtu = smsc75xx_change_mtu,
  1163. .ndo_set_mac_address = eth_mac_addr,
  1164. .ndo_validate_addr = eth_validate_addr,
  1165. .ndo_eth_ioctl = smsc75xx_ioctl,
  1166. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1167. .ndo_set_features = smsc75xx_set_features,
  1168. };
  1169. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1170. {
  1171. struct smsc75xx_priv *pdata = NULL;
  1172. int ret;
  1173. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1174. ret = usbnet_get_endpoints(dev, intf);
  1175. if (ret < 0) {
  1176. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1177. return ret;
  1178. }
  1179. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1180. GFP_KERNEL);
  1181. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1182. if (!pdata)
  1183. return -ENOMEM;
  1184. pdata->dev = dev;
  1185. spin_lock_init(&pdata->rfe_ctl_lock);
  1186. mutex_init(&pdata->dataport_mutex);
  1187. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1188. if (DEFAULT_TX_CSUM_ENABLE)
  1189. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1190. if (DEFAULT_RX_CSUM_ENABLE)
  1191. dev->net->features |= NETIF_F_RXCSUM;
  1192. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1193. NETIF_F_RXCSUM;
  1194. ret = smsc75xx_wait_ready(dev, 0);
  1195. if (ret < 0) {
  1196. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1197. goto free_pdata;
  1198. }
  1199. smsc75xx_init_mac_address(dev);
  1200. /* Init all registers */
  1201. ret = smsc75xx_reset(dev);
  1202. if (ret < 0) {
  1203. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1204. goto cancel_work;
  1205. }
  1206. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1207. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1208. dev->net->flags |= IFF_MULTICAST;
  1209. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1210. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1211. dev->net->max_mtu = MAX_SINGLE_PACKET_SIZE;
  1212. return 0;
  1213. cancel_work:
  1214. cancel_work_sync(&pdata->set_multicast);
  1215. free_pdata:
  1216. kfree(pdata);
  1217. dev->data[0] = 0;
  1218. return ret;
  1219. }
  1220. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1221. {
  1222. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1223. if (pdata) {
  1224. cancel_work_sync(&pdata->set_multicast);
  1225. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1226. kfree(pdata);
  1227. dev->data[0] = 0;
  1228. }
  1229. }
  1230. static u16 smsc_crc(const u8 *buffer, size_t len)
  1231. {
  1232. return bitrev16(crc16(0xFFFF, buffer, len));
  1233. }
  1234. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1235. u32 wuf_mask1)
  1236. {
  1237. int cfg_base = WUF_CFGX + filter * 4;
  1238. int mask_base = WUF_MASKX + filter * 16;
  1239. int ret;
  1240. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1241. if (ret < 0) {
  1242. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1243. return ret;
  1244. }
  1245. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1246. if (ret < 0) {
  1247. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1248. return ret;
  1249. }
  1250. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1251. if (ret < 0) {
  1252. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1253. return ret;
  1254. }
  1255. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1256. if (ret < 0) {
  1257. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1258. return ret;
  1259. }
  1260. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1261. if (ret < 0) {
  1262. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1263. return ret;
  1264. }
  1265. return 0;
  1266. }
  1267. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1268. {
  1269. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1270. u32 val;
  1271. int ret;
  1272. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1273. if (ret < 0) {
  1274. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1275. return ret;
  1276. }
  1277. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1278. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1279. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1280. if (ret < 0) {
  1281. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1282. return ret;
  1283. }
  1284. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1285. return 0;
  1286. }
  1287. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1288. {
  1289. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1290. u32 val;
  1291. int ret;
  1292. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1293. if (ret < 0) {
  1294. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1295. return ret;
  1296. }
  1297. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1298. val |= PMT_CTL_SUS_MODE_1;
  1299. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1300. if (ret < 0) {
  1301. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1302. return ret;
  1303. }
  1304. /* clear wol status, enable energy detection */
  1305. val &= ~PMT_CTL_WUPS;
  1306. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1307. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1308. if (ret < 0) {
  1309. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1310. return ret;
  1311. }
  1312. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1313. return 0;
  1314. }
  1315. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1316. {
  1317. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1318. u32 val;
  1319. int ret;
  1320. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1321. if (ret < 0) {
  1322. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1323. return ret;
  1324. }
  1325. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1326. val |= PMT_CTL_SUS_MODE_2;
  1327. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1328. if (ret < 0) {
  1329. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1330. return ret;
  1331. }
  1332. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1333. return 0;
  1334. }
  1335. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1336. {
  1337. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1338. u32 val;
  1339. int ret;
  1340. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1341. if (ret < 0) {
  1342. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1343. return ret;
  1344. }
  1345. if (val & FCT_RX_CTL_RXUSED) {
  1346. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1347. return -EBUSY;
  1348. }
  1349. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1350. if (ret < 0) {
  1351. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1352. return ret;
  1353. }
  1354. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1355. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1356. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1357. if (ret < 0) {
  1358. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1359. return ret;
  1360. }
  1361. /* clear wol status */
  1362. val &= ~PMT_CTL_WUPS;
  1363. val |= PMT_CTL_WUPS_WOL;
  1364. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1365. if (ret < 0) {
  1366. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1367. return ret;
  1368. }
  1369. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1370. return 0;
  1371. }
  1372. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1373. {
  1374. struct mii_if_info *mii = &dev->mii;
  1375. int ret;
  1376. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1377. /* read to clear */
  1378. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1379. if (ret < 0) {
  1380. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1381. return ret;
  1382. }
  1383. /* enable interrupt source */
  1384. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1385. if (ret < 0) {
  1386. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1387. return ret;
  1388. }
  1389. ret |= mask;
  1390. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1391. return 0;
  1392. }
  1393. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1394. {
  1395. struct mii_if_info *mii = &dev->mii;
  1396. int ret;
  1397. /* first, a dummy read, needed to latch some MII phys */
  1398. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1399. if (ret < 0) {
  1400. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1401. return ret;
  1402. }
  1403. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1404. if (ret < 0) {
  1405. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1406. return ret;
  1407. }
  1408. return !!(ret & BMSR_LSTATUS);
  1409. }
  1410. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1411. {
  1412. int ret;
  1413. if (!netif_running(dev->net)) {
  1414. /* interface is ifconfig down so fully power down hw */
  1415. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1416. return smsc75xx_enter_suspend2(dev);
  1417. }
  1418. if (!link_up) {
  1419. /* link is down so enter EDPD mode */
  1420. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1421. /* enable PHY wakeup events for if cable is attached */
  1422. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1423. PHY_INT_MASK_ANEG_COMP);
  1424. if (ret < 0) {
  1425. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1426. return ret;
  1427. }
  1428. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1429. return smsc75xx_enter_suspend1(dev);
  1430. }
  1431. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1432. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1433. PHY_INT_MASK_LINK_DOWN);
  1434. if (ret < 0) {
  1435. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1436. return ret;
  1437. }
  1438. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1439. return smsc75xx_enter_suspend3(dev);
  1440. }
  1441. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1442. {
  1443. struct usbnet *dev = usb_get_intfdata(intf);
  1444. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1445. u32 val, link_up;
  1446. int ret;
  1447. ret = usbnet_suspend(intf, message);
  1448. if (ret < 0) {
  1449. netdev_warn(dev->net, "usbnet_suspend error\n");
  1450. return ret;
  1451. }
  1452. if (pdata->suspend_flags) {
  1453. netdev_warn(dev->net, "error during last resume\n");
  1454. pdata->suspend_flags = 0;
  1455. }
  1456. /* determine if link is up using only _nopm functions */
  1457. link_up = smsc75xx_link_ok_nopm(dev);
  1458. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1459. ret = smsc75xx_autosuspend(dev, link_up);
  1460. goto done;
  1461. }
  1462. /* if we get this far we're not autosuspending */
  1463. /* if no wol options set, or if link is down and we're not waking on
  1464. * PHY activity, enter lowest power SUSPEND2 mode
  1465. */
  1466. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1467. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1468. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1469. /* disable energy detect (link up) & wake up events */
  1470. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1471. if (ret < 0) {
  1472. netdev_warn(dev->net, "Error reading WUCSR\n");
  1473. goto done;
  1474. }
  1475. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1476. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1477. if (ret < 0) {
  1478. netdev_warn(dev->net, "Error writing WUCSR\n");
  1479. goto done;
  1480. }
  1481. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1482. if (ret < 0) {
  1483. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1484. goto done;
  1485. }
  1486. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1487. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1488. if (ret < 0) {
  1489. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1490. goto done;
  1491. }
  1492. ret = smsc75xx_enter_suspend2(dev);
  1493. goto done;
  1494. }
  1495. if (pdata->wolopts & WAKE_PHY) {
  1496. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1497. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1498. if (ret < 0) {
  1499. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1500. goto done;
  1501. }
  1502. /* if link is down then configure EDPD and enter SUSPEND1,
  1503. * otherwise enter SUSPEND0 below
  1504. */
  1505. if (!link_up) {
  1506. struct mii_if_info *mii = &dev->mii;
  1507. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1508. /* enable energy detect power-down mode */
  1509. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1510. PHY_MODE_CTRL_STS);
  1511. if (ret < 0) {
  1512. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1513. goto done;
  1514. }
  1515. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1516. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1517. PHY_MODE_CTRL_STS, ret);
  1518. /* enter SUSPEND1 mode */
  1519. ret = smsc75xx_enter_suspend1(dev);
  1520. goto done;
  1521. }
  1522. }
  1523. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1524. int i, filter = 0;
  1525. /* disable all filters */
  1526. for (i = 0; i < WUF_NUM; i++) {
  1527. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1528. if (ret < 0) {
  1529. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1530. goto done;
  1531. }
  1532. }
  1533. if (pdata->wolopts & WAKE_MCAST) {
  1534. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1535. netdev_info(dev->net, "enabling multicast detection\n");
  1536. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1537. | smsc_crc(mcast, 3);
  1538. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1539. if (ret < 0) {
  1540. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1541. goto done;
  1542. }
  1543. }
  1544. if (pdata->wolopts & WAKE_ARP) {
  1545. const u8 arp[] = {0x08, 0x06};
  1546. netdev_info(dev->net, "enabling ARP detection\n");
  1547. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1548. | smsc_crc(arp, 2);
  1549. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1550. if (ret < 0) {
  1551. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1552. goto done;
  1553. }
  1554. }
  1555. /* clear any pending pattern match packet status */
  1556. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1557. if (ret < 0) {
  1558. netdev_warn(dev->net, "Error reading WUCSR\n");
  1559. goto done;
  1560. }
  1561. val |= WUCSR_WUFR;
  1562. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1563. if (ret < 0) {
  1564. netdev_warn(dev->net, "Error writing WUCSR\n");
  1565. goto done;
  1566. }
  1567. netdev_info(dev->net, "enabling packet match detection\n");
  1568. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1569. if (ret < 0) {
  1570. netdev_warn(dev->net, "Error reading WUCSR\n");
  1571. goto done;
  1572. }
  1573. val |= WUCSR_WUEN;
  1574. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1575. if (ret < 0) {
  1576. netdev_warn(dev->net, "Error writing WUCSR\n");
  1577. goto done;
  1578. }
  1579. } else {
  1580. netdev_info(dev->net, "disabling packet match detection\n");
  1581. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1582. if (ret < 0) {
  1583. netdev_warn(dev->net, "Error reading WUCSR\n");
  1584. goto done;
  1585. }
  1586. val &= ~WUCSR_WUEN;
  1587. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1588. if (ret < 0) {
  1589. netdev_warn(dev->net, "Error writing WUCSR\n");
  1590. goto done;
  1591. }
  1592. }
  1593. /* disable magic, bcast & unicast wakeup sources */
  1594. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1595. if (ret < 0) {
  1596. netdev_warn(dev->net, "Error reading WUCSR\n");
  1597. goto done;
  1598. }
  1599. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1600. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1601. if (ret < 0) {
  1602. netdev_warn(dev->net, "Error writing WUCSR\n");
  1603. goto done;
  1604. }
  1605. if (pdata->wolopts & WAKE_PHY) {
  1606. netdev_info(dev->net, "enabling PHY wakeup\n");
  1607. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1608. if (ret < 0) {
  1609. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1610. goto done;
  1611. }
  1612. /* clear wol status, enable energy detection */
  1613. val &= ~PMT_CTL_WUPS;
  1614. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1615. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1616. if (ret < 0) {
  1617. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1618. goto done;
  1619. }
  1620. }
  1621. if (pdata->wolopts & WAKE_MAGIC) {
  1622. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1623. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1624. if (ret < 0) {
  1625. netdev_warn(dev->net, "Error reading WUCSR\n");
  1626. goto done;
  1627. }
  1628. /* clear any pending magic packet status */
  1629. val |= WUCSR_MPR | WUCSR_MPEN;
  1630. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1631. if (ret < 0) {
  1632. netdev_warn(dev->net, "Error writing WUCSR\n");
  1633. goto done;
  1634. }
  1635. }
  1636. if (pdata->wolopts & WAKE_BCAST) {
  1637. netdev_info(dev->net, "enabling broadcast detection\n");
  1638. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1639. if (ret < 0) {
  1640. netdev_warn(dev->net, "Error reading WUCSR\n");
  1641. goto done;
  1642. }
  1643. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1644. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1645. if (ret < 0) {
  1646. netdev_warn(dev->net, "Error writing WUCSR\n");
  1647. goto done;
  1648. }
  1649. }
  1650. if (pdata->wolopts & WAKE_UCAST) {
  1651. netdev_info(dev->net, "enabling unicast detection\n");
  1652. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1653. if (ret < 0) {
  1654. netdev_warn(dev->net, "Error reading WUCSR\n");
  1655. goto done;
  1656. }
  1657. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1658. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1659. if (ret < 0) {
  1660. netdev_warn(dev->net, "Error writing WUCSR\n");
  1661. goto done;
  1662. }
  1663. }
  1664. /* enable receiver to enable frame reception */
  1665. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1666. if (ret < 0) {
  1667. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1668. goto done;
  1669. }
  1670. val |= MAC_RX_RXEN;
  1671. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1672. if (ret < 0) {
  1673. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1674. goto done;
  1675. }
  1676. /* some wol options are enabled, so enter SUSPEND0 */
  1677. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1678. ret = smsc75xx_enter_suspend0(dev);
  1679. done:
  1680. /*
  1681. * TODO: resume() might need to handle the suspend failure
  1682. * in system sleep
  1683. */
  1684. if (ret && PMSG_IS_AUTO(message))
  1685. usbnet_resume(intf);
  1686. return ret;
  1687. }
  1688. static int smsc75xx_resume(struct usb_interface *intf)
  1689. {
  1690. struct usbnet *dev = usb_get_intfdata(intf);
  1691. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1692. u8 suspend_flags = pdata->suspend_flags;
  1693. int ret;
  1694. u32 val;
  1695. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1696. /* do this first to ensure it's cleared even in error case */
  1697. pdata->suspend_flags = 0;
  1698. if (suspend_flags & SUSPEND_ALLMODES) {
  1699. /* Disable wakeup sources */
  1700. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1701. if (ret < 0) {
  1702. netdev_warn(dev->net, "Error reading WUCSR\n");
  1703. return ret;
  1704. }
  1705. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1706. | WUCSR_BCST_EN);
  1707. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1708. if (ret < 0) {
  1709. netdev_warn(dev->net, "Error writing WUCSR\n");
  1710. return ret;
  1711. }
  1712. /* clear wake-up status */
  1713. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1714. if (ret < 0) {
  1715. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1716. return ret;
  1717. }
  1718. val &= ~PMT_CTL_WOL_EN;
  1719. val |= PMT_CTL_WUPS;
  1720. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1721. if (ret < 0) {
  1722. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1723. return ret;
  1724. }
  1725. }
  1726. if (suspend_flags & SUSPEND_SUSPEND2) {
  1727. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1728. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1729. if (ret < 0) {
  1730. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1731. return ret;
  1732. }
  1733. val |= PMT_CTL_PHY_PWRUP;
  1734. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1735. if (ret < 0) {
  1736. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1737. return ret;
  1738. }
  1739. }
  1740. ret = smsc75xx_wait_ready(dev, 1);
  1741. if (ret < 0) {
  1742. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1743. return ret;
  1744. }
  1745. return usbnet_resume(intf);
  1746. }
  1747. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1748. u32 rx_cmd_a, u32 rx_cmd_b)
  1749. {
  1750. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1751. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1752. skb->ip_summed = CHECKSUM_NONE;
  1753. } else {
  1754. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1755. skb->ip_summed = CHECKSUM_COMPLETE;
  1756. }
  1757. }
  1758. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1759. {
  1760. /* This check is no longer done by usbnet */
  1761. if (skb->len < dev->net->hard_header_len)
  1762. return 0;
  1763. while (skb->len > 0) {
  1764. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1765. struct sk_buff *ax_skb;
  1766. unsigned char *packet;
  1767. rx_cmd_a = get_unaligned_le32(skb->data);
  1768. skb_pull(skb, 4);
  1769. rx_cmd_b = get_unaligned_le32(skb->data);
  1770. skb_pull(skb, 4 + RXW_PADDING);
  1771. packet = skb->data;
  1772. /* get the packet length */
  1773. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1774. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1775. if (unlikely(size > skb->len)) {
  1776. netif_dbg(dev, rx_err, dev->net,
  1777. "size err rx_cmd_a=0x%08x\n",
  1778. rx_cmd_a);
  1779. return 0;
  1780. }
  1781. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1782. netif_dbg(dev, rx_err, dev->net,
  1783. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1784. dev->net->stats.rx_errors++;
  1785. dev->net->stats.rx_dropped++;
  1786. if (rx_cmd_a & RX_CMD_A_FCS)
  1787. dev->net->stats.rx_crc_errors++;
  1788. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1789. dev->net->stats.rx_frame_errors++;
  1790. } else {
  1791. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1792. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1793. netif_dbg(dev, rx_err, dev->net,
  1794. "size err rx_cmd_a=0x%08x\n",
  1795. rx_cmd_a);
  1796. return 0;
  1797. }
  1798. /* last frame in this batch */
  1799. if (skb->len == size) {
  1800. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1801. rx_cmd_b);
  1802. skb_trim(skb, skb->len - 4); /* remove fcs */
  1803. skb->truesize = size + sizeof(struct sk_buff);
  1804. return 1;
  1805. }
  1806. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1807. if (unlikely(!ax_skb)) {
  1808. netdev_warn(dev->net, "Error allocating skb\n");
  1809. return 0;
  1810. }
  1811. ax_skb->len = size;
  1812. ax_skb->data = packet;
  1813. skb_set_tail_pointer(ax_skb, size);
  1814. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1815. rx_cmd_b);
  1816. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1817. ax_skb->truesize = size + sizeof(struct sk_buff);
  1818. usbnet_skb_return(dev, ax_skb);
  1819. }
  1820. skb_pull(skb, size);
  1821. /* padding bytes before the next frame starts */
  1822. if (skb->len)
  1823. skb_pull(skb, align_count);
  1824. }
  1825. return 1;
  1826. }
  1827. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1828. struct sk_buff *skb, gfp_t flags)
  1829. {
  1830. u32 tx_cmd_a, tx_cmd_b;
  1831. void *ptr;
  1832. if (skb_cow_head(skb, SMSC75XX_TX_OVERHEAD)) {
  1833. dev_kfree_skb_any(skb);
  1834. return NULL;
  1835. }
  1836. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1837. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1838. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1839. if (skb_is_gso(skb)) {
  1840. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1841. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1842. tx_cmd_a |= TX_CMD_A_LSO;
  1843. } else {
  1844. tx_cmd_b = 0;
  1845. }
  1846. ptr = skb_push(skb, 8);
  1847. put_unaligned_le32(tx_cmd_a, ptr);
  1848. put_unaligned_le32(tx_cmd_b, ptr + 4);
  1849. return skb;
  1850. }
  1851. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1852. {
  1853. dev->intf->needs_remote_wakeup = on;
  1854. return 0;
  1855. }
  1856. static const struct driver_info smsc75xx_info = {
  1857. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1858. .bind = smsc75xx_bind,
  1859. .unbind = smsc75xx_unbind,
  1860. .link_reset = smsc75xx_link_reset,
  1861. .reset = smsc75xx_reset,
  1862. .rx_fixup = smsc75xx_rx_fixup,
  1863. .tx_fixup = smsc75xx_tx_fixup,
  1864. .status = smsc75xx_status,
  1865. .manage_power = smsc75xx_manage_power,
  1866. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1867. };
  1868. static const struct usb_device_id products[] = {
  1869. {
  1870. /* SMSC7500 USB Gigabit Ethernet Device */
  1871. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1872. .driver_info = (unsigned long) &smsc75xx_info,
  1873. },
  1874. {
  1875. /* SMSC7500 USB Gigabit Ethernet Device */
  1876. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1877. .driver_info = (unsigned long) &smsc75xx_info,
  1878. },
  1879. { }, /* END */
  1880. };
  1881. MODULE_DEVICE_TABLE(usb, products);
  1882. static struct usb_driver smsc75xx_driver = {
  1883. .name = SMSC_CHIPNAME,
  1884. .id_table = products,
  1885. .probe = usbnet_probe,
  1886. .suspend = smsc75xx_suspend,
  1887. .resume = smsc75xx_resume,
  1888. .reset_resume = smsc75xx_resume,
  1889. .disconnect = usbnet_disconnect,
  1890. .disable_hub_initiated_lpm = 1,
  1891. .supports_autosuspend = 1,
  1892. };
  1893. module_usb_driver(smsc75xx_driver);
  1894. MODULE_AUTHOR("Nancy Lin");
  1895. MODULE_AUTHOR("Steve Glendinning <[email protected]>");
  1896. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1897. MODULE_LICENSE("GPL");