mscc_serdes.h 874 B

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  1. /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
  2. /*
  3. * Driver for Microsemi VSC85xx PHYs
  4. *
  5. * Copyright (c) 2021 Microsemi Corporation
  6. */
  7. #ifndef _MSCC_SERDES_PHY_H_
  8. #define _MSCC_SERDES_PHY_H_
  9. #define PHY_S6G_PLL5G_CFG2_GAIN_MASK GENMASK(9, 5)
  10. #define PHY_S6G_PLL5G_CFG2_ENA_GAIN 1
  11. #define PHY_S6G_DES_PHY_CTRL_POS 13
  12. #define PHY_S6G_DES_MBTR_CTRL_POS 10
  13. #define PHY_S6G_DES_CPMD_SEL_POS 8
  14. #define PHY_S6G_DES_BW_HYST_POS 5
  15. #define PHY_S6G_DES_BW_ANA_POS 1
  16. #define PHY_S6G_DES_CFG 0x21
  17. #define PHY_S6G_IB_CFG0 0x22
  18. #define PHY_S6G_IB_CFG1 0x23
  19. #define PHY_S6G_IB_CFG2 0x24
  20. #define PHY_S6G_IB_CFG3 0x25
  21. #define PHY_S6G_IB_CFG4 0x26
  22. #define PHY_S6G_GP_CFG 0x2E
  23. #define PHY_S6G_DFT_CFG0 0x35
  24. #define PHY_S6G_IB_DFT_CFG2 0x37
  25. int vsc85xx_sd6g_config_v2(struct phy_device *phydev);
  26. #endif /* _MSCC_PHY_SERDES_H_ */