dp83640.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for the National Semiconductor DP83640 PHYTER
  4. *
  5. * Copyright (C) 2010 OMICRON electronics GmbH
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/crc32.h>
  9. #include <linux/ethtool.h>
  10. #include <linux/kernel.h>
  11. #include <linux/list.h>
  12. #include <linux/mii.h>
  13. #include <linux/module.h>
  14. #include <linux/net_tstamp.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/if_vlan.h>
  17. #include <linux/phy.h>
  18. #include <linux/ptp_classify.h>
  19. #include <linux/ptp_clock_kernel.h>
  20. #include "dp83640_reg.h"
  21. #define DP83640_PHY_ID 0x20005ce1
  22. #define PAGESEL 0x13
  23. #define MAX_RXTS 64
  24. #define N_EXT_TS 6
  25. #define N_PER_OUT 7
  26. #define PSF_PTPVER 2
  27. #define PSF_EVNT 0x4000
  28. #define PSF_RX 0x2000
  29. #define PSF_TX 0x1000
  30. #define EXT_EVENT 1
  31. #define CAL_EVENT 7
  32. #define CAL_TRIGGER 1
  33. #define DP83640_N_PINS 12
  34. #define MII_DP83640_MICR 0x11
  35. #define MII_DP83640_MISR 0x12
  36. #define MII_DP83640_MICR_OE 0x1
  37. #define MII_DP83640_MICR_IE 0x2
  38. #define MII_DP83640_MISR_RHF_INT_EN 0x01
  39. #define MII_DP83640_MISR_FHF_INT_EN 0x02
  40. #define MII_DP83640_MISR_ANC_INT_EN 0x04
  41. #define MII_DP83640_MISR_DUP_INT_EN 0x08
  42. #define MII_DP83640_MISR_SPD_INT_EN 0x10
  43. #define MII_DP83640_MISR_LINK_INT_EN 0x20
  44. #define MII_DP83640_MISR_ED_INT_EN 0x40
  45. #define MII_DP83640_MISR_LQ_INT_EN 0x80
  46. #define MII_DP83640_MISR_ANC_INT 0x400
  47. #define MII_DP83640_MISR_DUP_INT 0x800
  48. #define MII_DP83640_MISR_SPD_INT 0x1000
  49. #define MII_DP83640_MISR_LINK_INT 0x2000
  50. #define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\
  51. MII_DP83640_MISR_DUP_INT |\
  52. MII_DP83640_MISR_SPD_INT |\
  53. MII_DP83640_MISR_LINK_INT)
  54. /* phyter seems to miss the mark by 16 ns */
  55. #define ADJTIME_FIX 16
  56. #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
  57. #if defined(__BIG_ENDIAN)
  58. #define ENDIAN_FLAG 0
  59. #elif defined(__LITTLE_ENDIAN)
  60. #define ENDIAN_FLAG PSF_ENDIAN
  61. #endif
  62. struct dp83640_skb_info {
  63. int ptp_type;
  64. unsigned long tmo;
  65. };
  66. struct phy_rxts {
  67. u16 ns_lo; /* ns[15:0] */
  68. u16 ns_hi; /* overflow[1:0], ns[29:16] */
  69. u16 sec_lo; /* sec[15:0] */
  70. u16 sec_hi; /* sec[31:16] */
  71. u16 seqid; /* sequenceId[15:0] */
  72. u16 msgtype; /* messageType[3:0], hash[11:0] */
  73. };
  74. struct phy_txts {
  75. u16 ns_lo; /* ns[15:0] */
  76. u16 ns_hi; /* overflow[1:0], ns[29:16] */
  77. u16 sec_lo; /* sec[15:0] */
  78. u16 sec_hi; /* sec[31:16] */
  79. };
  80. struct rxts {
  81. struct list_head list;
  82. unsigned long tmo;
  83. u64 ns;
  84. u16 seqid;
  85. u8 msgtype;
  86. u16 hash;
  87. };
  88. struct dp83640_clock;
  89. struct dp83640_private {
  90. struct list_head list;
  91. struct dp83640_clock *clock;
  92. struct phy_device *phydev;
  93. struct mii_timestamper mii_ts;
  94. struct delayed_work ts_work;
  95. int hwts_tx_en;
  96. int hwts_rx_en;
  97. int layer;
  98. int version;
  99. /* remember state of cfg0 during calibration */
  100. int cfg0;
  101. /* remember the last event time stamp */
  102. struct phy_txts edata;
  103. /* list of rx timestamps */
  104. struct list_head rxts;
  105. struct list_head rxpool;
  106. struct rxts rx_pool_data[MAX_RXTS];
  107. /* protects above three fields from concurrent access */
  108. spinlock_t rx_lock;
  109. /* queues of incoming and outgoing packets */
  110. struct sk_buff_head rx_queue;
  111. struct sk_buff_head tx_queue;
  112. };
  113. struct dp83640_clock {
  114. /* keeps the instance in the 'phyter_clocks' list */
  115. struct list_head list;
  116. /* we create one clock instance per MII bus */
  117. struct mii_bus *bus;
  118. /* protects extended registers from concurrent access */
  119. struct mutex extreg_lock;
  120. /* remembers which page was last selected */
  121. int page;
  122. /* our advertised capabilities */
  123. struct ptp_clock_info caps;
  124. /* protects the three fields below from concurrent access */
  125. struct mutex clock_lock;
  126. /* the one phyter from which we shall read */
  127. struct dp83640_private *chosen;
  128. /* list of the other attached phyters, not chosen */
  129. struct list_head phylist;
  130. /* reference to our PTP hardware clock */
  131. struct ptp_clock *ptp_clock;
  132. };
  133. /* globals */
  134. enum {
  135. CALIBRATE_GPIO,
  136. PEROUT_GPIO,
  137. EXTTS0_GPIO,
  138. EXTTS1_GPIO,
  139. EXTTS2_GPIO,
  140. EXTTS3_GPIO,
  141. EXTTS4_GPIO,
  142. EXTTS5_GPIO,
  143. GPIO_TABLE_SIZE
  144. };
  145. static int chosen_phy = -1;
  146. static ushort gpio_tab[GPIO_TABLE_SIZE] = {
  147. 1, 2, 3, 4, 8, 9, 10, 11
  148. };
  149. module_param(chosen_phy, int, 0444);
  150. module_param_array(gpio_tab, ushort, NULL, 0444);
  151. MODULE_PARM_DESC(chosen_phy,
  152. "The address of the PHY to use for the ancillary clock features");
  153. MODULE_PARM_DESC(gpio_tab,
  154. "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
  155. static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
  156. {
  157. int i, index;
  158. for (i = 0; i < DP83640_N_PINS; i++) {
  159. snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
  160. pd[i].index = i;
  161. }
  162. for (i = 0; i < GPIO_TABLE_SIZE; i++) {
  163. if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
  164. pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
  165. return;
  166. }
  167. }
  168. index = gpio_tab[CALIBRATE_GPIO] - 1;
  169. pd[index].func = PTP_PF_PHYSYNC;
  170. pd[index].chan = 0;
  171. index = gpio_tab[PEROUT_GPIO] - 1;
  172. pd[index].func = PTP_PF_PEROUT;
  173. pd[index].chan = 0;
  174. for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
  175. index = gpio_tab[i] - 1;
  176. pd[index].func = PTP_PF_EXTTS;
  177. pd[index].chan = i - EXTTS0_GPIO;
  178. }
  179. }
  180. /* a list of clocks and a mutex to protect it */
  181. static LIST_HEAD(phyter_clocks);
  182. static DEFINE_MUTEX(phyter_clocks_lock);
  183. static void rx_timestamp_work(struct work_struct *work);
  184. /* extended register access functions */
  185. #define BROADCAST_ADDR 31
  186. static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
  187. u16 val)
  188. {
  189. return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
  190. }
  191. /* Caller must hold extreg_lock. */
  192. static int ext_read(struct phy_device *phydev, int page, u32 regnum)
  193. {
  194. struct dp83640_private *dp83640 = phydev->priv;
  195. int val;
  196. if (dp83640->clock->page != page) {
  197. broadcast_write(phydev, PAGESEL, page);
  198. dp83640->clock->page = page;
  199. }
  200. val = phy_read(phydev, regnum);
  201. return val;
  202. }
  203. /* Caller must hold extreg_lock. */
  204. static void ext_write(int broadcast, struct phy_device *phydev,
  205. int page, u32 regnum, u16 val)
  206. {
  207. struct dp83640_private *dp83640 = phydev->priv;
  208. if (dp83640->clock->page != page) {
  209. broadcast_write(phydev, PAGESEL, page);
  210. dp83640->clock->page = page;
  211. }
  212. if (broadcast)
  213. broadcast_write(phydev, regnum, val);
  214. else
  215. phy_write(phydev, regnum, val);
  216. }
  217. /* Caller must hold extreg_lock. */
  218. static int tdr_write(int bc, struct phy_device *dev,
  219. const struct timespec64 *ts, u16 cmd)
  220. {
  221. ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
  222. ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
  223. ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
  224. ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
  225. ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
  226. return 0;
  227. }
  228. /* convert phy timestamps into driver timestamps */
  229. static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
  230. {
  231. u32 sec;
  232. sec = p->sec_lo;
  233. sec |= p->sec_hi << 16;
  234. rxts->ns = p->ns_lo;
  235. rxts->ns |= (p->ns_hi & 0x3fff) << 16;
  236. rxts->ns += ((u64)sec) * 1000000000ULL;
  237. rxts->seqid = p->seqid;
  238. rxts->msgtype = (p->msgtype >> 12) & 0xf;
  239. rxts->hash = p->msgtype & 0x0fff;
  240. rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
  241. }
  242. static u64 phy2txts(struct phy_txts *p)
  243. {
  244. u64 ns;
  245. u32 sec;
  246. sec = p->sec_lo;
  247. sec |= p->sec_hi << 16;
  248. ns = p->ns_lo;
  249. ns |= (p->ns_hi & 0x3fff) << 16;
  250. ns += ((u64)sec) * 1000000000ULL;
  251. return ns;
  252. }
  253. static int periodic_output(struct dp83640_clock *clock,
  254. struct ptp_clock_request *clkreq, bool on,
  255. int trigger)
  256. {
  257. struct dp83640_private *dp83640 = clock->chosen;
  258. struct phy_device *phydev = dp83640->phydev;
  259. u32 sec, nsec, pwidth;
  260. u16 gpio, ptp_trig, val;
  261. if (on) {
  262. gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
  263. trigger);
  264. if (gpio < 1)
  265. return -EINVAL;
  266. } else {
  267. gpio = 0;
  268. }
  269. ptp_trig = TRIG_WR |
  270. (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
  271. (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
  272. TRIG_PER |
  273. TRIG_PULSE;
  274. val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
  275. if (!on) {
  276. val |= TRIG_DIS;
  277. mutex_lock(&clock->extreg_lock);
  278. ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
  279. ext_write(0, phydev, PAGE4, PTP_CTL, val);
  280. mutex_unlock(&clock->extreg_lock);
  281. return 0;
  282. }
  283. sec = clkreq->perout.start.sec;
  284. nsec = clkreq->perout.start.nsec;
  285. pwidth = clkreq->perout.period.sec * 1000000000UL;
  286. pwidth += clkreq->perout.period.nsec;
  287. pwidth /= 2;
  288. mutex_lock(&clock->extreg_lock);
  289. ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
  290. /*load trigger*/
  291. val |= TRIG_LOAD;
  292. ext_write(0, phydev, PAGE4, PTP_CTL, val);
  293. ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
  294. ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
  295. ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
  296. ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
  297. ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
  298. ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
  299. /* Triggers 0 and 1 has programmable pulsewidth2 */
  300. if (trigger < 2) {
  301. ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
  302. ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
  303. }
  304. /*enable trigger*/
  305. val &= ~TRIG_LOAD;
  306. val |= TRIG_EN;
  307. ext_write(0, phydev, PAGE4, PTP_CTL, val);
  308. mutex_unlock(&clock->extreg_lock);
  309. return 0;
  310. }
  311. /* ptp clock methods */
  312. static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
  313. {
  314. struct dp83640_clock *clock =
  315. container_of(ptp, struct dp83640_clock, caps);
  316. struct phy_device *phydev = clock->chosen->phydev;
  317. u64 rate;
  318. int neg_adj = 0;
  319. u16 hi, lo;
  320. if (scaled_ppm < 0) {
  321. neg_adj = 1;
  322. scaled_ppm = -scaled_ppm;
  323. }
  324. rate = scaled_ppm;
  325. rate <<= 13;
  326. rate = div_u64(rate, 15625);
  327. hi = (rate >> 16) & PTP_RATE_HI_MASK;
  328. if (neg_adj)
  329. hi |= PTP_RATE_DIR;
  330. lo = rate & 0xffff;
  331. mutex_lock(&clock->extreg_lock);
  332. ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
  333. ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
  334. mutex_unlock(&clock->extreg_lock);
  335. return 0;
  336. }
  337. static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
  338. {
  339. struct dp83640_clock *clock =
  340. container_of(ptp, struct dp83640_clock, caps);
  341. struct phy_device *phydev = clock->chosen->phydev;
  342. struct timespec64 ts;
  343. int err;
  344. delta += ADJTIME_FIX;
  345. ts = ns_to_timespec64(delta);
  346. mutex_lock(&clock->extreg_lock);
  347. err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
  348. mutex_unlock(&clock->extreg_lock);
  349. return err;
  350. }
  351. static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
  352. struct timespec64 *ts)
  353. {
  354. struct dp83640_clock *clock =
  355. container_of(ptp, struct dp83640_clock, caps);
  356. struct phy_device *phydev = clock->chosen->phydev;
  357. unsigned int val[4];
  358. mutex_lock(&clock->extreg_lock);
  359. ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
  360. val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
  361. val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
  362. val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
  363. val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
  364. mutex_unlock(&clock->extreg_lock);
  365. ts->tv_nsec = val[0] | (val[1] << 16);
  366. ts->tv_sec = val[2] | (val[3] << 16);
  367. return 0;
  368. }
  369. static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
  370. const struct timespec64 *ts)
  371. {
  372. struct dp83640_clock *clock =
  373. container_of(ptp, struct dp83640_clock, caps);
  374. struct phy_device *phydev = clock->chosen->phydev;
  375. int err;
  376. mutex_lock(&clock->extreg_lock);
  377. err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
  378. mutex_unlock(&clock->extreg_lock);
  379. return err;
  380. }
  381. static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
  382. struct ptp_clock_request *rq, int on)
  383. {
  384. struct dp83640_clock *clock =
  385. container_of(ptp, struct dp83640_clock, caps);
  386. struct phy_device *phydev = clock->chosen->phydev;
  387. unsigned int index;
  388. u16 evnt, event_num, gpio_num;
  389. switch (rq->type) {
  390. case PTP_CLK_REQ_EXTTS:
  391. /* Reject requests with unsupported flags */
  392. if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
  393. PTP_RISING_EDGE |
  394. PTP_FALLING_EDGE |
  395. PTP_STRICT_FLAGS))
  396. return -EOPNOTSUPP;
  397. /* Reject requests to enable time stamping on both edges. */
  398. if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
  399. (rq->extts.flags & PTP_ENABLE_FEATURE) &&
  400. (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
  401. return -EOPNOTSUPP;
  402. index = rq->extts.index;
  403. if (index >= N_EXT_TS)
  404. return -EINVAL;
  405. event_num = EXT_EVENT + index;
  406. evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
  407. if (on) {
  408. gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
  409. PTP_PF_EXTTS, index);
  410. if (gpio_num < 1)
  411. return -EINVAL;
  412. evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
  413. if (rq->extts.flags & PTP_FALLING_EDGE)
  414. evnt |= EVNT_FALL;
  415. else
  416. evnt |= EVNT_RISE;
  417. }
  418. mutex_lock(&clock->extreg_lock);
  419. ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
  420. mutex_unlock(&clock->extreg_lock);
  421. return 0;
  422. case PTP_CLK_REQ_PEROUT:
  423. /* Reject requests with unsupported flags */
  424. if (rq->perout.flags)
  425. return -EOPNOTSUPP;
  426. if (rq->perout.index >= N_PER_OUT)
  427. return -EINVAL;
  428. return periodic_output(clock, rq, on, rq->perout.index);
  429. default:
  430. break;
  431. }
  432. return -EOPNOTSUPP;
  433. }
  434. static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
  435. enum ptp_pin_function func, unsigned int chan)
  436. {
  437. struct dp83640_clock *clock =
  438. container_of(ptp, struct dp83640_clock, caps);
  439. if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
  440. !list_empty(&clock->phylist))
  441. return 1;
  442. if (func == PTP_PF_PHYSYNC)
  443. return 1;
  444. return 0;
  445. }
  446. static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
  447. static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
  448. static void enable_status_frames(struct phy_device *phydev, bool on)
  449. {
  450. struct dp83640_private *dp83640 = phydev->priv;
  451. struct dp83640_clock *clock = dp83640->clock;
  452. u16 cfg0 = 0, ver;
  453. if (on)
  454. cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
  455. ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
  456. mutex_lock(&clock->extreg_lock);
  457. ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
  458. ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
  459. mutex_unlock(&clock->extreg_lock);
  460. if (!phydev->attached_dev) {
  461. phydev_warn(phydev,
  462. "expected to find an attached netdevice\n");
  463. return;
  464. }
  465. if (on) {
  466. if (dev_mc_add(phydev->attached_dev, status_frame_dst))
  467. phydev_warn(phydev, "failed to add mc address\n");
  468. } else {
  469. if (dev_mc_del(phydev->attached_dev, status_frame_dst))
  470. phydev_warn(phydev, "failed to delete mc address\n");
  471. }
  472. }
  473. static bool is_status_frame(struct sk_buff *skb, int type)
  474. {
  475. struct ethhdr *h = eth_hdr(skb);
  476. if (PTP_CLASS_V2_L2 == type &&
  477. !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
  478. return true;
  479. else
  480. return false;
  481. }
  482. static int expired(struct rxts *rxts)
  483. {
  484. return time_after(jiffies, rxts->tmo);
  485. }
  486. /* Caller must hold rx_lock. */
  487. static void prune_rx_ts(struct dp83640_private *dp83640)
  488. {
  489. struct list_head *this, *next;
  490. struct rxts *rxts;
  491. list_for_each_safe(this, next, &dp83640->rxts) {
  492. rxts = list_entry(this, struct rxts, list);
  493. if (expired(rxts)) {
  494. list_del_init(&rxts->list);
  495. list_add(&rxts->list, &dp83640->rxpool);
  496. }
  497. }
  498. }
  499. /* synchronize the phyters so they act as one clock */
  500. static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
  501. {
  502. int val;
  503. phy_write(phydev, PAGESEL, 0);
  504. val = phy_read(phydev, PHYCR2);
  505. if (on)
  506. val |= BC_WRITE;
  507. else
  508. val &= ~BC_WRITE;
  509. phy_write(phydev, PHYCR2, val);
  510. phy_write(phydev, PAGESEL, init_page);
  511. }
  512. static void recalibrate(struct dp83640_clock *clock)
  513. {
  514. s64 now, diff;
  515. struct phy_txts event_ts;
  516. struct timespec64 ts;
  517. struct list_head *this;
  518. struct dp83640_private *tmp;
  519. struct phy_device *master = clock->chosen->phydev;
  520. u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
  521. trigger = CAL_TRIGGER;
  522. cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
  523. if (cal_gpio < 1) {
  524. pr_err("PHY calibration pin not available - PHY is not calibrated.");
  525. return;
  526. }
  527. mutex_lock(&clock->extreg_lock);
  528. /*
  529. * enable broadcast, disable status frames, enable ptp clock
  530. */
  531. list_for_each(this, &clock->phylist) {
  532. tmp = list_entry(this, struct dp83640_private, list);
  533. enable_broadcast(tmp->phydev, clock->page, 1);
  534. tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
  535. ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
  536. ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
  537. }
  538. enable_broadcast(master, clock->page, 1);
  539. cfg0 = ext_read(master, PAGE5, PSF_CFG0);
  540. ext_write(0, master, PAGE5, PSF_CFG0, 0);
  541. ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
  542. /*
  543. * enable an event timestamp
  544. */
  545. evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
  546. evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
  547. evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
  548. list_for_each(this, &clock->phylist) {
  549. tmp = list_entry(this, struct dp83640_private, list);
  550. ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
  551. }
  552. ext_write(0, master, PAGE5, PTP_EVNT, evnt);
  553. /*
  554. * configure a trigger
  555. */
  556. ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
  557. ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
  558. ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
  559. ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
  560. /* load trigger */
  561. val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
  562. val |= TRIG_LOAD;
  563. ext_write(0, master, PAGE4, PTP_CTL, val);
  564. /* enable trigger */
  565. val &= ~TRIG_LOAD;
  566. val |= TRIG_EN;
  567. ext_write(0, master, PAGE4, PTP_CTL, val);
  568. /* disable trigger */
  569. val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
  570. val |= TRIG_DIS;
  571. ext_write(0, master, PAGE4, PTP_CTL, val);
  572. /*
  573. * read out and correct offsets
  574. */
  575. val = ext_read(master, PAGE4, PTP_STS);
  576. phydev_info(master, "master PTP_STS 0x%04hx\n", val);
  577. val = ext_read(master, PAGE4, PTP_ESTS);
  578. phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
  579. event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
  580. event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
  581. event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
  582. event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
  583. now = phy2txts(&event_ts);
  584. list_for_each(this, &clock->phylist) {
  585. tmp = list_entry(this, struct dp83640_private, list);
  586. val = ext_read(tmp->phydev, PAGE4, PTP_STS);
  587. phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
  588. val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
  589. phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
  590. event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
  591. event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
  592. event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
  593. event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
  594. diff = now - (s64) phy2txts(&event_ts);
  595. phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
  596. diff);
  597. diff += ADJTIME_FIX;
  598. ts = ns_to_timespec64(diff);
  599. tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
  600. }
  601. /*
  602. * restore status frames
  603. */
  604. list_for_each(this, &clock->phylist) {
  605. tmp = list_entry(this, struct dp83640_private, list);
  606. ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
  607. }
  608. ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
  609. mutex_unlock(&clock->extreg_lock);
  610. }
  611. /* time stamping methods */
  612. static inline u16 exts_chan_to_edata(int ch)
  613. {
  614. return 1 << ((ch + EXT_EVENT) * 2);
  615. }
  616. static int decode_evnt(struct dp83640_private *dp83640,
  617. void *data, int len, u16 ests)
  618. {
  619. struct phy_txts *phy_txts;
  620. struct ptp_clock_event event;
  621. int i, parsed;
  622. int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
  623. u16 ext_status = 0;
  624. /* calculate length of the event timestamp status message */
  625. if (ests & MULT_EVNT)
  626. parsed = (words + 2) * sizeof(u16);
  627. else
  628. parsed = (words + 1) * sizeof(u16);
  629. /* check if enough data is available */
  630. if (len < parsed)
  631. return len;
  632. if (ests & MULT_EVNT) {
  633. ext_status = *(u16 *) data;
  634. data += sizeof(ext_status);
  635. }
  636. phy_txts = data;
  637. switch (words) {
  638. case 3:
  639. dp83640->edata.sec_hi = phy_txts->sec_hi;
  640. fallthrough;
  641. case 2:
  642. dp83640->edata.sec_lo = phy_txts->sec_lo;
  643. fallthrough;
  644. case 1:
  645. dp83640->edata.ns_hi = phy_txts->ns_hi;
  646. fallthrough;
  647. case 0:
  648. dp83640->edata.ns_lo = phy_txts->ns_lo;
  649. }
  650. if (!ext_status) {
  651. i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
  652. ext_status = exts_chan_to_edata(i);
  653. }
  654. event.type = PTP_CLOCK_EXTTS;
  655. event.timestamp = phy2txts(&dp83640->edata);
  656. /* Compensate for input path and synchronization delays */
  657. event.timestamp -= 35;
  658. for (i = 0; i < N_EXT_TS; i++) {
  659. if (ext_status & exts_chan_to_edata(i)) {
  660. event.index = i;
  661. ptp_clock_event(dp83640->clock->ptp_clock, &event);
  662. }
  663. }
  664. return parsed;
  665. }
  666. #define DP83640_PACKET_HASH_LEN 10
  667. static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
  668. {
  669. struct ptp_header *hdr;
  670. u8 msgtype;
  671. u16 seqid;
  672. u16 hash;
  673. /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
  674. hdr = ptp_parse_header(skb, type);
  675. if (!hdr)
  676. return 0;
  677. msgtype = ptp_get_msgtype(hdr, type);
  678. if (rxts->msgtype != (msgtype & 0xf))
  679. return 0;
  680. seqid = be16_to_cpu(hdr->sequence_id);
  681. if (rxts->seqid != seqid)
  682. return 0;
  683. hash = ether_crc(DP83640_PACKET_HASH_LEN,
  684. (unsigned char *)&hdr->source_port_identity) >> 20;
  685. if (rxts->hash != hash)
  686. return 0;
  687. return 1;
  688. }
  689. static void decode_rxts(struct dp83640_private *dp83640,
  690. struct phy_rxts *phy_rxts)
  691. {
  692. struct rxts *rxts;
  693. struct skb_shared_hwtstamps *shhwtstamps = NULL;
  694. struct sk_buff *skb;
  695. unsigned long flags;
  696. u8 overflow;
  697. overflow = (phy_rxts->ns_hi >> 14) & 0x3;
  698. if (overflow)
  699. pr_debug("rx timestamp queue overflow, count %d\n", overflow);
  700. spin_lock_irqsave(&dp83640->rx_lock, flags);
  701. prune_rx_ts(dp83640);
  702. if (list_empty(&dp83640->rxpool)) {
  703. pr_debug("rx timestamp pool is empty\n");
  704. goto out;
  705. }
  706. rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
  707. list_del_init(&rxts->list);
  708. phy2rxts(phy_rxts, rxts);
  709. spin_lock(&dp83640->rx_queue.lock);
  710. skb_queue_walk(&dp83640->rx_queue, skb) {
  711. struct dp83640_skb_info *skb_info;
  712. skb_info = (struct dp83640_skb_info *)skb->cb;
  713. if (match(skb, skb_info->ptp_type, rxts)) {
  714. __skb_unlink(skb, &dp83640->rx_queue);
  715. shhwtstamps = skb_hwtstamps(skb);
  716. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  717. shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
  718. list_add(&rxts->list, &dp83640->rxpool);
  719. break;
  720. }
  721. }
  722. spin_unlock(&dp83640->rx_queue.lock);
  723. if (!shhwtstamps)
  724. list_add_tail(&rxts->list, &dp83640->rxts);
  725. out:
  726. spin_unlock_irqrestore(&dp83640->rx_lock, flags);
  727. if (shhwtstamps)
  728. netif_rx(skb);
  729. }
  730. static void decode_txts(struct dp83640_private *dp83640,
  731. struct phy_txts *phy_txts)
  732. {
  733. struct skb_shared_hwtstamps shhwtstamps;
  734. struct dp83640_skb_info *skb_info;
  735. struct sk_buff *skb;
  736. u8 overflow;
  737. u64 ns;
  738. /* We must already have the skb that triggered this. */
  739. again:
  740. skb = skb_dequeue(&dp83640->tx_queue);
  741. if (!skb) {
  742. pr_debug("have timestamp but tx_queue empty\n");
  743. return;
  744. }
  745. overflow = (phy_txts->ns_hi >> 14) & 0x3;
  746. if (overflow) {
  747. pr_debug("tx timestamp queue overflow, count %d\n", overflow);
  748. while (skb) {
  749. kfree_skb(skb);
  750. skb = skb_dequeue(&dp83640->tx_queue);
  751. }
  752. return;
  753. }
  754. skb_info = (struct dp83640_skb_info *)skb->cb;
  755. if (time_after(jiffies, skb_info->tmo)) {
  756. kfree_skb(skb);
  757. goto again;
  758. }
  759. ns = phy2txts(phy_txts);
  760. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  761. shhwtstamps.hwtstamp = ns_to_ktime(ns);
  762. skb_complete_tx_timestamp(skb, &shhwtstamps);
  763. }
  764. static void decode_status_frame(struct dp83640_private *dp83640,
  765. struct sk_buff *skb)
  766. {
  767. struct phy_rxts *phy_rxts;
  768. struct phy_txts *phy_txts;
  769. u8 *ptr;
  770. int len, size;
  771. u16 ests, type;
  772. ptr = skb->data + 2;
  773. for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
  774. type = *(u16 *)ptr;
  775. ests = type & 0x0fff;
  776. type = type & 0xf000;
  777. len -= sizeof(type);
  778. ptr += sizeof(type);
  779. if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
  780. phy_rxts = (struct phy_rxts *) ptr;
  781. decode_rxts(dp83640, phy_rxts);
  782. size = sizeof(*phy_rxts);
  783. } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
  784. phy_txts = (struct phy_txts *) ptr;
  785. decode_txts(dp83640, phy_txts);
  786. size = sizeof(*phy_txts);
  787. } else if (PSF_EVNT == type) {
  788. size = decode_evnt(dp83640, ptr, len, ests);
  789. } else {
  790. size = 0;
  791. break;
  792. }
  793. ptr += size;
  794. }
  795. }
  796. static void dp83640_free_clocks(void)
  797. {
  798. struct dp83640_clock *clock;
  799. struct list_head *this, *next;
  800. mutex_lock(&phyter_clocks_lock);
  801. list_for_each_safe(this, next, &phyter_clocks) {
  802. clock = list_entry(this, struct dp83640_clock, list);
  803. if (!list_empty(&clock->phylist)) {
  804. pr_warn("phy list non-empty while unloading\n");
  805. BUG();
  806. }
  807. list_del(&clock->list);
  808. mutex_destroy(&clock->extreg_lock);
  809. mutex_destroy(&clock->clock_lock);
  810. put_device(&clock->bus->dev);
  811. kfree(clock->caps.pin_config);
  812. kfree(clock);
  813. }
  814. mutex_unlock(&phyter_clocks_lock);
  815. }
  816. static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
  817. {
  818. INIT_LIST_HEAD(&clock->list);
  819. clock->bus = bus;
  820. mutex_init(&clock->extreg_lock);
  821. mutex_init(&clock->clock_lock);
  822. INIT_LIST_HEAD(&clock->phylist);
  823. clock->caps.owner = THIS_MODULE;
  824. sprintf(clock->caps.name, "dp83640 timer");
  825. clock->caps.max_adj = 1953124;
  826. clock->caps.n_alarm = 0;
  827. clock->caps.n_ext_ts = N_EXT_TS;
  828. clock->caps.n_per_out = N_PER_OUT;
  829. clock->caps.n_pins = DP83640_N_PINS;
  830. clock->caps.pps = 0;
  831. clock->caps.adjfine = ptp_dp83640_adjfine;
  832. clock->caps.adjtime = ptp_dp83640_adjtime;
  833. clock->caps.gettime64 = ptp_dp83640_gettime;
  834. clock->caps.settime64 = ptp_dp83640_settime;
  835. clock->caps.enable = ptp_dp83640_enable;
  836. clock->caps.verify = ptp_dp83640_verify;
  837. /*
  838. * Convert the module param defaults into a dynamic pin configuration.
  839. */
  840. dp83640_gpio_defaults(clock->caps.pin_config);
  841. /*
  842. * Get a reference to this bus instance.
  843. */
  844. get_device(&bus->dev);
  845. }
  846. static int choose_this_phy(struct dp83640_clock *clock,
  847. struct phy_device *phydev)
  848. {
  849. if (chosen_phy == -1 && !clock->chosen)
  850. return 1;
  851. if (chosen_phy == phydev->mdio.addr)
  852. return 1;
  853. return 0;
  854. }
  855. static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
  856. {
  857. if (clock)
  858. mutex_lock(&clock->clock_lock);
  859. return clock;
  860. }
  861. /*
  862. * Look up and lock a clock by bus instance.
  863. * If there is no clock for this bus, then create it first.
  864. */
  865. static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
  866. {
  867. struct dp83640_clock *clock = NULL, *tmp;
  868. struct list_head *this;
  869. mutex_lock(&phyter_clocks_lock);
  870. list_for_each(this, &phyter_clocks) {
  871. tmp = list_entry(this, struct dp83640_clock, list);
  872. if (tmp->bus == bus) {
  873. clock = tmp;
  874. break;
  875. }
  876. }
  877. if (clock)
  878. goto out;
  879. clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
  880. if (!clock)
  881. goto out;
  882. clock->caps.pin_config = kcalloc(DP83640_N_PINS,
  883. sizeof(struct ptp_pin_desc),
  884. GFP_KERNEL);
  885. if (!clock->caps.pin_config) {
  886. kfree(clock);
  887. clock = NULL;
  888. goto out;
  889. }
  890. dp83640_clock_init(clock, bus);
  891. list_add_tail(&clock->list, &phyter_clocks);
  892. out:
  893. mutex_unlock(&phyter_clocks_lock);
  894. return dp83640_clock_get(clock);
  895. }
  896. static void dp83640_clock_put(struct dp83640_clock *clock)
  897. {
  898. mutex_unlock(&clock->clock_lock);
  899. }
  900. static int dp83640_soft_reset(struct phy_device *phydev)
  901. {
  902. int ret;
  903. ret = genphy_soft_reset(phydev);
  904. if (ret < 0)
  905. return ret;
  906. /* From DP83640 datasheet: "Software driver code must wait 3 us
  907. * following a software reset before allowing further serial MII
  908. * operations with the DP83640."
  909. */
  910. udelay(10); /* Taking udelay inaccuracy into account */
  911. return 0;
  912. }
  913. static int dp83640_config_init(struct phy_device *phydev)
  914. {
  915. struct dp83640_private *dp83640 = phydev->priv;
  916. struct dp83640_clock *clock = dp83640->clock;
  917. if (clock->chosen && !list_empty(&clock->phylist))
  918. recalibrate(clock);
  919. else {
  920. mutex_lock(&clock->extreg_lock);
  921. enable_broadcast(phydev, clock->page, 1);
  922. mutex_unlock(&clock->extreg_lock);
  923. }
  924. enable_status_frames(phydev, true);
  925. mutex_lock(&clock->extreg_lock);
  926. ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
  927. mutex_unlock(&clock->extreg_lock);
  928. return 0;
  929. }
  930. static int dp83640_ack_interrupt(struct phy_device *phydev)
  931. {
  932. int err = phy_read(phydev, MII_DP83640_MISR);
  933. if (err < 0)
  934. return err;
  935. return 0;
  936. }
  937. static int dp83640_config_intr(struct phy_device *phydev)
  938. {
  939. int micr;
  940. int misr;
  941. int err;
  942. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  943. err = dp83640_ack_interrupt(phydev);
  944. if (err)
  945. return err;
  946. misr = phy_read(phydev, MII_DP83640_MISR);
  947. if (misr < 0)
  948. return misr;
  949. misr |=
  950. (MII_DP83640_MISR_ANC_INT_EN |
  951. MII_DP83640_MISR_DUP_INT_EN |
  952. MII_DP83640_MISR_SPD_INT_EN |
  953. MII_DP83640_MISR_LINK_INT_EN);
  954. err = phy_write(phydev, MII_DP83640_MISR, misr);
  955. if (err < 0)
  956. return err;
  957. micr = phy_read(phydev, MII_DP83640_MICR);
  958. if (micr < 0)
  959. return micr;
  960. micr |=
  961. (MII_DP83640_MICR_OE |
  962. MII_DP83640_MICR_IE);
  963. return phy_write(phydev, MII_DP83640_MICR, micr);
  964. } else {
  965. micr = phy_read(phydev, MII_DP83640_MICR);
  966. if (micr < 0)
  967. return micr;
  968. micr &=
  969. ~(MII_DP83640_MICR_OE |
  970. MII_DP83640_MICR_IE);
  971. err = phy_write(phydev, MII_DP83640_MICR, micr);
  972. if (err < 0)
  973. return err;
  974. misr = phy_read(phydev, MII_DP83640_MISR);
  975. if (misr < 0)
  976. return misr;
  977. misr &=
  978. ~(MII_DP83640_MISR_ANC_INT_EN |
  979. MII_DP83640_MISR_DUP_INT_EN |
  980. MII_DP83640_MISR_SPD_INT_EN |
  981. MII_DP83640_MISR_LINK_INT_EN);
  982. err = phy_write(phydev, MII_DP83640_MISR, misr);
  983. if (err)
  984. return err;
  985. return dp83640_ack_interrupt(phydev);
  986. }
  987. }
  988. static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev)
  989. {
  990. int irq_status;
  991. irq_status = phy_read(phydev, MII_DP83640_MISR);
  992. if (irq_status < 0) {
  993. phy_error(phydev);
  994. return IRQ_NONE;
  995. }
  996. if (!(irq_status & MII_DP83640_MISR_INT_MASK))
  997. return IRQ_NONE;
  998. phy_trigger_machine(phydev);
  999. return IRQ_HANDLED;
  1000. }
  1001. static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
  1002. {
  1003. struct dp83640_private *dp83640 =
  1004. container_of(mii_ts, struct dp83640_private, mii_ts);
  1005. struct hwtstamp_config cfg;
  1006. u16 txcfg0, rxcfg0;
  1007. if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
  1008. return -EFAULT;
  1009. if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
  1010. return -ERANGE;
  1011. dp83640->hwts_tx_en = cfg.tx_type;
  1012. switch (cfg.rx_filter) {
  1013. case HWTSTAMP_FILTER_NONE:
  1014. dp83640->hwts_rx_en = 0;
  1015. dp83640->layer = 0;
  1016. dp83640->version = 0;
  1017. break;
  1018. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  1019. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  1020. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  1021. dp83640->hwts_rx_en = 1;
  1022. dp83640->layer = PTP_CLASS_L4;
  1023. dp83640->version = PTP_CLASS_V1;
  1024. cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
  1025. break;
  1026. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  1027. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  1028. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  1029. dp83640->hwts_rx_en = 1;
  1030. dp83640->layer = PTP_CLASS_L4;
  1031. dp83640->version = PTP_CLASS_V2;
  1032. cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
  1033. break;
  1034. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  1035. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  1036. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  1037. dp83640->hwts_rx_en = 1;
  1038. dp83640->layer = PTP_CLASS_L2;
  1039. dp83640->version = PTP_CLASS_V2;
  1040. cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
  1041. break;
  1042. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  1043. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  1044. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  1045. dp83640->hwts_rx_en = 1;
  1046. dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
  1047. dp83640->version = PTP_CLASS_V2;
  1048. cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
  1049. break;
  1050. default:
  1051. return -ERANGE;
  1052. }
  1053. txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
  1054. rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
  1055. if (dp83640->layer & PTP_CLASS_L2) {
  1056. txcfg0 |= TX_L2_EN;
  1057. rxcfg0 |= RX_L2_EN;
  1058. }
  1059. if (dp83640->layer & PTP_CLASS_L4) {
  1060. txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
  1061. rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
  1062. }
  1063. if (dp83640->hwts_tx_en)
  1064. txcfg0 |= TX_TS_EN;
  1065. if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
  1066. txcfg0 |= SYNC_1STEP | CHK_1STEP;
  1067. if (dp83640->hwts_rx_en)
  1068. rxcfg0 |= RX_TS_EN;
  1069. mutex_lock(&dp83640->clock->extreg_lock);
  1070. ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
  1071. ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
  1072. mutex_unlock(&dp83640->clock->extreg_lock);
  1073. return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
  1074. }
  1075. static void rx_timestamp_work(struct work_struct *work)
  1076. {
  1077. struct dp83640_private *dp83640 =
  1078. container_of(work, struct dp83640_private, ts_work.work);
  1079. struct sk_buff *skb;
  1080. /* Deliver expired packets. */
  1081. while ((skb = skb_dequeue(&dp83640->rx_queue))) {
  1082. struct dp83640_skb_info *skb_info;
  1083. skb_info = (struct dp83640_skb_info *)skb->cb;
  1084. if (!time_after(jiffies, skb_info->tmo)) {
  1085. skb_queue_head(&dp83640->rx_queue, skb);
  1086. break;
  1087. }
  1088. netif_rx(skb);
  1089. }
  1090. if (!skb_queue_empty(&dp83640->rx_queue))
  1091. schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
  1092. }
  1093. static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts,
  1094. struct sk_buff *skb, int type)
  1095. {
  1096. struct dp83640_private *dp83640 =
  1097. container_of(mii_ts, struct dp83640_private, mii_ts);
  1098. struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
  1099. struct list_head *this, *next;
  1100. struct rxts *rxts;
  1101. struct skb_shared_hwtstamps *shhwtstamps = NULL;
  1102. unsigned long flags;
  1103. if (is_status_frame(skb, type)) {
  1104. decode_status_frame(dp83640, skb);
  1105. kfree_skb(skb);
  1106. return true;
  1107. }
  1108. if (!dp83640->hwts_rx_en)
  1109. return false;
  1110. if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
  1111. return false;
  1112. spin_lock_irqsave(&dp83640->rx_lock, flags);
  1113. prune_rx_ts(dp83640);
  1114. list_for_each_safe(this, next, &dp83640->rxts) {
  1115. rxts = list_entry(this, struct rxts, list);
  1116. if (match(skb, type, rxts)) {
  1117. shhwtstamps = skb_hwtstamps(skb);
  1118. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  1119. shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
  1120. list_del_init(&rxts->list);
  1121. list_add(&rxts->list, &dp83640->rxpool);
  1122. break;
  1123. }
  1124. }
  1125. spin_unlock_irqrestore(&dp83640->rx_lock, flags);
  1126. if (!shhwtstamps) {
  1127. skb_info->ptp_type = type;
  1128. skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
  1129. skb_queue_tail(&dp83640->rx_queue, skb);
  1130. schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
  1131. } else {
  1132. netif_rx(skb);
  1133. }
  1134. return true;
  1135. }
  1136. static void dp83640_txtstamp(struct mii_timestamper *mii_ts,
  1137. struct sk_buff *skb, int type)
  1138. {
  1139. struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
  1140. struct dp83640_private *dp83640 =
  1141. container_of(mii_ts, struct dp83640_private, mii_ts);
  1142. switch (dp83640->hwts_tx_en) {
  1143. case HWTSTAMP_TX_ONESTEP_SYNC:
  1144. if (ptp_msg_is_sync(skb, type)) {
  1145. kfree_skb(skb);
  1146. return;
  1147. }
  1148. fallthrough;
  1149. case HWTSTAMP_TX_ON:
  1150. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1151. skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
  1152. skb_queue_tail(&dp83640->tx_queue, skb);
  1153. break;
  1154. case HWTSTAMP_TX_OFF:
  1155. default:
  1156. kfree_skb(skb);
  1157. break;
  1158. }
  1159. }
  1160. static int dp83640_ts_info(struct mii_timestamper *mii_ts,
  1161. struct ethtool_ts_info *info)
  1162. {
  1163. struct dp83640_private *dp83640 =
  1164. container_of(mii_ts, struct dp83640_private, mii_ts);
  1165. info->so_timestamping =
  1166. SOF_TIMESTAMPING_TX_HARDWARE |
  1167. SOF_TIMESTAMPING_RX_HARDWARE |
  1168. SOF_TIMESTAMPING_RAW_HARDWARE;
  1169. info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
  1170. info->tx_types =
  1171. (1 << HWTSTAMP_TX_OFF) |
  1172. (1 << HWTSTAMP_TX_ON) |
  1173. (1 << HWTSTAMP_TX_ONESTEP_SYNC);
  1174. info->rx_filters =
  1175. (1 << HWTSTAMP_FILTER_NONE) |
  1176. (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
  1177. (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
  1178. (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
  1179. (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
  1180. return 0;
  1181. }
  1182. static int dp83640_probe(struct phy_device *phydev)
  1183. {
  1184. struct dp83640_clock *clock;
  1185. struct dp83640_private *dp83640;
  1186. int err = -ENOMEM, i;
  1187. if (phydev->mdio.addr == BROADCAST_ADDR)
  1188. return 0;
  1189. clock = dp83640_clock_get_bus(phydev->mdio.bus);
  1190. if (!clock)
  1191. goto no_clock;
  1192. dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
  1193. if (!dp83640)
  1194. goto no_memory;
  1195. dp83640->phydev = phydev;
  1196. dp83640->mii_ts.rxtstamp = dp83640_rxtstamp;
  1197. dp83640->mii_ts.txtstamp = dp83640_txtstamp;
  1198. dp83640->mii_ts.hwtstamp = dp83640_hwtstamp;
  1199. dp83640->mii_ts.ts_info = dp83640_ts_info;
  1200. INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
  1201. INIT_LIST_HEAD(&dp83640->rxts);
  1202. INIT_LIST_HEAD(&dp83640->rxpool);
  1203. for (i = 0; i < MAX_RXTS; i++)
  1204. list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
  1205. phydev->mii_ts = &dp83640->mii_ts;
  1206. phydev->priv = dp83640;
  1207. spin_lock_init(&dp83640->rx_lock);
  1208. skb_queue_head_init(&dp83640->rx_queue);
  1209. skb_queue_head_init(&dp83640->tx_queue);
  1210. dp83640->clock = clock;
  1211. if (choose_this_phy(clock, phydev)) {
  1212. clock->chosen = dp83640;
  1213. clock->ptp_clock = ptp_clock_register(&clock->caps,
  1214. &phydev->mdio.dev);
  1215. if (IS_ERR(clock->ptp_clock)) {
  1216. err = PTR_ERR(clock->ptp_clock);
  1217. goto no_register;
  1218. }
  1219. } else
  1220. list_add_tail(&dp83640->list, &clock->phylist);
  1221. dp83640_clock_put(clock);
  1222. return 0;
  1223. no_register:
  1224. clock->chosen = NULL;
  1225. kfree(dp83640);
  1226. no_memory:
  1227. dp83640_clock_put(clock);
  1228. no_clock:
  1229. return err;
  1230. }
  1231. static void dp83640_remove(struct phy_device *phydev)
  1232. {
  1233. struct dp83640_clock *clock;
  1234. struct list_head *this, *next;
  1235. struct dp83640_private *tmp, *dp83640 = phydev->priv;
  1236. if (phydev->mdio.addr == BROADCAST_ADDR)
  1237. return;
  1238. phydev->mii_ts = NULL;
  1239. enable_status_frames(phydev, false);
  1240. cancel_delayed_work_sync(&dp83640->ts_work);
  1241. skb_queue_purge(&dp83640->rx_queue);
  1242. skb_queue_purge(&dp83640->tx_queue);
  1243. clock = dp83640_clock_get(dp83640->clock);
  1244. if (dp83640 == clock->chosen) {
  1245. ptp_clock_unregister(clock->ptp_clock);
  1246. clock->chosen = NULL;
  1247. } else {
  1248. list_for_each_safe(this, next, &clock->phylist) {
  1249. tmp = list_entry(this, struct dp83640_private, list);
  1250. if (tmp == dp83640) {
  1251. list_del_init(&tmp->list);
  1252. break;
  1253. }
  1254. }
  1255. }
  1256. dp83640_clock_put(clock);
  1257. kfree(dp83640);
  1258. }
  1259. static struct phy_driver dp83640_driver = {
  1260. .phy_id = DP83640_PHY_ID,
  1261. .phy_id_mask = 0xfffffff0,
  1262. .name = "NatSemi DP83640",
  1263. /* PHY_BASIC_FEATURES */
  1264. .probe = dp83640_probe,
  1265. .remove = dp83640_remove,
  1266. .soft_reset = dp83640_soft_reset,
  1267. .config_init = dp83640_config_init,
  1268. .config_intr = dp83640_config_intr,
  1269. .handle_interrupt = dp83640_handle_interrupt,
  1270. };
  1271. static int __init dp83640_init(void)
  1272. {
  1273. return phy_driver_register(&dp83640_driver, THIS_MODULE);
  1274. }
  1275. static void __exit dp83640_exit(void)
  1276. {
  1277. dp83640_free_clocks();
  1278. phy_driver_unregister(&dp83640_driver);
  1279. }
  1280. MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
  1281. MODULE_AUTHOR("Richard Cochran <[email protected]>");
  1282. MODULE_LICENSE("GPL");
  1283. module_init(dp83640_init);
  1284. module_exit(dp83640_exit);
  1285. static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
  1286. { DP83640_PHY_ID, 0xfffffff0 },
  1287. { }
  1288. };
  1289. MODULE_DEVICE_TABLE(mdio, dp83640_tbl);