ax88796b.c 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Driver for Asix PHYs
  3. *
  4. * Author: Michael Schmitz <[email protected]>
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/errno.h>
  8. #include <linux/init.h>
  9. #include <linux/module.h>
  10. #include <linux/mii.h>
  11. #include <linux/phy.h>
  12. #define PHY_ID_ASIX_AX88772A 0x003b1861
  13. #define PHY_ID_ASIX_AX88772C 0x003b1881
  14. #define PHY_ID_ASIX_AX88796B 0x003b1841
  15. MODULE_DESCRIPTION("Asix PHY driver");
  16. MODULE_AUTHOR("Michael Schmitz <[email protected]>");
  17. MODULE_LICENSE("GPL");
  18. /**
  19. * asix_soft_reset - software reset the PHY via BMCR_RESET bit
  20. * @phydev: target phy_device struct
  21. *
  22. * Description: Perform a software PHY reset using the standard
  23. * BMCR_RESET bit and poll for the reset bit to be cleared.
  24. * Toggle BMCR_RESET bit off to accommodate broken AX8796B PHY implementation
  25. * such as used on the Individual Computers' X-Surf 100 Zorro card.
  26. *
  27. * Returns: 0 on success, < 0 on failure
  28. */
  29. static int asix_soft_reset(struct phy_device *phydev)
  30. {
  31. int ret;
  32. /* Asix PHY won't reset unless reset bit toggles */
  33. ret = phy_write(phydev, MII_BMCR, 0);
  34. if (ret < 0)
  35. return ret;
  36. return genphy_soft_reset(phydev);
  37. }
  38. /* AX88772A is not working properly with some old switches (NETGEAR EN 108TP):
  39. * after autoneg is done and the link status is reported as active, the MII_LPA
  40. * register is 0. This issue is not reproducible on AX88772C.
  41. */
  42. static int asix_ax88772a_read_status(struct phy_device *phydev)
  43. {
  44. int ret, val;
  45. ret = genphy_update_link(phydev);
  46. if (ret)
  47. return ret;
  48. if (!phydev->link)
  49. return 0;
  50. /* If MII_LPA is 0, phy_resolve_aneg_linkmode() will fail to resolve
  51. * linkmode so use MII_BMCR as default values.
  52. */
  53. val = phy_read(phydev, MII_BMCR);
  54. if (val < 0)
  55. return val;
  56. if (val & BMCR_SPEED100)
  57. phydev->speed = SPEED_100;
  58. else
  59. phydev->speed = SPEED_10;
  60. if (val & BMCR_FULLDPLX)
  61. phydev->duplex = DUPLEX_FULL;
  62. else
  63. phydev->duplex = DUPLEX_HALF;
  64. ret = genphy_read_lpa(phydev);
  65. if (ret < 0)
  66. return ret;
  67. if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
  68. phy_resolve_aneg_linkmode(phydev);
  69. return 0;
  70. }
  71. static void asix_ax88772a_link_change_notify(struct phy_device *phydev)
  72. {
  73. /* Reset PHY, otherwise MII_LPA will provide outdated information.
  74. * This issue is reproducible only with some link partner PHYs
  75. */
  76. if (phydev->state == PHY_NOLINK) {
  77. phy_init_hw(phydev);
  78. phy_start_aneg(phydev);
  79. }
  80. }
  81. static struct phy_driver asix_driver[] = {
  82. {
  83. PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772A),
  84. .name = "Asix Electronics AX88772A",
  85. .flags = PHY_IS_INTERNAL,
  86. .read_status = asix_ax88772a_read_status,
  87. .suspend = genphy_suspend,
  88. .resume = genphy_resume,
  89. .soft_reset = asix_soft_reset,
  90. .link_change_notify = asix_ax88772a_link_change_notify,
  91. }, {
  92. PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772C),
  93. .name = "Asix Electronics AX88772C",
  94. .flags = PHY_IS_INTERNAL,
  95. .suspend = genphy_suspend,
  96. .resume = genphy_resume,
  97. .soft_reset = asix_soft_reset,
  98. }, {
  99. .phy_id = PHY_ID_ASIX_AX88796B,
  100. .name = "Asix Electronics AX88796B",
  101. .phy_id_mask = 0xfffffff0,
  102. /* PHY_BASIC_FEATURES */
  103. .soft_reset = asix_soft_reset,
  104. } };
  105. module_phy_driver(asix_driver);
  106. static struct mdio_device_id __maybe_unused asix_tbl[] = {
  107. { PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772A) },
  108. { PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772C) },
  109. { PHY_ID_ASIX_AX88796B, 0xfffffff0 },
  110. { }
  111. };
  112. MODULE_DEVICE_TABLE(mdio, asix_tbl);