mdio-ipq8064.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Qualcomm IPQ8064 MDIO interface driver
  3. *
  4. * Copyright (C) 2019 Christian Lamparter <[email protected]>
  5. * Copyright (C) 2020 Ansuel Smith <[email protected]>
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_mdio.h>
  11. #include <linux/of_address.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. /* MII address register definitions */
  15. #define MII_ADDR_REG_ADDR 0x10
  16. #define MII_BUSY BIT(0)
  17. #define MII_WRITE BIT(1)
  18. #define MII_CLKRANGE(x) ((x) << 2)
  19. #define MII_CLKRANGE_60_100M MII_CLKRANGE(0)
  20. #define MII_CLKRANGE_100_150M MII_CLKRANGE(1)
  21. #define MII_CLKRANGE_20_35M MII_CLKRANGE(2)
  22. #define MII_CLKRANGE_35_60M MII_CLKRANGE(3)
  23. #define MII_CLKRANGE_150_250M MII_CLKRANGE(4)
  24. #define MII_CLKRANGE_250_300M MII_CLKRANGE(5)
  25. #define MII_CLKRANGE_MASK GENMASK(4, 2)
  26. #define MII_REG_SHIFT 6
  27. #define MII_REG_MASK GENMASK(10, 6)
  28. #define MII_ADDR_SHIFT 11
  29. #define MII_ADDR_MASK GENMASK(15, 11)
  30. #define MII_DATA_REG_ADDR 0x14
  31. #define MII_MDIO_DELAY_USEC (1000)
  32. #define MII_MDIO_RETRY_MSEC (10)
  33. struct ipq8064_mdio {
  34. struct regmap *base; /* NSS_GMAC0_BASE */
  35. };
  36. static int
  37. ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
  38. {
  39. u32 busy;
  40. return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
  41. !(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
  42. MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
  43. }
  44. static int
  45. ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
  46. {
  47. u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
  48. struct ipq8064_mdio *priv = bus->priv;
  49. u32 ret_val;
  50. int err;
  51. /* Reject clause 45 */
  52. if (reg_offset & MII_ADDR_C45)
  53. return -EOPNOTSUPP;
  54. miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
  55. ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
  56. regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
  57. usleep_range(10, 13);
  58. err = ipq8064_mdio_wait_busy(priv);
  59. if (err)
  60. return err;
  61. regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
  62. return (int)ret_val;
  63. }
  64. static int
  65. ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
  66. {
  67. u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
  68. struct ipq8064_mdio *priv = bus->priv;
  69. /* Reject clause 45 */
  70. if (reg_offset & MII_ADDR_C45)
  71. return -EOPNOTSUPP;
  72. regmap_write(priv->base, MII_DATA_REG_ADDR, data);
  73. miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
  74. ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
  75. regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
  76. /* For the specific reg 31 extra time is needed or the next
  77. * read will produce garbage data.
  78. */
  79. if (reg_offset == 31)
  80. usleep_range(30, 43);
  81. else
  82. usleep_range(10, 13);
  83. return ipq8064_mdio_wait_busy(priv);
  84. }
  85. static const struct regmap_config ipq8064_mdio_regmap_config = {
  86. .reg_bits = 32,
  87. .reg_stride = 4,
  88. .val_bits = 32,
  89. .can_multi_write = false,
  90. /* the mdio lock is used by any user of this mdio driver */
  91. .disable_locking = true,
  92. .cache_type = REGCACHE_NONE,
  93. };
  94. static int
  95. ipq8064_mdio_probe(struct platform_device *pdev)
  96. {
  97. struct device_node *np = pdev->dev.of_node;
  98. struct ipq8064_mdio *priv;
  99. struct resource res;
  100. struct mii_bus *bus;
  101. void __iomem *base;
  102. int ret;
  103. if (of_address_to_resource(np, 0, &res))
  104. return -ENOMEM;
  105. base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
  106. if (!base)
  107. return -ENOMEM;
  108. bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
  109. if (!bus)
  110. return -ENOMEM;
  111. bus->name = "ipq8064_mdio_bus";
  112. bus->read = ipq8064_mdio_read;
  113. bus->write = ipq8064_mdio_write;
  114. snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
  115. bus->parent = &pdev->dev;
  116. priv = bus->priv;
  117. priv->base = devm_regmap_init_mmio(&pdev->dev, base,
  118. &ipq8064_mdio_regmap_config);
  119. if (IS_ERR(priv->base))
  120. return PTR_ERR(priv->base);
  121. ret = of_mdiobus_register(bus, np);
  122. if (ret)
  123. return ret;
  124. platform_set_drvdata(pdev, bus);
  125. return 0;
  126. }
  127. static int
  128. ipq8064_mdio_remove(struct platform_device *pdev)
  129. {
  130. struct mii_bus *bus = platform_get_drvdata(pdev);
  131. mdiobus_unregister(bus);
  132. return 0;
  133. }
  134. static const struct of_device_id ipq8064_mdio_dt_ids[] = {
  135. { .compatible = "qcom,ipq8064-mdio" },
  136. { }
  137. };
  138. MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
  139. static struct platform_driver ipq8064_mdio_driver = {
  140. .probe = ipq8064_mdio_probe,
  141. .remove = ipq8064_mdio_remove,
  142. .driver = {
  143. .name = "ipq8064-mdio",
  144. .of_match_table = ipq8064_mdio_dt_ids,
  145. },
  146. };
  147. module_platform_driver(ipq8064_mdio_driver);
  148. MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
  149. MODULE_AUTHOR("Christian Lamparter <[email protected]>");
  150. MODULE_AUTHOR("Ansuel Smith <[email protected]>");
  151. MODULE_LICENSE("GPL");