mdio-cavium.c 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2009-2016 Cavium, Inc.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/io.h>
  7. #include <linux/module.h>
  8. #include <linux/phy.h>
  9. #include "mdio-cavium.h"
  10. static void cavium_mdiobus_set_mode(struct cavium_mdiobus *p,
  11. enum cavium_mdiobus_mode m)
  12. {
  13. union cvmx_smix_clk smi_clk;
  14. if (m == p->mode)
  15. return;
  16. smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
  17. smi_clk.s.mode = (m == C45) ? 1 : 0;
  18. smi_clk.s.preamble = 1;
  19. oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
  20. p->mode = m;
  21. }
  22. static int cavium_mdiobus_c45_addr(struct cavium_mdiobus *p,
  23. int phy_id, int regnum)
  24. {
  25. union cvmx_smix_cmd smi_cmd;
  26. union cvmx_smix_wr_dat smi_wr;
  27. int timeout = 1000;
  28. cavium_mdiobus_set_mode(p, C45);
  29. smi_wr.u64 = 0;
  30. smi_wr.s.dat = regnum & 0xffff;
  31. oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
  32. regnum = (regnum >> 16) & 0x1f;
  33. smi_cmd.u64 = 0;
  34. smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
  35. smi_cmd.s.phy_adr = phy_id;
  36. smi_cmd.s.reg_adr = regnum;
  37. oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
  38. do {
  39. /* Wait 1000 clocks so we don't saturate the RSL bus
  40. * doing reads.
  41. */
  42. __delay(1000);
  43. smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
  44. } while (smi_wr.s.pending && --timeout);
  45. if (timeout <= 0)
  46. return -EIO;
  47. return 0;
  48. }
  49. int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
  50. {
  51. struct cavium_mdiobus *p = bus->priv;
  52. union cvmx_smix_cmd smi_cmd;
  53. union cvmx_smix_rd_dat smi_rd;
  54. unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
  55. int timeout = 1000;
  56. if (regnum & MII_ADDR_C45) {
  57. int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
  58. if (r < 0)
  59. return r;
  60. regnum = (regnum >> 16) & 0x1f;
  61. op = 3; /* MDIO_CLAUSE_45_READ */
  62. } else {
  63. cavium_mdiobus_set_mode(p, C22);
  64. }
  65. smi_cmd.u64 = 0;
  66. smi_cmd.s.phy_op = op;
  67. smi_cmd.s.phy_adr = phy_id;
  68. smi_cmd.s.reg_adr = regnum;
  69. oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
  70. do {
  71. /* Wait 1000 clocks so we don't saturate the RSL bus
  72. * doing reads.
  73. */
  74. __delay(1000);
  75. smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
  76. } while (smi_rd.s.pending && --timeout);
  77. if (smi_rd.s.val)
  78. return smi_rd.s.dat;
  79. else
  80. return -EIO;
  81. }
  82. EXPORT_SYMBOL(cavium_mdiobus_read);
  83. int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val)
  84. {
  85. struct cavium_mdiobus *p = bus->priv;
  86. union cvmx_smix_cmd smi_cmd;
  87. union cvmx_smix_wr_dat smi_wr;
  88. unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
  89. int timeout = 1000;
  90. if (regnum & MII_ADDR_C45) {
  91. int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
  92. if (r < 0)
  93. return r;
  94. regnum = (regnum >> 16) & 0x1f;
  95. op = 1; /* MDIO_CLAUSE_45_WRITE */
  96. } else {
  97. cavium_mdiobus_set_mode(p, C22);
  98. }
  99. smi_wr.u64 = 0;
  100. smi_wr.s.dat = val;
  101. oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
  102. smi_cmd.u64 = 0;
  103. smi_cmd.s.phy_op = op;
  104. smi_cmd.s.phy_adr = phy_id;
  105. smi_cmd.s.reg_adr = regnum;
  106. oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
  107. do {
  108. /* Wait 1000 clocks so we don't saturate the RSL bus
  109. * doing reads.
  110. */
  111. __delay(1000);
  112. smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
  113. } while (smi_wr.s.pending && --timeout);
  114. if (timeout <= 0)
  115. return -EIO;
  116. return 0;
  117. }
  118. EXPORT_SYMBOL(cavium_mdiobus_write);
  119. MODULE_DESCRIPTION("Common code for OCTEON and Thunder MDIO bus drivers");
  120. MODULE_AUTHOR("David Daney");
  121. MODULE_LICENSE("GPL v2");