hwmtm.c 55 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /******************************************************************************
  3. *
  4. * (C)Copyright 1998,1999 SysKonnect,
  5. * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
  6. *
  7. * See the file "skfddi.c" for further information.
  8. *
  9. * The information in this file is provided "AS IS" without warranty.
  10. *
  11. ******************************************************************************/
  12. #define HWMTM
  13. #ifndef FDDI
  14. #define FDDI
  15. #endif
  16. #include "h/types.h"
  17. #include "h/fddi.h"
  18. #include "h/smc.h"
  19. #include "h/supern_2.h"
  20. #include "h/skfbiinc.h"
  21. /*
  22. -------------------------------------------------------------
  23. DOCUMENTATION
  24. -------------------------------------------------------------
  25. BEGIN_MANUAL_ENTRY(DOCUMENTATION)
  26. T B D
  27. END_MANUAL_ENTRY
  28. */
  29. /*
  30. -------------------------------------------------------------
  31. LOCAL VARIABLES:
  32. -------------------------------------------------------------
  33. */
  34. #ifdef COMMON_MB_POOL
  35. static SMbuf *mb_start;
  36. static SMbuf *mb_free;
  37. static int mb_init = FALSE ;
  38. static int call_count;
  39. #endif
  40. /*
  41. -------------------------------------------------------------
  42. EXTERNE VARIABLES:
  43. -------------------------------------------------------------
  44. */
  45. #ifdef DEBUG
  46. #ifndef DEBUG_BRD
  47. extern struct smt_debug debug ;
  48. #endif
  49. #endif
  50. #ifdef NDIS_OS2
  51. extern u_char offDepth ;
  52. extern u_char force_irq_pending ;
  53. #endif
  54. /*
  55. -------------------------------------------------------------
  56. LOCAL FUNCTIONS:
  57. -------------------------------------------------------------
  58. */
  59. static void queue_llc_rx(struct s_smc *smc, SMbuf *mb);
  60. static void smt_to_llc(struct s_smc *smc, SMbuf *mb);
  61. static void init_txd_ring(struct s_smc *smc);
  62. static void init_rxd_ring(struct s_smc *smc);
  63. static void queue_txd_mb(struct s_smc *smc, SMbuf *mb);
  64. static u_long init_descr_ring(struct s_smc *smc, union s_fp_descr volatile *start,
  65. int count);
  66. static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue);
  67. static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue);
  68. static SMbuf* get_llc_rx(struct s_smc *smc);
  69. static SMbuf* get_txd_mb(struct s_smc *smc);
  70. static void mac_drv_clear_txd(struct s_smc *smc);
  71. /*
  72. -------------------------------------------------------------
  73. EXTERNAL FUNCTIONS:
  74. -------------------------------------------------------------
  75. */
  76. /* The external SMT functions are listed in cmtdef.h */
  77. extern void* mac_drv_get_space(struct s_smc *smc, unsigned int size);
  78. extern void* mac_drv_get_desc_mem(struct s_smc *smc, unsigned int size);
  79. extern void mac_drv_fill_rxd(struct s_smc *smc);
  80. extern void mac_drv_tx_complete(struct s_smc *smc,
  81. volatile struct s_smt_fp_txd *txd);
  82. extern void mac_drv_rx_complete(struct s_smc *smc,
  83. volatile struct s_smt_fp_rxd *rxd,
  84. int frag_count, int len);
  85. extern void mac_drv_requeue_rxd(struct s_smc *smc,
  86. volatile struct s_smt_fp_rxd *rxd,
  87. int frag_count);
  88. extern void mac_drv_clear_rxd(struct s_smc *smc,
  89. volatile struct s_smt_fp_rxd *rxd, int frag_count);
  90. #ifdef USE_OS_CPY
  91. extern void hwm_cpy_rxd2mb(void);
  92. extern void hwm_cpy_txd2mb(void);
  93. #endif
  94. #ifdef ALL_RX_COMPLETE
  95. extern void mac_drv_all_receives_complete(void);
  96. #endif
  97. extern u_long mac_drv_virt2phys(struct s_smc *smc, void *virt);
  98. extern u_long dma_master(struct s_smc *smc, void *virt, int len, int flag);
  99. #ifdef NDIS_OS2
  100. extern void post_proc(void);
  101. #else
  102. extern void dma_complete(struct s_smc *smc, volatile union s_fp_descr *descr,
  103. int flag);
  104. #endif
  105. extern int mac_drv_rx_init(struct s_smc *smc, int len, int fc, char *look_ahead,
  106. int la_len);
  107. /*
  108. -------------------------------------------------------------
  109. PUBLIC FUNCTIONS:
  110. -------------------------------------------------------------
  111. */
  112. void process_receive(struct s_smc *smc);
  113. void fddi_isr(struct s_smc *smc);
  114. void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
  115. void init_driver_fplus(struct s_smc *smc);
  116. void mac_drv_rx_mode(struct s_smc *smc, int mode);
  117. void init_fddi_driver(struct s_smc *smc, u_char *mac_addr);
  118. void mac_drv_clear_tx_queue(struct s_smc *smc);
  119. void mac_drv_clear_rx_queue(struct s_smc *smc);
  120. void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
  121. int frame_status);
  122. void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
  123. int frame_status);
  124. int mac_drv_init(struct s_smc *smc);
  125. int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
  126. int frame_status);
  127. u_int mac_drv_check_space(void);
  128. SMbuf* smt_get_mbuf(struct s_smc *smc);
  129. #ifdef DEBUG
  130. void mac_drv_debug_lev(struct s_smc *smc, int flag, int lev);
  131. #endif
  132. /*
  133. -------------------------------------------------------------
  134. MACROS:
  135. -------------------------------------------------------------
  136. */
  137. #ifndef UNUSED
  138. #ifdef lint
  139. #define UNUSED(x) (x) = (x)
  140. #else
  141. #define UNUSED(x)
  142. #endif
  143. #endif
  144. #ifdef USE_CAN_ADDR
  145. #define MA smc->hw.fddi_canon_addr.a
  146. #define GROUP_ADDR_BIT 0x01
  147. #else
  148. #define MA smc->hw.fddi_home_addr.a
  149. #define GROUP_ADDR_BIT 0x80
  150. #endif
  151. #define RXD_TXD_COUNT (HWM_ASYNC_TXD_COUNT+HWM_SYNC_TXD_COUNT+\
  152. SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT)
  153. #ifdef MB_OUTSIDE_SMC
  154. #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd) +\
  155. MAX_MBUF*sizeof(SMbuf))
  156. #define EXT_VIRT_MEM_2 ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
  157. #else
  158. #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
  159. #endif
  160. /*
  161. * define critical read for 16 Bit drivers
  162. */
  163. #if defined(NDIS_OS2) || defined(ODI2)
  164. #define CR_READ(var) ((var) & 0xffff0000 | ((var) & 0xffff))
  165. #else
  166. #define CR_READ(var) (__le32)(var)
  167. #endif
  168. #define IMASK_SLOW (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
  169. IS_MINTR1 | IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
  170. IS_R1_C | IS_XA_C | IS_XS_C)
  171. /*
  172. -------------------------------------------------------------
  173. INIT- AND SMT FUNCTIONS:
  174. -------------------------------------------------------------
  175. */
  176. /*
  177. * BEGIN_MANUAL_ENTRY(mac_drv_check_space)
  178. * u_int mac_drv_check_space()
  179. *
  180. * function DOWNCALL (drvsr.c)
  181. * This function calculates the needed non virtual
  182. * memory for MBufs, RxD and TxD descriptors etc.
  183. * needed by the driver.
  184. *
  185. * return u_int memory in bytes
  186. *
  187. * END_MANUAL_ENTRY
  188. */
  189. u_int mac_drv_check_space(void)
  190. {
  191. #ifdef MB_OUTSIDE_SMC
  192. #ifdef COMMON_MB_POOL
  193. call_count++ ;
  194. if (call_count == 1) {
  195. return EXT_VIRT_MEM;
  196. }
  197. else {
  198. return EXT_VIRT_MEM_2;
  199. }
  200. #else
  201. return EXT_VIRT_MEM;
  202. #endif
  203. #else
  204. return 0;
  205. #endif
  206. }
  207. /*
  208. * BEGIN_MANUAL_ENTRY(mac_drv_init)
  209. * void mac_drv_init(smc)
  210. *
  211. * function DOWNCALL (drvsr.c)
  212. * In this function the hardware module allocates it's
  213. * memory.
  214. * The operating system dependent module should call
  215. * mac_drv_init once, after the adatper is detected.
  216. * END_MANUAL_ENTRY
  217. */
  218. int mac_drv_init(struct s_smc *smc)
  219. {
  220. if (sizeof(struct s_smt_fp_rxd) % 16) {
  221. SMT_PANIC(smc,HWM_E0001,HWM_E0001_MSG) ;
  222. }
  223. if (sizeof(struct s_smt_fp_txd) % 16) {
  224. SMT_PANIC(smc,HWM_E0002,HWM_E0002_MSG) ;
  225. }
  226. /*
  227. * get the required memory for the RxDs and TxDs
  228. */
  229. if (!(smc->os.hwm.descr_p = (union s_fp_descr volatile *)
  230. mac_drv_get_desc_mem(smc,(u_int)
  231. (RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd)))) {
  232. return 1; /* no space the hwm modul can't work */
  233. }
  234. /*
  235. * get the memory for the SMT MBufs
  236. */
  237. #ifndef MB_OUTSIDE_SMC
  238. smc->os.hwm.mbuf_pool.mb_start=(SMbuf *)(&smc->os.hwm.mbuf_pool.mb[0]) ;
  239. #else
  240. #ifndef COMMON_MB_POOL
  241. if (!(smc->os.hwm.mbuf_pool.mb_start = (SMbuf *) mac_drv_get_space(smc,
  242. MAX_MBUF*sizeof(SMbuf)))) {
  243. return 1; /* no space the hwm modul can't work */
  244. }
  245. #else
  246. if (!mb_start) {
  247. if (!(mb_start = (SMbuf *) mac_drv_get_space(smc,
  248. MAX_MBUF*sizeof(SMbuf)))) {
  249. return 1; /* no space the hwm modul can't work */
  250. }
  251. }
  252. #endif
  253. #endif
  254. return 0;
  255. }
  256. /*
  257. * BEGIN_MANUAL_ENTRY(init_driver_fplus)
  258. * init_driver_fplus(smc)
  259. *
  260. * Sets hardware modul specific values for the mode register 2
  261. * (e.g. the byte alignment for the received frames, the position of the
  262. * least significant byte etc.)
  263. * END_MANUAL_ENTRY
  264. */
  265. void init_driver_fplus(struct s_smc *smc)
  266. {
  267. smc->hw.fp.mdr2init = FM_LSB | FM_BMMODE | FM_ENNPRQ | FM_ENHSRQ | 3 ;
  268. #ifdef PCI
  269. smc->hw.fp.mdr2init |= FM_CHKPAR | FM_PARITY ;
  270. #endif
  271. smc->hw.fp.mdr3init = FM_MENRQAUNLCK | FM_MENRS ;
  272. #ifdef USE_CAN_ADDR
  273. /* enable address bit swapping */
  274. smc->hw.fp.frselreg_init = FM_ENXMTADSWAP | FM_ENRCVADSWAP ;
  275. #endif
  276. }
  277. static u_long init_descr_ring(struct s_smc *smc,
  278. union s_fp_descr volatile *start,
  279. int count)
  280. {
  281. int i ;
  282. union s_fp_descr volatile *d1 ;
  283. union s_fp_descr volatile *d2 ;
  284. u_long phys ;
  285. DB_GEN(3, "descr ring starts at = %p", start);
  286. for (i=count-1, d1=start; i ; i--) {
  287. d2 = d1 ;
  288. d1++ ; /* descr is owned by the host */
  289. d2->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
  290. d2->r.rxd_next = &d1->r ;
  291. phys = mac_drv_virt2phys(smc,(void *)d1) ;
  292. d2->r.rxd_nrdadr = cpu_to_le32(phys) ;
  293. }
  294. DB_GEN(3, "descr ring ends at = %p", d1);
  295. d1->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
  296. d1->r.rxd_next = &start->r ;
  297. phys = mac_drv_virt2phys(smc,(void *)start) ;
  298. d1->r.rxd_nrdadr = cpu_to_le32(phys) ;
  299. for (i=count, d1=start; i ; i--) {
  300. DRV_BUF_FLUSH(&d1->r,DDI_DMA_SYNC_FORDEV) ;
  301. d1++;
  302. }
  303. return phys;
  304. }
  305. static void init_txd_ring(struct s_smc *smc)
  306. {
  307. struct s_smt_fp_txd volatile *ds ;
  308. struct s_smt_tx_queue *queue ;
  309. u_long phys ;
  310. /*
  311. * initialize the transmit descriptors
  312. */
  313. ds = (struct s_smt_fp_txd volatile *) ((char *)smc->os.hwm.descr_p +
  314. SMT_R1_RXD_COUNT*sizeof(struct s_smt_fp_rxd)) ;
  315. queue = smc->hw.fp.tx[QUEUE_A0] ;
  316. DB_GEN(3, "Init async TxD ring, %d TxDs", HWM_ASYNC_TXD_COUNT);
  317. (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
  318. HWM_ASYNC_TXD_COUNT) ;
  319. phys = le32_to_cpu(ds->txd_ntdadr) ;
  320. ds++ ;
  321. queue->tx_curr_put = queue->tx_curr_get = ds ;
  322. ds-- ;
  323. queue->tx_free = HWM_ASYNC_TXD_COUNT ;
  324. queue->tx_used = 0 ;
  325. outpd(ADDR(B5_XA_DA),phys) ;
  326. ds = (struct s_smt_fp_txd volatile *) ((char *)ds +
  327. HWM_ASYNC_TXD_COUNT*sizeof(struct s_smt_fp_txd)) ;
  328. queue = smc->hw.fp.tx[QUEUE_S] ;
  329. DB_GEN(3, "Init sync TxD ring, %d TxDs", HWM_SYNC_TXD_COUNT);
  330. (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
  331. HWM_SYNC_TXD_COUNT) ;
  332. phys = le32_to_cpu(ds->txd_ntdadr) ;
  333. ds++ ;
  334. queue->tx_curr_put = queue->tx_curr_get = ds ;
  335. queue->tx_free = HWM_SYNC_TXD_COUNT ;
  336. queue->tx_used = 0 ;
  337. outpd(ADDR(B5_XS_DA),phys) ;
  338. }
  339. static void init_rxd_ring(struct s_smc *smc)
  340. {
  341. struct s_smt_fp_rxd volatile *ds ;
  342. struct s_smt_rx_queue *queue ;
  343. u_long phys ;
  344. /*
  345. * initialize the receive descriptors
  346. */
  347. ds = (struct s_smt_fp_rxd volatile *) smc->os.hwm.descr_p ;
  348. queue = smc->hw.fp.rx[QUEUE_R1] ;
  349. DB_GEN(3, "Init RxD ring, %d RxDs", SMT_R1_RXD_COUNT);
  350. (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
  351. SMT_R1_RXD_COUNT) ;
  352. phys = le32_to_cpu(ds->rxd_nrdadr) ;
  353. ds++ ;
  354. queue->rx_curr_put = queue->rx_curr_get = ds ;
  355. queue->rx_free = SMT_R1_RXD_COUNT ;
  356. queue->rx_used = 0 ;
  357. outpd(ADDR(B4_R1_DA),phys) ;
  358. }
  359. /*
  360. * BEGIN_MANUAL_ENTRY(init_fddi_driver)
  361. * void init_fddi_driver(smc,mac_addr)
  362. *
  363. * initializes the driver and it's variables
  364. *
  365. * END_MANUAL_ENTRY
  366. */
  367. void init_fddi_driver(struct s_smc *smc, u_char *mac_addr)
  368. {
  369. SMbuf *mb ;
  370. int i ;
  371. init_board(smc,mac_addr) ;
  372. (void)init_fplus(smc) ;
  373. /*
  374. * initialize the SMbufs for the SMT
  375. */
  376. #ifndef COMMON_MB_POOL
  377. mb = smc->os.hwm.mbuf_pool.mb_start ;
  378. smc->os.hwm.mbuf_pool.mb_free = (SMbuf *)NULL ;
  379. for (i = 0; i < MAX_MBUF; i++) {
  380. mb->sm_use_count = 1 ;
  381. smt_free_mbuf(smc,mb) ;
  382. mb++ ;
  383. }
  384. #else
  385. mb = mb_start ;
  386. if (!mb_init) {
  387. mb_free = 0 ;
  388. for (i = 0; i < MAX_MBUF; i++) {
  389. mb->sm_use_count = 1 ;
  390. smt_free_mbuf(smc,mb) ;
  391. mb++ ;
  392. }
  393. mb_init = TRUE ;
  394. }
  395. #endif
  396. /*
  397. * initialize the other variables
  398. */
  399. smc->os.hwm.llc_rx_pipe = smc->os.hwm.llc_rx_tail = (SMbuf *)NULL ;
  400. smc->os.hwm.txd_tx_pipe = smc->os.hwm.txd_tx_tail = NULL ;
  401. smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = smc->os.hwm.pass_DB = 0 ;
  402. smc->os.hwm.pass_llc_promisc = TRUE ;
  403. smc->os.hwm.queued_rx_frames = smc->os.hwm.queued_txd_mb = 0 ;
  404. smc->os.hwm.detec_count = 0 ;
  405. smc->os.hwm.rx_break = 0 ;
  406. smc->os.hwm.rx_len_error = 0 ;
  407. smc->os.hwm.isr_flag = FALSE ;
  408. /*
  409. * make sure that the start pointer is 16 byte aligned
  410. */
  411. i = 16 - ((long)smc->os.hwm.descr_p & 0xf) ;
  412. if (i != 16) {
  413. DB_GEN(3, "i = %d", i);
  414. smc->os.hwm.descr_p = (union s_fp_descr volatile *)
  415. ((char *)smc->os.hwm.descr_p+i) ;
  416. }
  417. DB_GEN(3, "pt to descr area = %p", smc->os.hwm.descr_p);
  418. init_txd_ring(smc) ;
  419. init_rxd_ring(smc) ;
  420. mac_drv_fill_rxd(smc) ;
  421. init_plc(smc) ;
  422. }
  423. SMbuf *smt_get_mbuf(struct s_smc *smc)
  424. {
  425. register SMbuf *mb ;
  426. #ifndef COMMON_MB_POOL
  427. mb = smc->os.hwm.mbuf_pool.mb_free ;
  428. #else
  429. mb = mb_free ;
  430. #endif
  431. if (mb) {
  432. #ifndef COMMON_MB_POOL
  433. smc->os.hwm.mbuf_pool.mb_free = mb->sm_next ;
  434. #else
  435. mb_free = mb->sm_next ;
  436. #endif
  437. mb->sm_off = 8 ;
  438. mb->sm_use_count = 1 ;
  439. }
  440. DB_GEN(3, "get SMbuf: mb = %p", mb);
  441. return mb; /* May be NULL */
  442. }
  443. void smt_free_mbuf(struct s_smc *smc, SMbuf *mb)
  444. {
  445. if (mb) {
  446. mb->sm_use_count-- ;
  447. DB_GEN(3, "free_mbuf: sm_use_count = %d", mb->sm_use_count);
  448. /*
  449. * If the use_count is != zero the MBuf is queued
  450. * more than once and must not queued into the
  451. * free MBuf queue
  452. */
  453. if (!mb->sm_use_count) {
  454. DB_GEN(3, "free SMbuf: mb = %p", mb);
  455. #ifndef COMMON_MB_POOL
  456. mb->sm_next = smc->os.hwm.mbuf_pool.mb_free ;
  457. smc->os.hwm.mbuf_pool.mb_free = mb ;
  458. #else
  459. mb->sm_next = mb_free ;
  460. mb_free = mb ;
  461. #endif
  462. }
  463. }
  464. else
  465. SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ;
  466. }
  467. /*
  468. * BEGIN_MANUAL_ENTRY(mac_drv_repair_descr)
  469. * void mac_drv_repair_descr(smc)
  470. *
  471. * function called from SMT (HWM / hwmtm.c)
  472. * The BMU is idle when this function is called.
  473. * Mac_drv_repair_descr sets up the physical address
  474. * for all receive and transmit queues where the BMU
  475. * should continue.
  476. * It may be that the BMU was reseted during a fragmented
  477. * transfer. In this case there are some fragments which will
  478. * never completed by the BMU. The OWN bit of this fragments
  479. * must be switched to be owned by the host.
  480. *
  481. * Give a start command to the receive BMU.
  482. * Start the transmit BMUs if transmit frames pending.
  483. *
  484. * END_MANUAL_ENTRY
  485. */
  486. void mac_drv_repair_descr(struct s_smc *smc)
  487. {
  488. u_long phys ;
  489. if (smc->hw.hw_state != STOPPED) {
  490. SK_BREAK() ;
  491. SMT_PANIC(smc,HWM_E0013,HWM_E0013_MSG) ;
  492. return ;
  493. }
  494. /*
  495. * repair tx queues: don't start
  496. */
  497. phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_A0]) ;
  498. outpd(ADDR(B5_XA_DA),phys) ;
  499. if (smc->hw.fp.tx_q[QUEUE_A0].tx_used) {
  500. outpd(ADDR(B0_XA_CSR),CSR_START) ;
  501. }
  502. phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_S]) ;
  503. outpd(ADDR(B5_XS_DA),phys) ;
  504. if (smc->hw.fp.tx_q[QUEUE_S].tx_used) {
  505. outpd(ADDR(B0_XS_CSR),CSR_START) ;
  506. }
  507. /*
  508. * repair rx queues
  509. */
  510. phys = repair_rxd_ring(smc,smc->hw.fp.rx[QUEUE_R1]) ;
  511. outpd(ADDR(B4_R1_DA),phys) ;
  512. outpd(ADDR(B0_R1_CSR),CSR_START) ;
  513. }
  514. static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue)
  515. {
  516. int i ;
  517. int tx_used ;
  518. u_long phys ;
  519. u_long tbctrl ;
  520. struct s_smt_fp_txd volatile *t ;
  521. SK_UNUSED(smc) ;
  522. t = queue->tx_curr_get ;
  523. tx_used = queue->tx_used ;
  524. for (i = tx_used+queue->tx_free-1 ; i ; i-- ) {
  525. t = t->txd_next ;
  526. }
  527. phys = le32_to_cpu(t->txd_ntdadr) ;
  528. t = queue->tx_curr_get ;
  529. while (tx_used) {
  530. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
  531. tbctrl = le32_to_cpu(t->txd_tbctrl) ;
  532. if (tbctrl & BMU_OWN) {
  533. if (tbctrl & BMU_STF) {
  534. break ; /* exit the loop */
  535. }
  536. else {
  537. /*
  538. * repair the descriptor
  539. */
  540. t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
  541. }
  542. }
  543. phys = le32_to_cpu(t->txd_ntdadr) ;
  544. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
  545. t = t->txd_next ;
  546. tx_used-- ;
  547. }
  548. return phys;
  549. }
  550. /*
  551. * Repairs the receive descriptor ring and returns the physical address
  552. * where the BMU should continue working.
  553. *
  554. * o The physical address where the BMU was stopped has to be
  555. * determined. This is the next RxD after rx_curr_get with an OWN
  556. * bit set.
  557. * o The BMU should start working at beginning of the next frame.
  558. * RxDs with an OWN bit set but with a reset STF bit should be
  559. * skipped and owned by the driver (OWN = 0).
  560. */
  561. static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue)
  562. {
  563. int i ;
  564. int rx_used ;
  565. u_long phys ;
  566. u_long rbctrl ;
  567. struct s_smt_fp_rxd volatile *r ;
  568. SK_UNUSED(smc) ;
  569. r = queue->rx_curr_get ;
  570. rx_used = queue->rx_used ;
  571. for (i = SMT_R1_RXD_COUNT-1 ; i ; i-- ) {
  572. r = r->rxd_next ;
  573. }
  574. phys = le32_to_cpu(r->rxd_nrdadr) ;
  575. r = queue->rx_curr_get ;
  576. while (rx_used) {
  577. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
  578. rbctrl = le32_to_cpu(r->rxd_rbctrl) ;
  579. if (rbctrl & BMU_OWN) {
  580. if (rbctrl & BMU_STF) {
  581. break ; /* exit the loop */
  582. }
  583. else {
  584. /*
  585. * repair the descriptor
  586. */
  587. r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
  588. }
  589. }
  590. phys = le32_to_cpu(r->rxd_nrdadr) ;
  591. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
  592. r = r->rxd_next ;
  593. rx_used-- ;
  594. }
  595. return phys;
  596. }
  597. /*
  598. -------------------------------------------------------------
  599. INTERRUPT SERVICE ROUTINE:
  600. -------------------------------------------------------------
  601. */
  602. /*
  603. * BEGIN_MANUAL_ENTRY(fddi_isr)
  604. * void fddi_isr(smc)
  605. *
  606. * function DOWNCALL (drvsr.c)
  607. * interrupt service routine, handles the interrupt requests
  608. * generated by the FDDI adapter.
  609. *
  610. * NOTE: The operating system dependent module must guarantee that the
  611. * interrupts of the adapter are disabled when it calls fddi_isr.
  612. *
  613. * About the USE_BREAK_ISR mechanismn:
  614. *
  615. * The main requirement of this mechanismn is to force an timer IRQ when
  616. * leaving process_receive() with leave_isr set. process_receive() may
  617. * be called at any time from anywhere!
  618. * To be sure we don't miss such event we set 'force_irq' per default.
  619. * We have to force and Timer IRQ if 'smc->os.hwm.leave_isr' AND
  620. * 'force_irq' are set. 'force_irq' may be reset if a receive complete
  621. * IRQ is pending.
  622. *
  623. * END_MANUAL_ENTRY
  624. */
  625. void fddi_isr(struct s_smc *smc)
  626. {
  627. u_long is ; /* ISR source */
  628. u_short stu, stl ;
  629. SMbuf *mb ;
  630. #ifdef USE_BREAK_ISR
  631. int force_irq ;
  632. #endif
  633. #ifdef ODI2
  634. if (smc->os.hwm.rx_break) {
  635. mac_drv_fill_rxd(smc) ;
  636. if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
  637. smc->os.hwm.rx_break = 0 ;
  638. process_receive(smc) ;
  639. }
  640. else {
  641. smc->os.hwm.detec_count = 0 ;
  642. smt_force_irq(smc) ;
  643. }
  644. }
  645. #endif
  646. smc->os.hwm.isr_flag = TRUE ;
  647. #ifdef USE_BREAK_ISR
  648. force_irq = TRUE ;
  649. if (smc->os.hwm.leave_isr) {
  650. smc->os.hwm.leave_isr = FALSE ;
  651. process_receive(smc) ;
  652. }
  653. #endif
  654. while ((is = GET_ISR() & ISR_MASK)) {
  655. NDD_TRACE("CH0B",is,0,0) ;
  656. DB_GEN(7, "ISA = 0x%lx", is);
  657. if (is & IMASK_SLOW) {
  658. NDD_TRACE("CH1b",is,0,0) ;
  659. if (is & IS_PLINT1) { /* PLC1 */
  660. plc1_irq(smc) ;
  661. }
  662. if (is & IS_PLINT2) { /* PLC2 */
  663. plc2_irq(smc) ;
  664. }
  665. if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
  666. stu = inpw(FM_A(FM_ST1U)) ;
  667. stl = inpw(FM_A(FM_ST1L)) ;
  668. DB_GEN(6, "Slow transmit complete");
  669. mac1_irq(smc,stu,stl) ;
  670. }
  671. if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
  672. stu= inpw(FM_A(FM_ST2U)) ;
  673. stl= inpw(FM_A(FM_ST2L)) ;
  674. DB_GEN(6, "Slow receive complete");
  675. DB_GEN(7, "stl = %x : stu = %x", stl, stu);
  676. mac2_irq(smc,stu,stl) ;
  677. }
  678. if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
  679. stu= inpw(FM_A(FM_ST3U)) ;
  680. stl= inpw(FM_A(FM_ST3L)) ;
  681. DB_GEN(6, "FORMAC Mode Register 3");
  682. mac3_irq(smc,stu,stl) ;
  683. }
  684. if (is & IS_TIMINT) { /* Timer 82C54-2 */
  685. timer_irq(smc) ;
  686. #ifdef NDIS_OS2
  687. force_irq_pending = 0 ;
  688. #endif
  689. /*
  690. * out of RxD detection
  691. */
  692. if (++smc->os.hwm.detec_count > 4) {
  693. /*
  694. * check out of RxD condition
  695. */
  696. process_receive(smc) ;
  697. }
  698. }
  699. if (is & IS_TOKEN) { /* Restricted Token Monitor */
  700. rtm_irq(smc) ;
  701. }
  702. if (is & IS_R1_P) { /* Parity error rx queue 1 */
  703. /* clear IRQ */
  704. outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
  705. SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
  706. }
  707. if (is & IS_R1_C) { /* Encoding error rx queue 1 */
  708. /* clear IRQ */
  709. outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
  710. SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
  711. }
  712. if (is & IS_XA_C) { /* Encoding error async tx q */
  713. /* clear IRQ */
  714. outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
  715. SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
  716. }
  717. if (is & IS_XS_C) { /* Encoding error sync tx q */
  718. /* clear IRQ */
  719. outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
  720. SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
  721. }
  722. }
  723. /*
  724. * Fast Tx complete Async/Sync Queue (BMU service)
  725. */
  726. if (is & (IS_XS_F|IS_XA_F)) {
  727. DB_GEN(6, "Fast tx complete queue");
  728. /*
  729. * clear IRQ, Note: no IRQ is lost, because
  730. * we always service both queues
  731. */
  732. outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
  733. outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
  734. mac_drv_clear_txd(smc) ;
  735. llc_restart_tx(smc) ;
  736. }
  737. /*
  738. * Fast Rx Complete (BMU service)
  739. */
  740. if (is & IS_R1_F) {
  741. DB_GEN(6, "Fast receive complete");
  742. /* clear IRQ */
  743. #ifndef USE_BREAK_ISR
  744. outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
  745. process_receive(smc) ;
  746. #else
  747. process_receive(smc) ;
  748. if (smc->os.hwm.leave_isr) {
  749. force_irq = FALSE ;
  750. } else {
  751. outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
  752. process_receive(smc) ;
  753. }
  754. #endif
  755. }
  756. #ifndef NDIS_OS2
  757. while ((mb = get_llc_rx(smc))) {
  758. smt_to_llc(smc,mb) ;
  759. }
  760. #else
  761. if (offDepth)
  762. post_proc() ;
  763. while (!offDepth && (mb = get_llc_rx(smc))) {
  764. smt_to_llc(smc,mb) ;
  765. }
  766. if (!offDepth && smc->os.hwm.rx_break) {
  767. process_receive(smc) ;
  768. }
  769. #endif
  770. if (smc->q.ev_get != smc->q.ev_put) {
  771. NDD_TRACE("CH2a",0,0,0) ;
  772. ev_dispatcher(smc) ;
  773. }
  774. #ifdef NDIS_OS2
  775. post_proc() ;
  776. if (offDepth) { /* leave fddi_isr because */
  777. break ; /* indications not allowed */
  778. }
  779. #endif
  780. #ifdef USE_BREAK_ISR
  781. if (smc->os.hwm.leave_isr) {
  782. break ; /* leave fddi_isr */
  783. }
  784. #endif
  785. /* NOTE: when the isr is left, no rx is pending */
  786. } /* end of interrupt source polling loop */
  787. #ifdef USE_BREAK_ISR
  788. if (smc->os.hwm.leave_isr && force_irq) {
  789. smt_force_irq(smc) ;
  790. }
  791. #endif
  792. smc->os.hwm.isr_flag = FALSE ;
  793. NDD_TRACE("CH0E",0,0,0) ;
  794. }
  795. /*
  796. -------------------------------------------------------------
  797. RECEIVE FUNCTIONS:
  798. -------------------------------------------------------------
  799. */
  800. #ifndef NDIS_OS2
  801. /*
  802. * BEGIN_MANUAL_ENTRY(mac_drv_rx_mode)
  803. * void mac_drv_rx_mode(smc,mode)
  804. *
  805. * function DOWNCALL (fplus.c)
  806. * Corresponding to the parameter mode, the operating system
  807. * dependent module can activate several receive modes.
  808. *
  809. * para mode = 1: RX_ENABLE_ALLMULTI enable all multicasts
  810. * = 2: RX_DISABLE_ALLMULTI disable "enable all multicasts"
  811. * = 3: RX_ENABLE_PROMISC enable promiscuous
  812. * = 4: RX_DISABLE_PROMISC disable promiscuous
  813. * = 5: RX_ENABLE_NSA enable rec. of all NSA frames
  814. * (disabled after 'driver reset' & 'set station address')
  815. * = 6: RX_DISABLE_NSA disable rec. of all NSA frames
  816. *
  817. * = 21: RX_ENABLE_PASS_SMT ( see description )
  818. * = 22: RX_DISABLE_PASS_SMT ( " " )
  819. * = 23: RX_ENABLE_PASS_NSA ( " " )
  820. * = 24: RX_DISABLE_PASS_NSA ( " " )
  821. * = 25: RX_ENABLE_PASS_DB ( " " )
  822. * = 26: RX_DISABLE_PASS_DB ( " " )
  823. * = 27: RX_DISABLE_PASS_ALL ( " " )
  824. * = 28: RX_DISABLE_LLC_PROMISC ( " " )
  825. * = 29: RX_ENABLE_LLC_PROMISC ( " " )
  826. *
  827. *
  828. * RX_ENABLE_PASS_SMT / RX_DISABLE_PASS_SMT
  829. *
  830. * If the operating system dependent module activates the
  831. * mode RX_ENABLE_PASS_SMT, the hardware module
  832. * duplicates all SMT frames with the frame control
  833. * FC_SMT_INFO and passes them to the LLC receive channel
  834. * by calling mac_drv_rx_init.
  835. * The SMT Frames which are sent by the local SMT and the NSA
  836. * frames whose A- and C-Indicator is not set are also duplicated
  837. * and passed.
  838. * The receive mode RX_DISABLE_PASS_SMT disables the passing
  839. * of SMT frames.
  840. *
  841. * RX_ENABLE_PASS_NSA / RX_DISABLE_PASS_NSA
  842. *
  843. * If the operating system dependent module activates the
  844. * mode RX_ENABLE_PASS_NSA, the hardware module
  845. * duplicates all NSA frames with frame control FC_SMT_NSA
  846. * and a set A-Indicator and passed them to the LLC
  847. * receive channel by calling mac_drv_rx_init.
  848. * All NSA Frames which are sent by the local SMT
  849. * are also duplicated and passed.
  850. * The receive mode RX_DISABLE_PASS_NSA disables the passing
  851. * of NSA frames with the A- or C-Indicator set.
  852. *
  853. * NOTE: For fear that the hardware module receives NSA frames with
  854. * a reset A-Indicator, the operating system dependent module
  855. * has to call mac_drv_rx_mode with the mode RX_ENABLE_NSA
  856. * before activate the RX_ENABLE_PASS_NSA mode and after every
  857. * 'driver reset' and 'set station address'.
  858. *
  859. * RX_ENABLE_PASS_DB / RX_DISABLE_PASS_DB
  860. *
  861. * If the operating system dependent module activates the
  862. * mode RX_ENABLE_PASS_DB, direct BEACON frames
  863. * (FC_BEACON frame control) are passed to the LLC receive
  864. * channel by mac_drv_rx_init.
  865. * The receive mode RX_DISABLE_PASS_DB disables the passing
  866. * of direct BEACON frames.
  867. *
  868. * RX_DISABLE_PASS_ALL
  869. *
  870. * Disables all special receives modes. It is equal to
  871. * call mac_drv_set_rx_mode successively with the
  872. * parameters RX_DISABLE_NSA, RX_DISABLE_PASS_SMT,
  873. * RX_DISABLE_PASS_NSA and RX_DISABLE_PASS_DB.
  874. *
  875. * RX_ENABLE_LLC_PROMISC
  876. *
  877. * (default) all received LLC frames and all SMT/NSA/DBEACON
  878. * frames depending on the attitude of the flags
  879. * PASS_SMT/PASS_NSA/PASS_DBEACON will be delivered to the
  880. * LLC layer
  881. *
  882. * RX_DISABLE_LLC_PROMISC
  883. *
  884. * all received SMT/NSA/DBEACON frames depending on the
  885. * attitude of the flags PASS_SMT/PASS_NSA/PASS_DBEACON
  886. * will be delivered to the LLC layer.
  887. * all received LLC frames with a directed address, Multicast
  888. * or Broadcast address will be delivered to the LLC
  889. * layer too.
  890. *
  891. * END_MANUAL_ENTRY
  892. */
  893. void mac_drv_rx_mode(struct s_smc *smc, int mode)
  894. {
  895. switch(mode) {
  896. case RX_ENABLE_PASS_SMT:
  897. smc->os.hwm.pass_SMT = TRUE ;
  898. break ;
  899. case RX_DISABLE_PASS_SMT:
  900. smc->os.hwm.pass_SMT = FALSE ;
  901. break ;
  902. case RX_ENABLE_PASS_NSA:
  903. smc->os.hwm.pass_NSA = TRUE ;
  904. break ;
  905. case RX_DISABLE_PASS_NSA:
  906. smc->os.hwm.pass_NSA = FALSE ;
  907. break ;
  908. case RX_ENABLE_PASS_DB:
  909. smc->os.hwm.pass_DB = TRUE ;
  910. break ;
  911. case RX_DISABLE_PASS_DB:
  912. smc->os.hwm.pass_DB = FALSE ;
  913. break ;
  914. case RX_DISABLE_PASS_ALL:
  915. smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = FALSE ;
  916. smc->os.hwm.pass_DB = FALSE ;
  917. smc->os.hwm.pass_llc_promisc = TRUE ;
  918. mac_set_rx_mode(smc,RX_DISABLE_NSA) ;
  919. break ;
  920. case RX_DISABLE_LLC_PROMISC:
  921. smc->os.hwm.pass_llc_promisc = FALSE ;
  922. break ;
  923. case RX_ENABLE_LLC_PROMISC:
  924. smc->os.hwm.pass_llc_promisc = TRUE ;
  925. break ;
  926. case RX_ENABLE_ALLMULTI:
  927. case RX_DISABLE_ALLMULTI:
  928. case RX_ENABLE_PROMISC:
  929. case RX_DISABLE_PROMISC:
  930. case RX_ENABLE_NSA:
  931. case RX_DISABLE_NSA:
  932. default:
  933. mac_set_rx_mode(smc,mode) ;
  934. break ;
  935. }
  936. }
  937. #endif /* ifndef NDIS_OS2 */
  938. /*
  939. * process receive queue
  940. */
  941. void process_receive(struct s_smc *smc)
  942. {
  943. int i ;
  944. int n ;
  945. int frag_count ; /* number of RxDs of the curr rx buf */
  946. int used_frags ; /* number of RxDs of the curr frame */
  947. struct s_smt_rx_queue *queue ; /* points to the queue ctl struct */
  948. struct s_smt_fp_rxd volatile *r ; /* rxd pointer */
  949. struct s_smt_fp_rxd volatile *rxd ; /* first rxd of rx frame */
  950. u_long rbctrl ; /* receive buffer control word */
  951. u_long rfsw ; /* receive frame status word */
  952. u_short rx_used ;
  953. u_char far *virt ;
  954. char far *data ;
  955. SMbuf *mb ;
  956. u_char fc ; /* Frame control */
  957. int len ; /* Frame length */
  958. smc->os.hwm.detec_count = 0 ;
  959. queue = smc->hw.fp.rx[QUEUE_R1] ;
  960. NDD_TRACE("RHxB",0,0,0) ;
  961. for ( ; ; ) {
  962. r = queue->rx_curr_get ;
  963. rx_used = queue->rx_used ;
  964. frag_count = 0 ;
  965. #ifdef USE_BREAK_ISR
  966. if (smc->os.hwm.leave_isr) {
  967. goto rx_end ;
  968. }
  969. #endif
  970. #ifdef NDIS_OS2
  971. if (offDepth) {
  972. smc->os.hwm.rx_break = 1 ;
  973. goto rx_end ;
  974. }
  975. smc->os.hwm.rx_break = 0 ;
  976. #endif
  977. #ifdef ODI2
  978. if (smc->os.hwm.rx_break) {
  979. goto rx_end ;
  980. }
  981. #endif
  982. n = 0 ;
  983. do {
  984. DB_RX(5, "Check RxD %p for OWN and EOF", r);
  985. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
  986. rbctrl = le32_to_cpu(CR_READ(r->rxd_rbctrl));
  987. if (rbctrl & BMU_OWN) {
  988. NDD_TRACE("RHxE",r,rfsw,rbctrl) ;
  989. DB_RX(4, "End of RxDs");
  990. goto rx_end ;
  991. }
  992. /*
  993. * out of RxD detection
  994. */
  995. if (!rx_used) {
  996. SK_BREAK() ;
  997. SMT_PANIC(smc,HWM_E0009,HWM_E0009_MSG) ;
  998. /* Either we don't have an RxD or all
  999. * RxDs are filled. Therefore it's allowed
  1000. * for to set the STOPPED flag */
  1001. smc->hw.hw_state = STOPPED ;
  1002. mac_drv_clear_rx_queue(smc) ;
  1003. smc->hw.hw_state = STARTED ;
  1004. mac_drv_fill_rxd(smc) ;
  1005. smc->os.hwm.detec_count = 0 ;
  1006. goto rx_end ;
  1007. }
  1008. rfsw = le32_to_cpu(r->rxd_rfsw) ;
  1009. if ((rbctrl & BMU_STF) != ((rbctrl & BMU_ST_BUF) <<5)) {
  1010. /*
  1011. * The BMU_STF bit is deleted, 1 frame is
  1012. * placed into more than 1 rx buffer
  1013. *
  1014. * skip frame by setting the rx len to 0
  1015. *
  1016. * if fragment count == 0
  1017. * The missing STF bit belongs to the
  1018. * current frame, search for the
  1019. * EOF bit to complete the frame
  1020. * else
  1021. * the fragment belongs to the next frame,
  1022. * exit the loop and process the frame
  1023. */
  1024. SK_BREAK() ;
  1025. rfsw = 0 ;
  1026. if (frag_count) {
  1027. break ;
  1028. }
  1029. }
  1030. n += rbctrl & 0xffff ;
  1031. r = r->rxd_next ;
  1032. frag_count++ ;
  1033. rx_used-- ;
  1034. } while (!(rbctrl & BMU_EOF)) ;
  1035. used_frags = frag_count ;
  1036. DB_RX(5, "EOF set in RxD, used_frags = %d", used_frags);
  1037. /* may be next 2 DRV_BUF_FLUSH() can be skipped, because */
  1038. /* BMU_ST_BUF will not be changed by the ASIC */
  1039. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
  1040. while (rx_used && !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
  1041. DB_RX(5, "Check STF bit in %p", r);
  1042. r = r->rxd_next ;
  1043. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
  1044. frag_count++ ;
  1045. rx_used-- ;
  1046. }
  1047. DB_RX(5, "STF bit found");
  1048. /*
  1049. * The received frame is finished for the process receive
  1050. */
  1051. rxd = queue->rx_curr_get ;
  1052. queue->rx_curr_get = r ;
  1053. queue->rx_free += frag_count ;
  1054. queue->rx_used = rx_used ;
  1055. /*
  1056. * ASIC Errata no. 7 (STF - Bit Bug)
  1057. */
  1058. rxd->rxd_rbctrl &= cpu_to_le32(~BMU_STF) ;
  1059. for (r=rxd, i=frag_count ; i ; r=r->rxd_next, i--){
  1060. DB_RX(5, "dma_complete for RxD %p", r);
  1061. dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
  1062. }
  1063. smc->hw.fp.err_stats.err_valid++ ;
  1064. smc->mib.m[MAC0].fddiMACCopied_Ct++ ;
  1065. /* the length of the data including the FC */
  1066. len = (rfsw & RD_LENGTH) - 4 ;
  1067. DB_RX(4, "frame length = %d", len);
  1068. /*
  1069. * check the frame_length and all error flags
  1070. */
  1071. if (rfsw & (RX_MSRABT|RX_FS_E|RX_FS_CRC|RX_FS_IMPL)){
  1072. if (rfsw & RD_S_MSRABT) {
  1073. DB_RX(2, "Frame aborted by the FORMAC");
  1074. smc->hw.fp.err_stats.err_abort++ ;
  1075. }
  1076. /*
  1077. * check frame status
  1078. */
  1079. if (rfsw & RD_S_SEAC2) {
  1080. DB_RX(2, "E-Indicator set");
  1081. smc->hw.fp.err_stats.err_e_indicator++ ;
  1082. }
  1083. if (rfsw & RD_S_SFRMERR) {
  1084. DB_RX(2, "CRC error");
  1085. smc->hw.fp.err_stats.err_crc++ ;
  1086. }
  1087. if (rfsw & RX_FS_IMPL) {
  1088. DB_RX(2, "Implementer frame");
  1089. smc->hw.fp.err_stats.err_imp_frame++ ;
  1090. }
  1091. goto abort_frame ;
  1092. }
  1093. if (len > FDDI_RAW_MTU-4) {
  1094. DB_RX(2, "Frame too long error");
  1095. smc->hw.fp.err_stats.err_too_long++ ;
  1096. goto abort_frame ;
  1097. }
  1098. /*
  1099. * SUPERNET 3 Bug: FORMAC delivers status words
  1100. * of aborted frames to the BMU
  1101. */
  1102. if (len <= 4) {
  1103. DB_RX(2, "Frame length = 0");
  1104. goto abort_frame ;
  1105. }
  1106. if (len != (n-4)) {
  1107. DB_RX(4, "BMU: rx len differs: [%d:%d]", len, n);
  1108. smc->os.hwm.rx_len_error++ ;
  1109. goto abort_frame ;
  1110. }
  1111. /*
  1112. * Check SA == MA
  1113. */
  1114. virt = (u_char far *) rxd->rxd_virt ;
  1115. DB_RX(2, "FC = %x", *virt);
  1116. if (virt[12] == MA[5] &&
  1117. virt[11] == MA[4] &&
  1118. virt[10] == MA[3] &&
  1119. virt[9] == MA[2] &&
  1120. virt[8] == MA[1] &&
  1121. (virt[7] & ~GROUP_ADDR_BIT) == MA[0]) {
  1122. goto abort_frame ;
  1123. }
  1124. /*
  1125. * test if LLC frame
  1126. */
  1127. if (rfsw & RX_FS_LLC) {
  1128. /*
  1129. * if pass_llc_promisc is disable
  1130. * if DA != Multicast or Broadcast or DA!=MA
  1131. * abort the frame
  1132. */
  1133. if (!smc->os.hwm.pass_llc_promisc) {
  1134. if(!(virt[1] & GROUP_ADDR_BIT)) {
  1135. if (virt[6] != MA[5] ||
  1136. virt[5] != MA[4] ||
  1137. virt[4] != MA[3] ||
  1138. virt[3] != MA[2] ||
  1139. virt[2] != MA[1] ||
  1140. virt[1] != MA[0]) {
  1141. DB_RX(2, "DA != MA and not multi- or broadcast");
  1142. goto abort_frame ;
  1143. }
  1144. }
  1145. }
  1146. /*
  1147. * LLC frame received
  1148. */
  1149. DB_RX(4, "LLC - receive");
  1150. mac_drv_rx_complete(smc,rxd,frag_count,len) ;
  1151. }
  1152. else {
  1153. if (!(mb = smt_get_mbuf(smc))) {
  1154. smc->hw.fp.err_stats.err_no_buf++ ;
  1155. DB_RX(4, "No SMbuf; receive terminated");
  1156. goto abort_frame ;
  1157. }
  1158. data = smtod(mb,char *) - 1 ;
  1159. /*
  1160. * copy the frame into a SMT_MBuf
  1161. */
  1162. #ifdef USE_OS_CPY
  1163. hwm_cpy_rxd2mb(rxd,data,len) ;
  1164. #else
  1165. for (r=rxd, i=used_frags ; i ; r=r->rxd_next, i--){
  1166. n = le32_to_cpu(r->rxd_rbctrl) & RD_LENGTH ;
  1167. DB_RX(6, "cp SMT frame to mb: len = %d", n);
  1168. memcpy(data,r->rxd_virt,n) ;
  1169. data += n ;
  1170. }
  1171. data = smtod(mb,char *) - 1 ;
  1172. #endif
  1173. fc = *(char *)mb->sm_data = *data ;
  1174. mb->sm_len = len - 1 ; /* len - fc */
  1175. data++ ;
  1176. /*
  1177. * SMT frame received
  1178. */
  1179. switch(fc) {
  1180. case FC_SMT_INFO :
  1181. smc->hw.fp.err_stats.err_smt_frame++ ;
  1182. DB_RX(5, "SMT frame received");
  1183. if (smc->os.hwm.pass_SMT) {
  1184. DB_RX(5, "pass SMT frame");
  1185. mac_drv_rx_complete(smc, rxd,
  1186. frag_count,len) ;
  1187. }
  1188. else {
  1189. DB_RX(5, "requeue RxD");
  1190. mac_drv_requeue_rxd(smc,rxd,frag_count);
  1191. }
  1192. smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
  1193. break ;
  1194. case FC_SMT_NSA :
  1195. smc->hw.fp.err_stats.err_smt_frame++ ;
  1196. DB_RX(5, "SMT frame received");
  1197. /* if pass_NSA set pass the NSA frame or */
  1198. /* pass_SMT set and the A-Indicator */
  1199. /* is not set, pass the NSA frame */
  1200. if (smc->os.hwm.pass_NSA ||
  1201. (smc->os.hwm.pass_SMT &&
  1202. !(rfsw & A_INDIC))) {
  1203. DB_RX(5, "pass SMT frame");
  1204. mac_drv_rx_complete(smc, rxd,
  1205. frag_count,len) ;
  1206. }
  1207. else {
  1208. DB_RX(5, "requeue RxD");
  1209. mac_drv_requeue_rxd(smc,rxd,frag_count);
  1210. }
  1211. smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
  1212. break ;
  1213. case FC_BEACON :
  1214. if (smc->os.hwm.pass_DB) {
  1215. DB_RX(5, "pass DB frame");
  1216. mac_drv_rx_complete(smc, rxd,
  1217. frag_count,len) ;
  1218. }
  1219. else {
  1220. DB_RX(5, "requeue RxD");
  1221. mac_drv_requeue_rxd(smc,rxd,frag_count);
  1222. }
  1223. smt_free_mbuf(smc,mb) ;
  1224. break ;
  1225. default :
  1226. /*
  1227. * unknown FC abort the frame
  1228. */
  1229. DB_RX(2, "unknown FC error");
  1230. smt_free_mbuf(smc,mb) ;
  1231. DB_RX(5, "requeue RxD");
  1232. mac_drv_requeue_rxd(smc,rxd,frag_count) ;
  1233. if ((fc & 0xf0) == FC_MAC)
  1234. smc->hw.fp.err_stats.err_mac_frame++ ;
  1235. else
  1236. smc->hw.fp.err_stats.err_imp_frame++ ;
  1237. break ;
  1238. }
  1239. }
  1240. DB_RX(3, "next RxD is %p", queue->rx_curr_get);
  1241. NDD_TRACE("RHx1",queue->rx_curr_get,0,0) ;
  1242. continue ;
  1243. /*--------------------------------------------------------------------*/
  1244. abort_frame:
  1245. DB_RX(5, "requeue RxD");
  1246. mac_drv_requeue_rxd(smc,rxd,frag_count) ;
  1247. DB_RX(3, "next RxD is %p", queue->rx_curr_get);
  1248. NDD_TRACE("RHx2",queue->rx_curr_get,0,0) ;
  1249. }
  1250. rx_end:
  1251. #ifdef ALL_RX_COMPLETE
  1252. mac_drv_all_receives_complete(smc) ;
  1253. #endif
  1254. return ; /* lint bug: needs return detect end of function */
  1255. }
  1256. static void smt_to_llc(struct s_smc *smc, SMbuf *mb)
  1257. {
  1258. u_char fc ;
  1259. DB_RX(4, "send a queued frame to the llc layer");
  1260. smc->os.hwm.r.len = mb->sm_len ;
  1261. smc->os.hwm.r.mb_pos = smtod(mb,char *) ;
  1262. fc = *smc->os.hwm.r.mb_pos ;
  1263. (void)mac_drv_rx_init(smc,(int)mb->sm_len,(int)fc,
  1264. smc->os.hwm.r.mb_pos,(int)mb->sm_len) ;
  1265. smt_free_mbuf(smc,mb) ;
  1266. }
  1267. /*
  1268. * BEGIN_MANUAL_ENTRY(hwm_rx_frag)
  1269. * void hwm_rx_frag(smc,virt,phys,len,frame_status)
  1270. *
  1271. * function MACRO (hardware module, hwmtm.h)
  1272. * This function calls dma_master for preparing the
  1273. * system hardware for the DMA transfer and initializes
  1274. * the current RxD with the length and the physical and
  1275. * virtual address of the fragment. Furthermore, it sets the
  1276. * STF and EOF bits depending on the frame status byte,
  1277. * switches the OWN flag of the RxD, so that it is owned by the
  1278. * adapter and issues an rx_start.
  1279. *
  1280. * para virt virtual pointer to the fragment
  1281. * len the length of the fragment
  1282. * frame_status status of the frame, see design description
  1283. *
  1284. * NOTE: It is possible to call this function with a fragment length
  1285. * of zero.
  1286. *
  1287. * END_MANUAL_ENTRY
  1288. */
  1289. void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
  1290. int frame_status)
  1291. {
  1292. struct s_smt_fp_rxd volatile *r ;
  1293. __le32 rbctrl;
  1294. NDD_TRACE("RHfB",virt,len,frame_status) ;
  1295. DB_RX(2, "hwm_rx_frag: len = %d, frame_status = %x", len, frame_status);
  1296. r = smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put ;
  1297. r->rxd_virt = virt ;
  1298. r->rxd_rbadr = cpu_to_le32(phys) ;
  1299. rbctrl = cpu_to_le32( (((__u32)frame_status &
  1300. (FIRST_FRAG|LAST_FRAG))<<26) |
  1301. (((u_long) frame_status & FIRST_FRAG) << 21) |
  1302. BMU_OWN | BMU_CHECK | BMU_EN_IRQ_EOF | len) ;
  1303. r->rxd_rbctrl = rbctrl ;
  1304. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
  1305. outpd(ADDR(B0_R1_CSR),CSR_START) ;
  1306. smc->hw.fp.rx_q[QUEUE_R1].rx_free-- ;
  1307. smc->hw.fp.rx_q[QUEUE_R1].rx_used++ ;
  1308. smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put = r->rxd_next ;
  1309. NDD_TRACE("RHfE",r,le32_to_cpu(r->rxd_rbadr),0) ;
  1310. }
  1311. /*
  1312. * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue)
  1313. *
  1314. * void mac_drv_clear_rx_queue(smc)
  1315. * struct s_smc *smc ;
  1316. *
  1317. * function DOWNCALL (hardware module, hwmtm.c)
  1318. * mac_drv_clear_rx_queue is called by the OS-specific module
  1319. * after it has issued a card_stop.
  1320. * In this case, the frames in the receive queue are obsolete and
  1321. * should be removed. For removing mac_drv_clear_rx_queue
  1322. * calls dma_master for each RxD and mac_drv_clear_rxd for each
  1323. * receive buffer.
  1324. *
  1325. * NOTE: calling sequence card_stop:
  1326. * CLI_FBI(), card_stop(),
  1327. * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
  1328. *
  1329. * NOTE: The caller is responsible that the BMUs are idle
  1330. * when this function is called.
  1331. *
  1332. * END_MANUAL_ENTRY
  1333. */
  1334. void mac_drv_clear_rx_queue(struct s_smc *smc)
  1335. {
  1336. struct s_smt_fp_rxd volatile *r ;
  1337. struct s_smt_fp_rxd volatile *next_rxd ;
  1338. struct s_smt_rx_queue *queue ;
  1339. int frag_count ;
  1340. int i ;
  1341. if (smc->hw.hw_state != STOPPED) {
  1342. SK_BREAK() ;
  1343. SMT_PANIC(smc,HWM_E0012,HWM_E0012_MSG) ;
  1344. return ;
  1345. }
  1346. queue = smc->hw.fp.rx[QUEUE_R1] ;
  1347. DB_RX(5, "clear_rx_queue");
  1348. /*
  1349. * dma_complete and mac_drv_clear_rxd for all RxDs / receive buffers
  1350. */
  1351. r = queue->rx_curr_get ;
  1352. while (queue->rx_used) {
  1353. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
  1354. DB_RX(5, "switch OWN bit of RxD 0x%p", r);
  1355. r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
  1356. frag_count = 1 ;
  1357. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
  1358. r = r->rxd_next ;
  1359. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
  1360. while (r != queue->rx_curr_put &&
  1361. !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
  1362. DB_RX(5, "Check STF bit in %p", r);
  1363. r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
  1364. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
  1365. r = r->rxd_next ;
  1366. DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
  1367. frag_count++ ;
  1368. }
  1369. DB_RX(5, "STF bit found");
  1370. next_rxd = r ;
  1371. for (r=queue->rx_curr_get,i=frag_count; i ; r=r->rxd_next,i--){
  1372. DB_RX(5, "dma_complete for RxD %p", r);
  1373. dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
  1374. }
  1375. DB_RX(5, "mac_drv_clear_rxd: RxD %p frag_count %d",
  1376. queue->rx_curr_get, frag_count);
  1377. mac_drv_clear_rxd(smc,queue->rx_curr_get,frag_count) ;
  1378. queue->rx_curr_get = next_rxd ;
  1379. queue->rx_used -= frag_count ;
  1380. queue->rx_free += frag_count ;
  1381. }
  1382. }
  1383. /*
  1384. -------------------------------------------------------------
  1385. SEND FUNCTIONS:
  1386. -------------------------------------------------------------
  1387. */
  1388. /*
  1389. * BEGIN_MANUAL_ENTRY(hwm_tx_init)
  1390. * int hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)
  1391. *
  1392. * function DOWN_CALL (hardware module, hwmtm.c)
  1393. * hwm_tx_init checks if the frame can be sent through the
  1394. * corresponding send queue.
  1395. *
  1396. * para fc the frame control. To determine through which
  1397. * send queue the frame should be transmitted.
  1398. * 0x50 - 0x57: asynchronous LLC frame
  1399. * 0xD0 - 0xD7: synchronous LLC frame
  1400. * 0x41, 0x4F: SMT frame to the network
  1401. * 0x42: SMT frame to the network and to the local SMT
  1402. * 0x43: SMT frame to the local SMT
  1403. * frag_count count of the fragments for this frame
  1404. * frame_len length of the frame
  1405. * frame_status status of the frame, the send queue bit is already
  1406. * specified
  1407. *
  1408. * return frame_status
  1409. *
  1410. * END_MANUAL_ENTRY
  1411. */
  1412. int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
  1413. int frame_status)
  1414. {
  1415. NDD_TRACE("THiB",fc,frag_count,frame_len) ;
  1416. smc->os.hwm.tx_p = smc->hw.fp.tx[frame_status & QUEUE_A0] ;
  1417. smc->os.hwm.tx_descr = TX_DESCRIPTOR | (((u_long)(frame_len-1)&3)<<27) ;
  1418. smc->os.hwm.tx_len = frame_len ;
  1419. DB_TX(3, "hwm_tx_init: fc = %x, len = %d", fc, frame_len);
  1420. if ((fc & ~(FC_SYNC_BIT|FC_LLC_PRIOR)) == FC_ASYNC_LLC) {
  1421. frame_status |= LAN_TX ;
  1422. }
  1423. else {
  1424. switch (fc) {
  1425. case FC_SMT_INFO :
  1426. case FC_SMT_NSA :
  1427. frame_status |= LAN_TX ;
  1428. break ;
  1429. case FC_SMT_LOC :
  1430. frame_status |= LOC_TX ;
  1431. break ;
  1432. case FC_SMT_LAN_LOC :
  1433. frame_status |= LAN_TX | LOC_TX ;
  1434. break ;
  1435. default :
  1436. SMT_PANIC(smc,HWM_E0010,HWM_E0010_MSG) ;
  1437. }
  1438. }
  1439. if (!smc->hw.mac_ring_is_up) {
  1440. frame_status &= ~LAN_TX ;
  1441. frame_status |= RING_DOWN ;
  1442. DB_TX(2, "Ring is down: terminate LAN_TX");
  1443. }
  1444. if (frag_count > smc->os.hwm.tx_p->tx_free) {
  1445. #ifndef NDIS_OS2
  1446. mac_drv_clear_txd(smc) ;
  1447. if (frag_count > smc->os.hwm.tx_p->tx_free) {
  1448. DB_TX(2, "Out of TxDs, terminate LAN_TX");
  1449. frame_status &= ~LAN_TX ;
  1450. frame_status |= OUT_OF_TXD ;
  1451. }
  1452. #else
  1453. DB_TX(2, "Out of TxDs, terminate LAN_TX");
  1454. frame_status &= ~LAN_TX ;
  1455. frame_status |= OUT_OF_TXD ;
  1456. #endif
  1457. }
  1458. DB_TX(3, "frame_status = %x", frame_status);
  1459. NDD_TRACE("THiE",frame_status,smc->os.hwm.tx_p->tx_free,0) ;
  1460. return frame_status;
  1461. }
  1462. /*
  1463. * BEGIN_MANUAL_ENTRY(hwm_tx_frag)
  1464. * void hwm_tx_frag(smc,virt,phys,len,frame_status)
  1465. *
  1466. * function DOWNCALL (hardware module, hwmtm.c)
  1467. * If the frame should be sent to the LAN, this function calls
  1468. * dma_master, fills the current TxD with the virtual and the
  1469. * physical address, sets the STF and EOF bits dependent on
  1470. * the frame status, and requests the BMU to start the
  1471. * transmit.
  1472. * If the frame should be sent to the local SMT, an SMT_MBuf
  1473. * is allocated if the FIRST_FRAG bit is set in the frame_status.
  1474. * The fragment of the frame is copied into the SMT MBuf.
  1475. * The function smt_received_pack is called if the LAST_FRAG
  1476. * bit is set in the frame_status word.
  1477. *
  1478. * para virt virtual pointer to the fragment
  1479. * len the length of the fragment
  1480. * frame_status status of the frame, see design description
  1481. *
  1482. * return nothing returned, no parameter is modified
  1483. *
  1484. * NOTE: It is possible to invoke this macro with a fragment length
  1485. * of zero.
  1486. *
  1487. * END_MANUAL_ENTRY
  1488. */
  1489. void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
  1490. int frame_status)
  1491. {
  1492. struct s_smt_fp_txd volatile *t ;
  1493. struct s_smt_tx_queue *queue ;
  1494. __le32 tbctrl ;
  1495. queue = smc->os.hwm.tx_p ;
  1496. NDD_TRACE("THfB",virt,len,frame_status) ;
  1497. /* Bug fix: AF / May 31 1999 (#missing)
  1498. * snmpinfo problem reported by IBM is caused by invalid
  1499. * t-pointer (txd) if LAN_TX is not set but LOC_TX only.
  1500. * Set: t = queue->tx_curr_put here !
  1501. */
  1502. t = queue->tx_curr_put ;
  1503. DB_TX(2, "hwm_tx_frag: len = %d, frame_status = %x", len, frame_status);
  1504. if (frame_status & LAN_TX) {
  1505. /* '*t' is already defined */
  1506. DB_TX(3, "LAN_TX: TxD = %p, virt = %p", t, virt);
  1507. t->txd_virt = virt ;
  1508. t->txd_txdscr = cpu_to_le32(smc->os.hwm.tx_descr) ;
  1509. t->txd_tbadr = cpu_to_le32(phys) ;
  1510. tbctrl = cpu_to_le32((((__u32)frame_status &
  1511. (FIRST_FRAG|LAST_FRAG|EN_IRQ_EOF))<< 26) |
  1512. BMU_OWN|BMU_CHECK |len) ;
  1513. t->txd_tbctrl = tbctrl ;
  1514. #ifndef AIX
  1515. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
  1516. outpd(queue->tx_bmu_ctl,CSR_START) ;
  1517. #else /* ifndef AIX */
  1518. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
  1519. if (frame_status & QUEUE_A0) {
  1520. outpd(ADDR(B0_XA_CSR),CSR_START) ;
  1521. }
  1522. else {
  1523. outpd(ADDR(B0_XS_CSR),CSR_START) ;
  1524. }
  1525. #endif
  1526. queue->tx_free-- ;
  1527. queue->tx_used++ ;
  1528. queue->tx_curr_put = t->txd_next ;
  1529. if (frame_status & LAST_FRAG) {
  1530. smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
  1531. }
  1532. }
  1533. if (frame_status & LOC_TX) {
  1534. DB_TX(3, "LOC_TX:");
  1535. if (frame_status & FIRST_FRAG) {
  1536. if(!(smc->os.hwm.tx_mb = smt_get_mbuf(smc))) {
  1537. smc->hw.fp.err_stats.err_no_buf++ ;
  1538. DB_TX(4, "No SMbuf; transmit terminated");
  1539. }
  1540. else {
  1541. smc->os.hwm.tx_data =
  1542. smtod(smc->os.hwm.tx_mb,char *) - 1 ;
  1543. #ifdef USE_OS_CPY
  1544. #ifdef PASS_1ST_TXD_2_TX_COMP
  1545. hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
  1546. smc->os.hwm.tx_len) ;
  1547. #endif
  1548. #endif
  1549. }
  1550. }
  1551. if (smc->os.hwm.tx_mb) {
  1552. #ifndef USE_OS_CPY
  1553. DB_TX(3, "copy fragment into MBuf");
  1554. memcpy(smc->os.hwm.tx_data,virt,len) ;
  1555. smc->os.hwm.tx_data += len ;
  1556. #endif
  1557. if (frame_status & LAST_FRAG) {
  1558. #ifdef USE_OS_CPY
  1559. #ifndef PASS_1ST_TXD_2_TX_COMP
  1560. /*
  1561. * hwm_cpy_txd2mb(txd,data,len) copies 'len'
  1562. * bytes from the virtual pointer in 'rxd'
  1563. * to 'data'. The virtual pointer of the
  1564. * os-specific tx-buffer should be written
  1565. * in the LAST txd.
  1566. */
  1567. hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
  1568. smc->os.hwm.tx_len) ;
  1569. #endif /* nPASS_1ST_TXD_2_TX_COMP */
  1570. #endif /* USE_OS_CPY */
  1571. smc->os.hwm.tx_data =
  1572. smtod(smc->os.hwm.tx_mb,char *) - 1 ;
  1573. *(char *)smc->os.hwm.tx_mb->sm_data =
  1574. *smc->os.hwm.tx_data ;
  1575. smc->os.hwm.tx_data++ ;
  1576. smc->os.hwm.tx_mb->sm_len =
  1577. smc->os.hwm.tx_len - 1 ;
  1578. DB_TX(3, "pass LLC frame to SMT");
  1579. smt_received_pack(smc,smc->os.hwm.tx_mb,
  1580. RD_FS_LOCAL) ;
  1581. }
  1582. }
  1583. }
  1584. NDD_TRACE("THfE",t,queue->tx_free,0) ;
  1585. }
  1586. /*
  1587. * queues a receive for later send
  1588. */
  1589. static void queue_llc_rx(struct s_smc *smc, SMbuf *mb)
  1590. {
  1591. DB_GEN(4, "queue_llc_rx: mb = %p", mb);
  1592. smc->os.hwm.queued_rx_frames++ ;
  1593. mb->sm_next = (SMbuf *)NULL ;
  1594. if (smc->os.hwm.llc_rx_pipe == NULL) {
  1595. smc->os.hwm.llc_rx_pipe = mb ;
  1596. }
  1597. else {
  1598. smc->os.hwm.llc_rx_tail->sm_next = mb ;
  1599. }
  1600. smc->os.hwm.llc_rx_tail = mb ;
  1601. /*
  1602. * force an timer IRQ to receive the data
  1603. */
  1604. if (!smc->os.hwm.isr_flag) {
  1605. smt_force_irq(smc) ;
  1606. }
  1607. }
  1608. /*
  1609. * get a SMbuf from the llc_rx_queue
  1610. */
  1611. static SMbuf *get_llc_rx(struct s_smc *smc)
  1612. {
  1613. SMbuf *mb ;
  1614. if ((mb = smc->os.hwm.llc_rx_pipe)) {
  1615. smc->os.hwm.queued_rx_frames-- ;
  1616. smc->os.hwm.llc_rx_pipe = mb->sm_next ;
  1617. }
  1618. DB_GEN(4, "get_llc_rx: mb = 0x%p", mb);
  1619. return mb;
  1620. }
  1621. /*
  1622. * queues a transmit SMT MBuf during the time were the MBuf is
  1623. * queued the TxD ring
  1624. */
  1625. static void queue_txd_mb(struct s_smc *smc, SMbuf *mb)
  1626. {
  1627. DB_GEN(4, "_rx: queue_txd_mb = %p", mb);
  1628. smc->os.hwm.queued_txd_mb++ ;
  1629. mb->sm_next = (SMbuf *)NULL ;
  1630. if (smc->os.hwm.txd_tx_pipe == NULL) {
  1631. smc->os.hwm.txd_tx_pipe = mb ;
  1632. }
  1633. else {
  1634. smc->os.hwm.txd_tx_tail->sm_next = mb ;
  1635. }
  1636. smc->os.hwm.txd_tx_tail = mb ;
  1637. }
  1638. /*
  1639. * get a SMbuf from the txd_tx_queue
  1640. */
  1641. static SMbuf *get_txd_mb(struct s_smc *smc)
  1642. {
  1643. SMbuf *mb ;
  1644. if ((mb = smc->os.hwm.txd_tx_pipe)) {
  1645. smc->os.hwm.queued_txd_mb-- ;
  1646. smc->os.hwm.txd_tx_pipe = mb->sm_next ;
  1647. }
  1648. DB_GEN(4, "get_txd_mb: mb = 0x%p", mb);
  1649. return mb;
  1650. }
  1651. /*
  1652. * SMT Send function
  1653. */
  1654. void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc)
  1655. {
  1656. char far *data ;
  1657. int len ;
  1658. int n ;
  1659. int i ;
  1660. int frag_count ;
  1661. int frame_status ;
  1662. SK_LOC_DECL(char far,*virt[3]) ;
  1663. int frag_len[3] ;
  1664. struct s_smt_tx_queue *queue ;
  1665. struct s_smt_fp_txd volatile *t ;
  1666. u_long phys ;
  1667. __le32 tbctrl;
  1668. NDD_TRACE("THSB",mb,fc,0) ;
  1669. DB_TX(4, "smt_send_mbuf: mb = 0x%p, fc = 0x%x", mb, fc);
  1670. mb->sm_off-- ; /* set to fc */
  1671. mb->sm_len++ ; /* + fc */
  1672. data = smtod(mb,char *) ;
  1673. *data = fc ;
  1674. if (fc == FC_SMT_LOC)
  1675. *data = FC_SMT_INFO ;
  1676. /*
  1677. * determine the frag count and the virt addresses of the frags
  1678. */
  1679. frag_count = 0 ;
  1680. len = mb->sm_len ;
  1681. while (len) {
  1682. n = SMT_PAGESIZE - ((long)data & (SMT_PAGESIZE-1)) ;
  1683. if (n >= len) {
  1684. n = len ;
  1685. }
  1686. DB_TX(5, "frag: virt/len = 0x%p/%d", data, n);
  1687. virt[frag_count] = data ;
  1688. frag_len[frag_count] = n ;
  1689. frag_count++ ;
  1690. len -= n ;
  1691. data += n ;
  1692. }
  1693. /*
  1694. * determine the frame status
  1695. */
  1696. queue = smc->hw.fp.tx[QUEUE_A0] ;
  1697. if (fc == FC_BEACON || fc == FC_SMT_LOC) {
  1698. frame_status = LOC_TX ;
  1699. }
  1700. else {
  1701. frame_status = LAN_TX ;
  1702. if ((smc->os.hwm.pass_NSA &&(fc == FC_SMT_NSA)) ||
  1703. (smc->os.hwm.pass_SMT &&(fc == FC_SMT_INFO)))
  1704. frame_status |= LOC_TX ;
  1705. }
  1706. if (!smc->hw.mac_ring_is_up || frag_count > queue->tx_free) {
  1707. frame_status &= ~LAN_TX;
  1708. if (frame_status) {
  1709. DB_TX(2, "Ring is down: terminate LAN_TX");
  1710. }
  1711. else {
  1712. DB_TX(2, "Ring is down: terminate transmission");
  1713. smt_free_mbuf(smc,mb) ;
  1714. return ;
  1715. }
  1716. }
  1717. DB_TX(5, "frame_status = 0x%x", frame_status);
  1718. if ((frame_status & LAN_TX) && (frame_status & LOC_TX)) {
  1719. mb->sm_use_count = 2 ;
  1720. }
  1721. if (frame_status & LAN_TX) {
  1722. t = queue->tx_curr_put ;
  1723. frame_status |= FIRST_FRAG ;
  1724. for (i = 0; i < frag_count; i++) {
  1725. DB_TX(5, "init TxD = 0x%p", t);
  1726. if (i == frag_count-1) {
  1727. frame_status |= LAST_FRAG ;
  1728. t->txd_txdscr = cpu_to_le32(TX_DESCRIPTOR |
  1729. (((__u32)(mb->sm_len-1)&3) << 27)) ;
  1730. }
  1731. t->txd_virt = virt[i] ;
  1732. phys = dma_master(smc, (void far *)virt[i],
  1733. frag_len[i], DMA_RD|SMT_BUF) ;
  1734. t->txd_tbadr = cpu_to_le32(phys) ;
  1735. tbctrl = cpu_to_le32((((__u32)frame_status &
  1736. (FIRST_FRAG|LAST_FRAG)) << 26) |
  1737. BMU_OWN | BMU_CHECK | BMU_SMT_TX |frag_len[i]) ;
  1738. t->txd_tbctrl = tbctrl ;
  1739. #ifndef AIX
  1740. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
  1741. outpd(queue->tx_bmu_ctl,CSR_START) ;
  1742. #else
  1743. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
  1744. outpd(ADDR(B0_XA_CSR),CSR_START) ;
  1745. #endif
  1746. frame_status &= ~FIRST_FRAG ;
  1747. queue->tx_curr_put = t = t->txd_next ;
  1748. queue->tx_free-- ;
  1749. queue->tx_used++ ;
  1750. }
  1751. smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
  1752. queue_txd_mb(smc,mb) ;
  1753. }
  1754. if (frame_status & LOC_TX) {
  1755. DB_TX(5, "pass Mbuf to LLC queue");
  1756. queue_llc_rx(smc,mb) ;
  1757. }
  1758. /*
  1759. * We need to unqueue the free SMT_MBUFs here, because it may
  1760. * be that the SMT want's to send more than 1 frame for one down call
  1761. */
  1762. mac_drv_clear_txd(smc) ;
  1763. NDD_TRACE("THSE",t,queue->tx_free,frag_count) ;
  1764. }
  1765. /* BEGIN_MANUAL_ENTRY(mac_drv_clear_txd)
  1766. * void mac_drv_clear_txd(smc)
  1767. *
  1768. * function DOWNCALL (hardware module, hwmtm.c)
  1769. * mac_drv_clear_txd searches in both send queues for TxD's
  1770. * which were finished by the adapter. It calls dma_complete
  1771. * for each TxD. If the last fragment of an LLC frame is
  1772. * reached, it calls mac_drv_tx_complete to release the
  1773. * send buffer.
  1774. *
  1775. * return nothing
  1776. *
  1777. * END_MANUAL_ENTRY
  1778. */
  1779. static void mac_drv_clear_txd(struct s_smc *smc)
  1780. {
  1781. struct s_smt_tx_queue *queue ;
  1782. struct s_smt_fp_txd volatile *t1 ;
  1783. struct s_smt_fp_txd volatile *t2 = NULL ;
  1784. SMbuf *mb ;
  1785. u_long tbctrl ;
  1786. int i ;
  1787. int frag_count ;
  1788. int n ;
  1789. NDD_TRACE("THcB",0,0,0) ;
  1790. for (i = QUEUE_S; i <= QUEUE_A0; i++) {
  1791. queue = smc->hw.fp.tx[i] ;
  1792. t1 = queue->tx_curr_get ;
  1793. DB_TX(5, "clear_txd: QUEUE = %d (0=sync/1=async)", i);
  1794. for ( ; ; ) {
  1795. frag_count = 0 ;
  1796. do {
  1797. DRV_BUF_FLUSH(t1,DDI_DMA_SYNC_FORCPU) ;
  1798. DB_TX(5, "check OWN/EOF bit of TxD 0x%p", t1);
  1799. tbctrl = le32_to_cpu(CR_READ(t1->txd_tbctrl));
  1800. if (tbctrl & BMU_OWN || !queue->tx_used){
  1801. DB_TX(4, "End of TxDs queue %d", i);
  1802. goto free_next_queue ; /* next queue */
  1803. }
  1804. t1 = t1->txd_next ;
  1805. frag_count++ ;
  1806. } while (!(tbctrl & BMU_EOF)) ;
  1807. t1 = queue->tx_curr_get ;
  1808. for (n = frag_count; n; n--) {
  1809. tbctrl = le32_to_cpu(t1->txd_tbctrl) ;
  1810. dma_complete(smc,
  1811. (union s_fp_descr volatile *) t1,
  1812. (int) (DMA_RD |
  1813. ((tbctrl & BMU_SMT_TX) >> 18))) ;
  1814. t2 = t1 ;
  1815. t1 = t1->txd_next ;
  1816. }
  1817. if (tbctrl & BMU_SMT_TX) {
  1818. mb = get_txd_mb(smc) ;
  1819. smt_free_mbuf(smc,mb) ;
  1820. }
  1821. else {
  1822. #ifndef PASS_1ST_TXD_2_TX_COMP
  1823. DB_TX(4, "mac_drv_tx_comp for TxD 0x%p", t2);
  1824. mac_drv_tx_complete(smc,t2) ;
  1825. #else
  1826. DB_TX(4, "mac_drv_tx_comp for TxD 0x%x",
  1827. queue->tx_curr_get);
  1828. mac_drv_tx_complete(smc,queue->tx_curr_get) ;
  1829. #endif
  1830. }
  1831. queue->tx_curr_get = t1 ;
  1832. queue->tx_free += frag_count ;
  1833. queue->tx_used -= frag_count ;
  1834. }
  1835. free_next_queue: ;
  1836. }
  1837. NDD_TRACE("THcE",0,0,0) ;
  1838. }
  1839. /*
  1840. * BEGINN_MANUAL_ENTRY(mac_drv_clear_tx_queue)
  1841. *
  1842. * void mac_drv_clear_tx_queue(smc)
  1843. * struct s_smc *smc ;
  1844. *
  1845. * function DOWNCALL (hardware module, hwmtm.c)
  1846. * mac_drv_clear_tx_queue is called from the SMT when
  1847. * the RMT state machine has entered the ISOLATE state.
  1848. * This function is also called by the os-specific module
  1849. * after it has called the function card_stop().
  1850. * In this case, the frames in the send queues are obsolete and
  1851. * should be removed.
  1852. *
  1853. * note calling sequence:
  1854. * CLI_FBI(), card_stop(),
  1855. * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
  1856. *
  1857. * NOTE: The caller is responsible that the BMUs are idle
  1858. * when this function is called.
  1859. *
  1860. * END_MANUAL_ENTRY
  1861. */
  1862. void mac_drv_clear_tx_queue(struct s_smc *smc)
  1863. {
  1864. struct s_smt_fp_txd volatile *t ;
  1865. struct s_smt_tx_queue *queue ;
  1866. int tx_used ;
  1867. int i ;
  1868. if (smc->hw.hw_state != STOPPED) {
  1869. SK_BREAK() ;
  1870. SMT_PANIC(smc,HWM_E0011,HWM_E0011_MSG) ;
  1871. return ;
  1872. }
  1873. for (i = QUEUE_S; i <= QUEUE_A0; i++) {
  1874. queue = smc->hw.fp.tx[i] ;
  1875. DB_TX(5, "clear_tx_queue: QUEUE = %d (0=sync/1=async)", i);
  1876. /*
  1877. * switch the OWN bit of all pending frames to the host
  1878. */
  1879. t = queue->tx_curr_get ;
  1880. tx_used = queue->tx_used ;
  1881. while (tx_used) {
  1882. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
  1883. DB_TX(5, "switch OWN bit of TxD 0x%p", t);
  1884. t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
  1885. DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
  1886. t = t->txd_next ;
  1887. tx_used-- ;
  1888. }
  1889. }
  1890. /*
  1891. * release all TxD's for both send queues
  1892. */
  1893. mac_drv_clear_txd(smc) ;
  1894. for (i = QUEUE_S; i <= QUEUE_A0; i++) {
  1895. queue = smc->hw.fp.tx[i] ;
  1896. t = queue->tx_curr_get ;
  1897. /*
  1898. * write the phys pointer of the NEXT descriptor into the
  1899. * BMU's current address descriptor pointer and set
  1900. * tx_curr_get and tx_curr_put to this position
  1901. */
  1902. if (i == QUEUE_S) {
  1903. outpd(ADDR(B5_XS_DA),le32_to_cpu(t->txd_ntdadr)) ;
  1904. }
  1905. else {
  1906. outpd(ADDR(B5_XA_DA),le32_to_cpu(t->txd_ntdadr)) ;
  1907. }
  1908. queue->tx_curr_put = queue->tx_curr_get->txd_next ;
  1909. queue->tx_curr_get = queue->tx_curr_put ;
  1910. }
  1911. }
  1912. /*
  1913. -------------------------------------------------------------
  1914. TEST FUNCTIONS:
  1915. -------------------------------------------------------------
  1916. */
  1917. #ifdef DEBUG
  1918. /*
  1919. * BEGIN_MANUAL_ENTRY(mac_drv_debug_lev)
  1920. * void mac_drv_debug_lev(smc,flag,lev)
  1921. *
  1922. * function DOWNCALL (drvsr.c)
  1923. * To get a special debug info the user can assign a debug level
  1924. * to any debug flag.
  1925. *
  1926. * para flag debug flag, possible values are:
  1927. * = 0: reset all debug flags (the defined level is
  1928. * ignored)
  1929. * = 1: debug.d_smtf
  1930. * = 2: debug.d_smt
  1931. * = 3: debug.d_ecm
  1932. * = 4: debug.d_rmt
  1933. * = 5: debug.d_cfm
  1934. * = 6: debug.d_pcm
  1935. *
  1936. * = 10: debug.d_os.hwm_rx (hardware module receive path)
  1937. * = 11: debug.d_os.hwm_tx(hardware module transmit path)
  1938. * = 12: debug.d_os.hwm_gen(hardware module general flag)
  1939. *
  1940. * lev debug level
  1941. *
  1942. * END_MANUAL_ENTRY
  1943. */
  1944. void mac_drv_debug_lev(struct s_smc *smc, int flag, int lev)
  1945. {
  1946. switch(flag) {
  1947. case (int)NULL:
  1948. DB_P.d_smtf = DB_P.d_smt = DB_P.d_ecm = DB_P.d_rmt = 0 ;
  1949. DB_P.d_cfm = 0 ;
  1950. DB_P.d_os.hwm_rx = DB_P.d_os.hwm_tx = DB_P.d_os.hwm_gen = 0 ;
  1951. #ifdef SBA
  1952. DB_P.d_sba = 0 ;
  1953. #endif
  1954. #ifdef ESS
  1955. DB_P.d_ess = 0 ;
  1956. #endif
  1957. break ;
  1958. case DEBUG_SMTF:
  1959. DB_P.d_smtf = lev ;
  1960. break ;
  1961. case DEBUG_SMT:
  1962. DB_P.d_smt = lev ;
  1963. break ;
  1964. case DEBUG_ECM:
  1965. DB_P.d_ecm = lev ;
  1966. break ;
  1967. case DEBUG_RMT:
  1968. DB_P.d_rmt = lev ;
  1969. break ;
  1970. case DEBUG_CFM:
  1971. DB_P.d_cfm = lev ;
  1972. break ;
  1973. case DEBUG_PCM:
  1974. DB_P.d_pcm = lev ;
  1975. break ;
  1976. case DEBUG_SBA:
  1977. #ifdef SBA
  1978. DB_P.d_sba = lev ;
  1979. #endif
  1980. break ;
  1981. case DEBUG_ESS:
  1982. #ifdef ESS
  1983. DB_P.d_ess = lev ;
  1984. #endif
  1985. break ;
  1986. case DB_HWM_RX:
  1987. DB_P.d_os.hwm_rx = lev ;
  1988. break ;
  1989. case DB_HWM_TX:
  1990. DB_P.d_os.hwm_tx = lev ;
  1991. break ;
  1992. case DB_HWM_GEN:
  1993. DB_P.d_os.hwm_gen = lev ;
  1994. break ;
  1995. default:
  1996. break ;
  1997. }
  1998. }
  1999. #endif