emac_rockchip.c 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * emac-rockchip.c - Rockchip EMAC specific glue layer
  4. *
  5. * Copyright (C) 2014 Romain Perier <[email protected]>
  6. */
  7. #include <linux/etherdevice.h>
  8. #include <linux/mfd/syscon.h>
  9. #include <linux/module.h>
  10. #include <linux/of_net.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #include <linux/regulator/consumer.h>
  14. #include "emac.h"
  15. #define DRV_NAME "rockchip_emac"
  16. struct emac_rockchip_soc_data {
  17. unsigned int grf_offset;
  18. unsigned int grf_mode_offset;
  19. unsigned int grf_speed_offset;
  20. bool need_div_macclk;
  21. };
  22. struct rockchip_priv_data {
  23. struct arc_emac_priv emac;
  24. struct regmap *grf;
  25. const struct emac_rockchip_soc_data *soc_data;
  26. struct regulator *regulator;
  27. struct clk *refclk;
  28. struct clk *macclk;
  29. };
  30. static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
  31. {
  32. struct rockchip_priv_data *emac = priv;
  33. u32 speed_offset = emac->soc_data->grf_speed_offset;
  34. u32 data;
  35. int err = 0;
  36. switch (speed) {
  37. case 10:
  38. data = (1 << (speed_offset + 16)) | (0 << speed_offset);
  39. break;
  40. case 100:
  41. data = (1 << (speed_offset + 16)) | (1 << speed_offset);
  42. break;
  43. default:
  44. pr_err("speed %u not supported\n", speed);
  45. return;
  46. }
  47. err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
  48. if (err)
  49. pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
  50. }
  51. static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
  52. .grf_offset = 0x140, .grf_mode_offset = 8,
  53. .grf_speed_offset = 9, .need_div_macclk = 1,
  54. };
  55. static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
  56. .grf_offset = 0x154, .grf_mode_offset = 0,
  57. .grf_speed_offset = 1, .need_div_macclk = 0,
  58. };
  59. static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
  60. .grf_offset = 0x0a4, .grf_mode_offset = 0,
  61. .grf_speed_offset = 1, .need_div_macclk = 0,
  62. };
  63. static const struct of_device_id emac_rockchip_dt_ids[] = {
  64. {
  65. .compatible = "rockchip,rk3036-emac",
  66. .data = &emac_rk3036_emac_data,
  67. },
  68. {
  69. .compatible = "rockchip,rk3066-emac",
  70. .data = &emac_rk3066_emac_data,
  71. },
  72. {
  73. .compatible = "rockchip,rk3188-emac",
  74. .data = &emac_rk3188_emac_data,
  75. },
  76. { /* Sentinel */ }
  77. };
  78. MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
  79. static int emac_rockchip_probe(struct platform_device *pdev)
  80. {
  81. struct device *dev = &pdev->dev;
  82. struct net_device *ndev;
  83. struct rockchip_priv_data *priv;
  84. const struct of_device_id *match;
  85. phy_interface_t interface;
  86. u32 data;
  87. int err;
  88. if (!pdev->dev.of_node)
  89. return -ENODEV;
  90. ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
  91. if (!ndev)
  92. return -ENOMEM;
  93. platform_set_drvdata(pdev, ndev);
  94. SET_NETDEV_DEV(ndev, dev);
  95. priv = netdev_priv(ndev);
  96. priv->emac.drv_name = DRV_NAME;
  97. priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
  98. err = of_get_phy_mode(dev->of_node, &interface);
  99. if (err)
  100. goto out_netdev;
  101. /* RK3036/RK3066/RK3188 SoCs only support RMII */
  102. if (interface != PHY_INTERFACE_MODE_RMII) {
  103. dev_err(dev, "unsupported phy interface mode %d\n", interface);
  104. err = -ENOTSUPP;
  105. goto out_netdev;
  106. }
  107. priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
  108. "rockchip,grf");
  109. if (IS_ERR(priv->grf)) {
  110. dev_err(dev, "failed to retrieve global register file (%ld)\n",
  111. PTR_ERR(priv->grf));
  112. err = PTR_ERR(priv->grf);
  113. goto out_netdev;
  114. }
  115. match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
  116. priv->soc_data = match->data;
  117. priv->emac.clk = devm_clk_get(dev, "hclk");
  118. if (IS_ERR(priv->emac.clk)) {
  119. dev_err(dev, "failed to retrieve host clock (%ld)\n",
  120. PTR_ERR(priv->emac.clk));
  121. err = PTR_ERR(priv->emac.clk);
  122. goto out_netdev;
  123. }
  124. priv->refclk = devm_clk_get(dev, "macref");
  125. if (IS_ERR(priv->refclk)) {
  126. dev_err(dev, "failed to retrieve reference clock (%ld)\n",
  127. PTR_ERR(priv->refclk));
  128. err = PTR_ERR(priv->refclk);
  129. goto out_netdev;
  130. }
  131. err = clk_prepare_enable(priv->refclk);
  132. if (err) {
  133. dev_err(dev, "failed to enable reference clock (%d)\n", err);
  134. goto out_netdev;
  135. }
  136. /* Optional regulator for PHY */
  137. priv->regulator = devm_regulator_get_optional(dev, "phy");
  138. if (IS_ERR(priv->regulator)) {
  139. if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
  140. err = -EPROBE_DEFER;
  141. goto out_clk_disable;
  142. }
  143. dev_err(dev, "no regulator found\n");
  144. priv->regulator = NULL;
  145. }
  146. if (priv->regulator) {
  147. err = regulator_enable(priv->regulator);
  148. if (err) {
  149. dev_err(dev, "failed to enable phy-supply (%d)\n", err);
  150. goto out_clk_disable;
  151. }
  152. }
  153. /* Set speed 100M */
  154. data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
  155. (1 << priv->soc_data->grf_speed_offset);
  156. /* Set RMII mode */
  157. data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
  158. (0 << priv->soc_data->grf_mode_offset);
  159. err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
  160. if (err) {
  161. dev_err(dev, "unable to apply initial settings to grf (%d)\n",
  162. err);
  163. goto out_regulator_disable;
  164. }
  165. /* RMII interface needs always a rate of 50MHz */
  166. err = clk_set_rate(priv->refclk, 50000000);
  167. if (err) {
  168. dev_err(dev,
  169. "failed to change reference clock rate (%d)\n", err);
  170. goto out_regulator_disable;
  171. }
  172. if (priv->soc_data->need_div_macclk) {
  173. priv->macclk = devm_clk_get(dev, "macclk");
  174. if (IS_ERR(priv->macclk)) {
  175. dev_err(dev, "failed to retrieve mac clock (%ld)\n",
  176. PTR_ERR(priv->macclk));
  177. err = PTR_ERR(priv->macclk);
  178. goto out_regulator_disable;
  179. }
  180. err = clk_prepare_enable(priv->macclk);
  181. if (err) {
  182. dev_err(dev, "failed to enable mac clock (%d)\n", err);
  183. goto out_regulator_disable;
  184. }
  185. /* RMII TX/RX needs always a rate of 25MHz */
  186. err = clk_set_rate(priv->macclk, 25000000);
  187. if (err) {
  188. dev_err(dev,
  189. "failed to change mac clock rate (%d)\n", err);
  190. goto out_clk_disable_macclk;
  191. }
  192. }
  193. err = arc_emac_probe(ndev, interface);
  194. if (err) {
  195. dev_err(dev, "failed to probe arc emac (%d)\n", err);
  196. goto out_clk_disable_macclk;
  197. }
  198. return 0;
  199. out_clk_disable_macclk:
  200. if (priv->soc_data->need_div_macclk)
  201. clk_disable_unprepare(priv->macclk);
  202. out_regulator_disable:
  203. if (priv->regulator)
  204. regulator_disable(priv->regulator);
  205. out_clk_disable:
  206. clk_disable_unprepare(priv->refclk);
  207. out_netdev:
  208. free_netdev(ndev);
  209. return err;
  210. }
  211. static int emac_rockchip_remove(struct platform_device *pdev)
  212. {
  213. struct net_device *ndev = platform_get_drvdata(pdev);
  214. struct rockchip_priv_data *priv = netdev_priv(ndev);
  215. int err;
  216. err = arc_emac_remove(ndev);
  217. clk_disable_unprepare(priv->refclk);
  218. if (priv->regulator)
  219. regulator_disable(priv->regulator);
  220. if (priv->soc_data->need_div_macclk)
  221. clk_disable_unprepare(priv->macclk);
  222. free_netdev(ndev);
  223. return err;
  224. }
  225. static struct platform_driver emac_rockchip_driver = {
  226. .probe = emac_rockchip_probe,
  227. .remove = emac_rockchip_remove,
  228. .driver = {
  229. .name = DRV_NAME,
  230. .of_match_table = emac_rockchip_dt_ids,
  231. },
  232. };
  233. module_platform_driver(emac_rockchip_driver);
  234. MODULE_AUTHOR("Romain Perier <[email protected]>");
  235. MODULE_DESCRIPTION("Rockchip EMAC platform driver");
  236. MODULE_LICENSE("GPL");