ring.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Applied Micro X-Gene SoC Ethernet v2 Driver
  4. *
  5. * Copyright (c) 2017, Applied Micro Circuits Corporation
  6. * Author(s): Iyappan Subramanian <[email protected]>
  7. * Keyur Chudgar <[email protected]>
  8. */
  9. #ifndef __XGENE_ENET_V2_RING_H__
  10. #define __XGENE_ENET_V2_RING_H__
  11. #define XGENE_ENET_DESC_SIZE 64
  12. #define XGENE_ENET_NUM_DESC 256
  13. #define NUM_BUFS 8
  14. #define SLOT_EMPTY 0xfff
  15. #define DMATXCTRL 0xa180
  16. #define DMATXDESCL 0xa184
  17. #define DMATXDESCH 0xa1a0
  18. #define DMATXSTATUS 0xa188
  19. #define DMARXCTRL 0xa18c
  20. #define DMARXDESCL 0xa190
  21. #define DMARXDESCH 0xa1a4
  22. #define DMARXSTATUS 0xa194
  23. #define DMAINTRMASK 0xa198
  24. #define DMAINTERRUPT 0xa19c
  25. #define D_POS 62
  26. #define D_LEN 2
  27. #define E_POS 63
  28. #define E_LEN 1
  29. #define PKT_ADDRL_POS 0
  30. #define PKT_ADDRL_LEN 32
  31. #define PKT_ADDRH_POS 32
  32. #define PKT_ADDRH_LEN 10
  33. #define PKT_SIZE_POS 32
  34. #define PKT_SIZE_LEN 12
  35. #define NEXT_DESC_ADDRL_POS 0
  36. #define NEXT_DESC_ADDRL_LEN 32
  37. #define NEXT_DESC_ADDRH_POS 48
  38. #define NEXT_DESC_ADDRH_LEN 10
  39. #define TXPKTCOUNT_POS 16
  40. #define TXPKTCOUNT_LEN 8
  41. #define RXPKTCOUNT_POS 16
  42. #define RXPKTCOUNT_LEN 8
  43. #define TX_PKT_SENT BIT(0)
  44. #define TX_BUS_ERROR BIT(3)
  45. #define RX_PKT_RCVD BIT(4)
  46. #define RX_BUS_ERROR BIT(7)
  47. #define RXSTATUS_RXPKTRCVD BIT(0)
  48. struct xge_raw_desc {
  49. __le64 m0;
  50. __le64 m1;
  51. __le64 m2;
  52. __le64 m3;
  53. __le64 m4;
  54. __le64 m5;
  55. __le64 m6;
  56. __le64 m7;
  57. };
  58. struct pkt_info {
  59. struct sk_buff *skb;
  60. dma_addr_t dma_addr;
  61. void *pkt_buf;
  62. };
  63. /* software context of a descriptor ring */
  64. struct xge_desc_ring {
  65. struct net_device *ndev;
  66. dma_addr_t dma_addr;
  67. u8 head;
  68. u8 tail;
  69. union {
  70. void *desc_addr;
  71. struct xge_raw_desc *raw_desc;
  72. };
  73. struct pkt_info (*pkt_info);
  74. };
  75. static inline u64 xge_set_desc_bits(int pos, int len, u64 val)
  76. {
  77. return (val & ((1ULL << len) - 1)) << pos;
  78. }
  79. static inline u64 xge_get_desc_bits(int pos, int len, u64 src)
  80. {
  81. return (src >> pos) & ((1ULL << len) - 1);
  82. }
  83. #define SET_BITS(field, val) \
  84. xge_set_desc_bits(field ## _POS, field ## _LEN, val)
  85. #define GET_BITS(field, src) \
  86. xge_get_desc_bits(field ## _POS, field ## _LEN, src)
  87. void xge_setup_desc(struct xge_desc_ring *ring);
  88. void xge_update_tx_desc_addr(struct xge_pdata *pdata);
  89. void xge_update_rx_desc_addr(struct xge_pdata *pdata);
  90. void xge_intr_enable(struct xge_pdata *pdata);
  91. void xge_intr_disable(struct xge_pdata *pdata);
  92. #endif /* __XGENE_ENET_V2_RING_H__ */