Эхлэл Бүгдийг харах Тусламж
Нэвтрэх
samsung-sm8650
/
android_kernel_samsung_sm8650_ksu
2
0
Салаа 0
Файлууд Асуудлууд 0 Хуулах хүсэлтүүд 0 Мэдлэгийн сан
Мод: 9e449c3f83
Салаанууд Тагууд
android_kernel_...
/
drivers
/
net
/
dsa
/
mv88e6xxx
/
global1.h

global1.h 16 KB
Түүх Анхны өгөгдөл

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364 
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
    2. 

  2. /*
    3. 

  3.  * Marvell 88E6xxx Switch Global (1) Registers support
    4. 

  4.  *
    5. 

  5.  * Copyright (c) 2008 Marvell Semiconductor
    6. 

  6.  *
    7. 

  7.  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
    8. 

  8.  *	Vivien Didelot <[email protected]>
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef _MV88E6XXX_GLOBAL1_H
    12. 

  12. #define _MV88E6XXX_GLOBAL1_H
    13. 

  13. 

  14. #include "chip.h"
    15. 

  15. 

  16. /* Offset 0x00: Switch Global Status Register */
    17. 

  17. #define MV88E6XXX_G1_STS				0x00
    18. 

  18. #define MV88E6352_G1_STS_PPU_STATE			0x8000
    19. 

  19. #define MV88E6185_G1_STS_PPU_STATE_MASK			0xc000
    20. 

  20. #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST		0x0000
    21. 

  21. #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING		0x4000
    22. 

  22. #define MV88E6185_G1_STS_PPU_STATE_DISABLED		0x8000
    23. 

  23. #define MV88E6185_G1_STS_PPU_STATE_POLLING		0xc000
    24. 

  24. #define MV88E6XXX_G1_STS_INIT_READY			0x0800
    25. 

  25. #define MV88E6393X_G1_STS_IRQ_DEVICE_2			9
    26. 

  26. #define MV88E6XXX_G1_STS_IRQ_AVB			8
    27. 

  27. #define MV88E6XXX_G1_STS_IRQ_DEVICE			7
    28. 

  28. #define MV88E6XXX_G1_STS_IRQ_STATS			6
    29. 

  29. #define MV88E6XXX_G1_STS_IRQ_VTU_PROB			5
    30. 

  30. #define MV88E6XXX_G1_STS_IRQ_VTU_DONE			4
    31. 

  31. #define MV88E6XXX_G1_STS_IRQ_ATU_PROB			3
    32. 

  32. #define MV88E6XXX_G1_STS_IRQ_ATU_DONE			2
    33. 

  33. #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE			1
    34. 

  34. #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE		0
    35. 

  35. 

  36. /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
    37. 

  37.  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
    38. 

  38.  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
    39. 

  39.  */
    40. 

  40. #define MV88E6XXX_G1_MAC_01		0x01
    41. 

  41. #define MV88E6XXX_G1_MAC_23		0x02
    42. 

  42. #define MV88E6XXX_G1_MAC_45		0x03
    43. 

  43. 

  44. /* Offset 0x01: ATU FID Register */
    45. 

  45. #define MV88E6352_G1_ATU_FID		0x01
    46. 

  46. 

  47. /* Offset 0x02: VTU FID Register */
    48. 

  48. #define MV88E6352_G1_VTU_FID		0x02
    49. 

  49. #define MV88E6352_G1_VTU_FID_VID_POLICY	0x1000
    50. 

  50. #define MV88E6352_G1_VTU_FID_MASK	0x0fff
    51. 

  51. 

  52. /* Offset 0x03: VTU SID Register */
    53. 

  53. #define MV88E6352_G1_VTU_SID		0x03
    54. 

  54. #define MV88E6352_G1_VTU_SID_MASK	0x3f
    55. 

  55. 

  56. /* Offset 0x04: Switch Global Control Register */
    57. 

  57. #define MV88E6XXX_G1_CTL1			0x04
    58. 

  58. #define MV88E6XXX_G1_CTL1_SW_RESET		0x8000
    59. 

  59. #define MV88E6XXX_G1_CTL1_PPU_ENABLE		0x4000
    60. 

  60. #define MV88E6352_G1_CTL1_DISCARD_EXCESS	0x2000
    61. 

  61. #define MV88E6185_G1_CTL1_SCHED_PRIO		0x0800
    62. 

  62. #define MV88E6185_G1_CTL1_MAX_FRAME_1632	0x0400
    63. 

  63. #define MV88E6185_G1_CTL1_RELOAD_EEPROM		0x0200
    64. 

  64. #define MV88E6393X_G1_CTL1_DEVICE2_EN		0x0200
    65. 

  65. #define MV88E6XXX_G1_CTL1_DEVICE_EN		0x0080
    66. 

  66. #define MV88E6XXX_G1_CTL1_STATS_DONE_EN		0x0040
    67. 

  67. #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN	0x0020
    68. 

  68. #define MV88E6XXX_G1_CTL1_VTU_DONE_EN		0x0010
    69. 

  69. #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN	0x0008
    70. 

  70. #define MV88E6XXX_G1_CTL1_ATU_DONE_EN		0x0004
    71. 

  71. #define MV88E6XXX_G1_CTL1_TCAM_EN		0x0002
    72. 

  72. #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN	0x0001
    73. 

  73. 

  74. /* Offset 0x05: VTU Operation Register */
    75. 

  75. #define MV88E6XXX_G1_VTU_OP			0x05
    76. 

  76. #define MV88E6XXX_G1_VTU_OP_BUSY		0x8000
    77. 

  77. #define MV88E6XXX_G1_VTU_OP_MASK		0x7000
    78. 

  78. #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL		0x1000
    79. 

  79. #define MV88E6XXX_G1_VTU_OP_NOOP		0x2000
    80. 

  80. #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE	0x3000
    81. 

  81. #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT	0x4000
    82. 

  82. #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE	0x5000
    83. 

  83. #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT	0x6000
    84. 

  84. #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION	0x7000
    85. 

  85. #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION	BIT(6)
    86. 

  86. #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION	BIT(5)
    87. 

  87. #define MV88E6XXX_G1_VTU_OP_SPID_MASK		0xf
    88. 

  88. 

  89. /* Offset 0x06: VTU VID Register */
    90. 

  90. #define MV88E6XXX_G1_VTU_VID		0x06
    91. 

  91. #define MV88E6XXX_G1_VTU_VID_MASK	0x0fff
    92. 

  92. #define MV88E6390_G1_VTU_VID_PAGE	0x2000
    93. 

  93. #define MV88E6XXX_G1_VTU_VID_VALID	0x1000
    94. 

  94. 

  95. /* Offset 0x07: VTU/STU Data Register 1
    96. 

  96.  * Offset 0x08: VTU/STU Data Register 2
    97. 

  97.  * Offset 0x09: VTU/STU Data Register 3
    98. 

  98.  */
    99. 

  99. #define MV88E6XXX_G1_VTU_DATA1				0x07
    100. 

  100. #define MV88E6XXX_G1_VTU_DATA2				0x08
    101. 

  101. #define MV88E6XXX_G1_VTU_DATA3				0x09
    102. 

  102. #define MV88E6XXX_G1_VTU_STU_DATA_MASK			0x0003
    103. 

  103. #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED	0x0000
    104. 

  104. #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED	0x0001
    105. 

  105. #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED		0x0002
    106. 

  106. #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER	0x0003
    107. 

  107. #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED	0x0000
    108. 

  108. #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING	0x0001
    109. 

  109. #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING	0x0002
    110. 

  110. #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING	0x0003
    111. 

  111. 

  112. /* Offset 0x0A: ATU Control Register */
    113. 

  113. #define MV88E6XXX_G1_ATU_CTL		0x0a
    114. 

  114. #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL	0x0008
    115. 

  115. #define MV88E6161_G1_ATU_CTL_HASH_MASK	0x0003
    116. 

  116. 

  117. /* Offset 0x0B: ATU Operation Register */
    118. 

  118. #define MV88E6XXX_G1_ATU_OP				0x0b
    119. 

  119. #define MV88E6XXX_G1_ATU_OP_BUSY			0x8000
    120. 

  120. #define MV88E6XXX_G1_ATU_OP_MASK			0x7000
    121. 

  121. #define MV88E6XXX_G1_ATU_OP_NOOP			0x0000
    122. 

  122. #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL		0x1000
    123. 

  123. #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC	0x2000
    124. 

  124. #define MV88E6XXX_G1_ATU_OP_LOAD_DB			0x3000
    125. 

  125. #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB			0x4000
    126. 

  126. #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB		0x5000
    127. 

  127. #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB	0x6000
    128. 

  128. #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION		0x7000
    129. 

  129. #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION		BIT(7)
    130. 

  130. #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION		BIT(6)
    131. 

  131. #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION		BIT(5)
    132. 

  132. #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION		BIT(4)
    133. 

  133. 

  134. /* Offset 0x0C: ATU Data Register */
    135. 

  135. #define MV88E6XXX_G1_ATU_DATA					0x0c
    136. 

  136. #define MV88E6XXX_G1_ATU_DATA_TRUNK				0x8000
    137. 

  137. #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK			0x00f0
    138. 

  138. #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK			0x3ff0
    139. 

  139. #define MV88E6XXX_G1_ATU_DATA_STATE_MASK			0x000f
    140. 

  140. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED			0x0000
    141. 

  141. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST		0x0001
    142. 

  142. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2			0x0002
    143. 

  143. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3			0x0003
    144. 

  144. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4			0x0004
    145. 

  145. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5			0x0005
    146. 

  146. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6			0x0006
    147. 

  147. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST		0x0007
    148. 

  148. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY		0x0008
    149. 

  149. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO		0x0009
    150. 

  150. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL		0x000a
    151. 

  151. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO	0x000b
    152. 

  152. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT		0x000c
    153. 

  153. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO	0x000d
    154. 

  154. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC			0x000e
    155. 

  155. #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO		0x000f
    156. 

  156. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED			0x0000
    157. 

  157. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY		0x0004
    158. 

  158. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL		0x0005
    159. 

  159. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT		0x0006
    160. 

  160. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC			0x0007
    161. 

  161. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO		0x000c
    162. 

  162. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO	0x000d
    163. 

  163. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO	0x000e
    164. 

  164. #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO		0x000f
    165. 

  165. 

  166. /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
    167. 

  167.  * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
    168. 

  168.  * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
    169. 

  169.  */
    170. 

  170. #define MV88E6XXX_G1_ATU_MAC01		0x0d
    171. 

  171. #define MV88E6XXX_G1_ATU_MAC23		0x0e
    172. 

  172. #define MV88E6XXX_G1_ATU_MAC45		0x0f
    173. 

  173. 

  174. /* Offset 0x10: IP-PRI Mapping Register 0
    175. 

  175.  * Offset 0x11: IP-PRI Mapping Register 1
    176. 

  176.  * Offset 0x12: IP-PRI Mapping Register 2
    177. 

  177.  * Offset 0x13: IP-PRI Mapping Register 3
    178. 

  178.  * Offset 0x14: IP-PRI Mapping Register 4
    179. 

  179.  * Offset 0x15: IP-PRI Mapping Register 5
    180. 

  180.  * Offset 0x16: IP-PRI Mapping Register 6
    181. 

  181.  * Offset 0x17: IP-PRI Mapping Register 7
    182. 

  182.  */
    183. 

  183. #define MV88E6XXX_G1_IP_PRI_0	0x10
    184. 

  184. #define MV88E6XXX_G1_IP_PRI_1	0x11
    185. 

  185. #define MV88E6XXX_G1_IP_PRI_2	0x12
    186. 

  186. #define MV88E6XXX_G1_IP_PRI_3	0x13
    187. 

  187. #define MV88E6XXX_G1_IP_PRI_4	0x14
    188. 

  188. #define MV88E6XXX_G1_IP_PRI_5	0x15
    189. 

  189. #define MV88E6XXX_G1_IP_PRI_6	0x16
    190. 

  190. #define MV88E6XXX_G1_IP_PRI_7	0x17
    191. 

  191. 

  192. /* Offset 0x18: IEEE-PRI Register */
    193. 

  193. #define MV88E6XXX_G1_IEEE_PRI	0x18
    194. 

  194. 

  195. /* Offset 0x19: Core Tag Type */
    196. 

  196. #define MV88E6185_G1_CORE_TAG_TYPE	0x19
    197. 

  197. 

  198. /* Offset 0x1A: Monitor Control */
    199. 

  199. #define MV88E6185_G1_MONITOR_CTL			0x1a
    200. 

  200. #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK	0xf000
    201. 

  201. #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK	0x0f00
    202. 

  202. #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK	        0x00f0
    203. 

  203. #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK	        0x00f0
    204. 

  204. #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK	0x000f
    205. 

  205. 

  206. /* Offset 0x1A: Monitor & MGMT Control Register */
    207. 

  207. #define MV88E6390_G1_MONITOR_MGMT_CTL				0x1a
    208. 

  208. #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE			0x8000
    209. 

  209. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK			0x3f00
    210. 

  210. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO	0x0000
    211. 

  211. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI	0x0100
    212. 

  212. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO	0x0200
    213. 

  213. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI	0x0300
    214. 

  214. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST		0x2000
    215. 

  215. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST		0x2100
    216. 

  216. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST		0x3000
    217. 

  217. #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI	0x00e0
    218. 

  218. #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK			0x00ff
    219. 

  219. 

  220. /* Offset 0x1C: Global Control 2 */
    221. 

  221. #define MV88E6XXX_G1_CTL2			0x1c
    222. 

  222. #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK	0xf000
    223. 

  223. #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE	0xe000
    224. 

  224. #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI	0xf000
    225. 

  225. #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK	0xc000
    226. 

  226. #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG	0x0000
    227. 

  227. #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT	0x4000
    228. 

  228. #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG	0x8000
    229. 

  229. #define MV88E6352_G1_CTL2_RMU_MODE_MASK		0x3000
    230. 

  230. #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED	0x0000
    231. 

  231. #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4	0x1000
    232. 

  232. #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5	0x2000
    233. 

  233. #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6	0x3000
    234. 

  234. #define MV88E6085_G1_CTL2_DA_CHECK		0x4000
    235. 

  235. #define MV88E6085_G1_CTL2_P10RM			0x2000
    236. 

  236. #define MV88E6085_G1_CTL2_RM_ENABLE		0x1000
    237. 

  237. #define MV88E6352_G1_CTL2_DA_CHECK		0x0800
    238. 

  238. #define MV88E6390_G1_CTL2_RMU_MODE_MASK		0x0700
    239. 

  239. #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0	0x0000
    240. 

  240. #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1	0x0100
    241. 

  241. #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9	0x0200
    242. 

  242. #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10	0x0300
    243. 

  243. #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA	0x0600
    244. 

  244. #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED	0x0700
    245. 

  245. #define MV88E6390_G1_CTL2_HIST_MODE_MASK	0x00c0
    246. 

  246. #define MV88E6390_G1_CTL2_HIST_MODE_RX		0x0040
    247. 

  247. #define MV88E6390_G1_CTL2_HIST_MODE_TX		0x0080
    248. 

  248. #define MV88E6352_G1_CTL2_CTR_MODE_MASK		0x0060
    249. 

  249. #define MV88E6390_G1_CTL2_CTR_MODE		0x0020
    250. 

  250. #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK	0x001f
    251. 

  251. 

  252. /* Offset 0x1D: Stats Operation Register */
    253. 

  253. #define MV88E6XXX_G1_STATS_OP			0x1d
    254. 

  254. #define MV88E6XXX_G1_STATS_OP_BUSY		0x8000
    255. 

  255. #define MV88E6XXX_G1_STATS_OP_NOP		0x0000
    256. 

  256. #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL		0x1000
    257. 

  257. #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT	0x2000
    258. 

  258. #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED	0x4000
    259. 

  259. #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT	0x5000
    260. 

  260. #define MV88E6XXX_G1_STATS_OP_HIST_RX		0x0400
    261. 

  261. #define MV88E6XXX_G1_STATS_OP_HIST_TX		0x0800
    262. 

  262. #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX	0x0c00
    263. 

  263. #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9	0x0200
    264. 

  264. #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10	0x0400
    265. 

  265. 

  266. /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
    267. 

  267.  * Offset 0x1F: Stats Counter Register Bytes 1 & 0
    268. 

  268.  */
    269. 

  269. #define MV88E6XXX_G1_STATS_COUNTER_32	0x1e
    270. 

  270. #define MV88E6XXX_G1_STATS_COUNTER_01	0x1f
    271. 

  271. 

  272. int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
    273. 

  273. int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
    274. 

  274. int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
    275. 

  275. 			  bit, int val);
    276. 

  276. int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
    277. 

  277. 			   u16 mask, u16 val);
    278. 

  278. 

  279. int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
    280. 

  280. 

  281. int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
    282. 

  282. int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
    283. 

  283. int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
    284. 

  284. 

  285. int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
    286. 

  286. int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
    287. 

  287. 

  288. int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu);
    289. 

  289. 

  290. int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
    291. 

  291. int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
    292. 

  292. int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
    293. 

  293. int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
    294. 

  294. int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
    295. 

  295. void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
    296. 

  296. int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
    297. 

  297. int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
    298. 

  298. 				 enum mv88e6xxx_egress_direction direction,
    299. 

  299. 				 int port);
    300. 

  300. int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
    301. 

  301. 				 enum mv88e6xxx_egress_direction direction,
    302. 

  302. 				 int port);
    303. 

  303. int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
    304. 

  304. int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
    305. 

  305. int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
    306. 

  306. 

  307. int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
    308. 

  308. 

  309. int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
    310. 

  310. int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
    311. 

  311. 

  312. int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
    313. 

  313. 

  314. int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
    315. 

  315. int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
    316. 

  316. int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
    317. 

  317. 

  318. int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
    319. 

  319. 

  320. int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
    321. 

  321. int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
    322. 

  322. 				  unsigned int msecs);
    323. 

  323. int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
    324. 

  324. 			     struct mv88e6xxx_atu_entry *entry);
    325. 

  325. int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
    326. 

  326. 			       struct mv88e6xxx_atu_entry *entry);
    327. 

  327. int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
    328. 

  328. int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
    329. 

  329. 			    bool all);
    330. 

  330. int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
    331. 

  331. void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
    332. 

  332. int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash);
    333. 

  333. int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);
    334. 

  334. 

  335. int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
    336. 

  336. 			     struct mv88e6xxx_vtu_entry *entry);
    337. 

  337. int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
    338. 

  338. 			     struct mv88e6xxx_vtu_entry *entry);
    339. 

  339. int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
    340. 

  340. 			       struct mv88e6xxx_vtu_entry *entry);
    341. 

  341. int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
    342. 

  342. 			     struct mv88e6xxx_vtu_entry *entry);
    343. 

  343. int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
    344. 

  344. 			       struct mv88e6xxx_vtu_entry *entry);
    345. 

  345. int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
    346. 

  346. 			     struct mv88e6xxx_vtu_entry *entry);
    347. 

  347. int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
    348. 

  348. 			       struct mv88e6xxx_vtu_entry *entry);
    349. 

  349. int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
    350. 

  350. int mv88e6xxx_g1_stu_getnext(struct mv88e6xxx_chip *chip,
    351. 

  351. 			     struct mv88e6xxx_stu_entry *entry);
    352. 

  352. int mv88e6352_g1_stu_getnext(struct mv88e6xxx_chip *chip,
    353. 

  353. 			     struct mv88e6xxx_stu_entry *entry);
    354. 

  354. int mv88e6352_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,
    355. 

  355. 			       struct mv88e6xxx_stu_entry *entry);
    356. 

  356. int mv88e6390_g1_stu_getnext(struct mv88e6xxx_chip *chip,
    357. 

  357. 			     struct mv88e6xxx_stu_entry *entry);
    358. 

  358. int mv88e6390_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,
    359. 

  359. 			       struct mv88e6xxx_stu_entry *entry);
    360. 

  360. int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
    361. 

  361. void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
    362. 

  362. int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);
    363. 

  363. 

  364. #endif /* _MV88E6XXX_GLOBAL1_H */
    365.