bcm_sf2_regs.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Broadcom Starfighter 2 switch register defines
  4. *
  5. * Copyright (C) 2014, Broadcom Corporation
  6. */
  7. #ifndef __BCM_SF2_REGS_H
  8. #define __BCM_SF2_REGS_H
  9. /* Register set relative to 'REG' */
  10. enum bcm_sf2_reg_offs {
  11. REG_SWITCH_CNTRL = 0,
  12. REG_SWITCH_STATUS,
  13. REG_DIR_DATA_WRITE,
  14. REG_DIR_DATA_READ,
  15. REG_SWITCH_REVISION,
  16. REG_PHY_REVISION,
  17. REG_SPHY_CNTRL,
  18. REG_CROSSBAR,
  19. REG_RGMII_0_CNTRL,
  20. REG_RGMII_1_CNTRL,
  21. REG_RGMII_2_CNTRL,
  22. REG_RGMII_11_CNTRL,
  23. REG_LED_0_CNTRL,
  24. REG_LED_1_CNTRL,
  25. REG_LED_2_CNTRL,
  26. REG_LED_3_CNTRL,
  27. REG_LED_4_CNTRL,
  28. REG_LED_5_CNTRL,
  29. REG_LED_AGGREGATE_CTRL,
  30. REG_SWITCH_REG_MAX,
  31. };
  32. /* Relative to REG_SWITCH_CNTRL */
  33. #define MDIO_MASTER_SEL (1 << 0)
  34. /* Relative to REG_SWITCH_REVISION */
  35. #define SF2_REV_MASK 0xffff
  36. #define SWITCH_TOP_REV_SHIFT 16
  37. #define SWITCH_TOP_REV_MASK 0xffff
  38. /* Relative to REG_PHY_REVISION */
  39. #define PHY_REVISION_MASK 0xffff
  40. /* Relative to REG_SPHY_CNTRL */
  41. #define IDDQ_BIAS (1 << 0)
  42. #define EXT_PWR_DOWN (1 << 1)
  43. #define FORCE_DLL_EN (1 << 2)
  44. #define IDDQ_GLOBAL_PWR (1 << 3)
  45. #define CK25_DIS (1 << 4)
  46. #define PHY_RESET (1 << 5)
  47. #define PHY_PHYAD_SHIFT 8
  48. #define PHY_PHYAD_MASK 0x1F
  49. /* Relative to REG_CROSSBAR */
  50. #define CROSSBAR_BCM4908_INT_P7 0
  51. #define CROSSBAR_BCM4908_INT_RUNNER 1
  52. #define CROSSBAR_BCM4908_EXT_SERDES 0
  53. #define CROSSBAR_BCM4908_EXT_GPHY4 1
  54. #define CROSSBAR_BCM4908_EXT_RGMII 2
  55. /* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */
  56. #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
  57. #define LED_CNTRL_M10_ENCODE_SHIFT 2
  58. #define LED_CNTRL_M100_ENCODE_SHIFT 4
  59. #define LED_CNTRL_M1000_ENCODE_SHIFT 6
  60. #define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8
  61. #define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10
  62. #define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12
  63. #define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14
  64. #define LED_CNTRL_RX_DV_EN (1 << 16)
  65. #define LED_CNTRL_TX_EN_EN (1 << 17)
  66. #define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18
  67. #define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20
  68. #define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22
  69. #define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24)
  70. #define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25)
  71. #define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26)
  72. #define LED_CNTRL_ACT_LED_POL_SEL (1 << 27)
  73. #define LED_CNTRL_MASK 0x3
  74. /* Register relative to REG_LED_*_CNTRL (BCM4908) */
  75. #define REG_LED_CTRL 0x0
  76. #define LED_CTRL_RX_ACT_EN 0x00000001
  77. #define LED_CTRL_TX_ACT_EN 0x00000002
  78. #define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004
  79. #define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008
  80. #define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010
  81. #define LED_CTRL_ACT_LED_ACT_SEL 0x00000020
  82. #define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040
  83. #define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080
  84. #define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100
  85. #define LED_CTRL_ACT_LED_POL_SEL 0x00000200
  86. #define LED_CTRL_LED_SPD_OVRD 0x00001c00
  87. #define LED_CTRL_LNK_STATUS_OVRD 0x00002000
  88. #define LED_CTRL_SPD_OVRD_EN 0x00004000
  89. #define LED_CTRL_LNK_OVRD_EN 0x00008000
  90. /* Register relative to REG_LED_*_CNTRL (BCM4908) */
  91. #define REG_LED_LINK_SPEED_ENC_SEL 0x4
  92. #define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0
  93. #define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3
  94. #define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6
  95. #define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9
  96. #define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12
  97. #define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15
  98. #define LED_LINK_SPEED_ENC_SEL_MASK 0x7
  99. /* Register relative to REG_LED_*_CNTRL (BCM4908) */
  100. #define REG_LED_LINK_SPEED_ENC 0x8
  101. #define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0
  102. #define LED_LINK_SPEED_ENC_M10_SHIFT 3
  103. #define LED_LINK_SPEED_ENC_M100_SHIFT 6
  104. #define LED_LINK_SPEED_ENC_M1000_SHIFT 9
  105. #define LED_LINK_SPEED_ENC_M2500_SHIFT 12
  106. #define LED_LINK_SPEED_ENC_M10G_SHIFT 15
  107. #define LED_LINK_SPEED_ENC_MASK 0x7
  108. /* Relative to REG_RGMII_CNTRL */
  109. #define RGMII_MODE_EN (1 << 0)
  110. #define ID_MODE_DIS (1 << 1)
  111. #define PORT_MODE_SHIFT 2
  112. #define INT_EPHY (0 << PORT_MODE_SHIFT)
  113. #define INT_GPHY (1 << PORT_MODE_SHIFT)
  114. #define EXT_EPHY (2 << PORT_MODE_SHIFT)
  115. #define EXT_GPHY (3 << PORT_MODE_SHIFT)
  116. #define EXT_REVMII (4 << PORT_MODE_SHIFT)
  117. #define PORT_MODE_MASK 0x7
  118. #define RVMII_REF_SEL (1 << 5)
  119. #define RX_PAUSE_EN (1 << 6)
  120. #define TX_PAUSE_EN (1 << 7)
  121. #define TX_CLK_STOP_EN (1 << 8)
  122. #define LPI_COUNT_SHIFT 9
  123. #define LPI_COUNT_MASK 0x3F
  124. /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
  125. #define INTRL2_CPU_STATUS 0x00
  126. #define INTRL2_CPU_SET 0x04
  127. #define INTRL2_CPU_CLEAR 0x08
  128. #define INTRL2_CPU_MASK_STATUS 0x0c
  129. #define INTRL2_CPU_MASK_SET 0x10
  130. #define INTRL2_CPU_MASK_CLEAR 0x14
  131. /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
  132. #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
  133. #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
  134. #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
  135. #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
  136. #define P_GPHY_IRQ(x) (1 << (4 + (x)))
  137. #define P_NUM_IRQ 5
  138. #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
  139. P_LINK_DOWN_IRQ((x)) | \
  140. P_ENERGY_ON_IRQ((x)) | \
  141. P_ENERGY_OFF_IRQ((x)) | \
  142. P_GPHY_IRQ((x)))
  143. /* INTRL2_0 interrupt sources */
  144. #define P0_IRQ_OFF 0
  145. #define MEM_DOUBLE_IRQ (1 << 5)
  146. #define EEE_LPI_IRQ (1 << 6)
  147. #define P5_CPU_WAKE_IRQ (1 << 7)
  148. #define P8_CPU_WAKE_IRQ (1 << 8)
  149. #define P7_CPU_WAKE_IRQ (1 << 9)
  150. #define IEEE1588_IRQ (1 << 10)
  151. #define MDIO_ERR_IRQ (1 << 11)
  152. #define MDIO_DONE_IRQ (1 << 12)
  153. #define GISB_ERR_IRQ (1 << 13)
  154. #define UBUS_ERR_IRQ (1 << 14)
  155. #define FAILOVER_ON_IRQ (1 << 15)
  156. #define FAILOVER_OFF_IRQ (1 << 16)
  157. #define TCAM_SOFT_ERR_IRQ (1 << 17)
  158. /* INTRL2_1 interrupt sources */
  159. #define P7_IRQ_OFF 0
  160. #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
  161. /* Register set relative to 'ACB' */
  162. #define ACB_CONTROL 0x00
  163. #define ACB_EN (1 << 0)
  164. #define ACB_ALGORITHM (1 << 1)
  165. #define ACB_FLUSH_SHIFT 2
  166. #define ACB_FLUSH_MASK 0x3
  167. #define ACB_QUEUE_0_CFG 0x08
  168. #define XOFF_THRESHOLD_MASK 0x7ff
  169. #define XON_EN (1 << 11)
  170. #define TOTAL_XOFF_THRESHOLD_SHIFT 12
  171. #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff
  172. #define TOTAL_XOFF_EN (1 << 23)
  173. #define TOTAL_XON_EN (1 << 24)
  174. #define PKTLEN_SHIFT 25
  175. #define PKTLEN_MASK 0x3f
  176. #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4))
  177. /* Register set relative to 'CORE' */
  178. #define CORE_G_PCTL_PORT0 0x00000
  179. #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
  180. #define CORE_IMP_CTL 0x00020
  181. #define RX_DIS (1 << 0)
  182. #define TX_DIS (1 << 1)
  183. #define RX_BCST_EN (1 << 2)
  184. #define RX_MCST_EN (1 << 3)
  185. #define RX_UCST_EN (1 << 4)
  186. #define CORE_SWMODE 0x0002c
  187. #define SW_FWDG_MODE (1 << 0)
  188. #define SW_FWDG_EN (1 << 1)
  189. #define RTRY_LMT_DIS (1 << 2)
  190. #define CORE_STS_OVERRIDE_IMP 0x00038
  191. #define GMII_SPEED_UP_2G (1 << 6)
  192. #define MII_SW_OR (1 << 7)
  193. /* Alternate layout for e.g: 7278 */
  194. #define CORE_STS_OVERRIDE_IMP2 0x39040
  195. #define CORE_NEW_CTRL 0x00084
  196. #define IP_MC (1 << 0)
  197. #define OUTRANGEERR_DISCARD (1 << 1)
  198. #define INRANGEERR_DISCARD (1 << 2)
  199. #define CABLE_DIAG_LEN (1 << 3)
  200. #define OVERRIDE_AUTO_PD_WAR (1 << 4)
  201. #define EN_AUTO_PD_WAR (1 << 5)
  202. #define UC_FWD_EN (1 << 6)
  203. #define MC_FWD_EN (1 << 7)
  204. #define CORE_SWITCH_CTRL 0x00088
  205. #define MII_DUMB_FWDG_EN (1 << 6)
  206. #define CORE_DIS_LEARN 0x000f0
  207. #define CORE_SFT_LRN_CTRL 0x000f8
  208. #define SW_LEARN_CNTL(x) (1 << (x))
  209. #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
  210. #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
  211. #define LINK_STS (1 << 0)
  212. #define DUPLX_MODE (1 << 1)
  213. #define SPEED_SHIFT 2
  214. #define SPEED_MASK 0x3
  215. #define RXFLOW_CNTL (1 << 4)
  216. #define TXFLOW_CNTL (1 << 5)
  217. #define SW_OVERRIDE (1 << 6)
  218. #define CORE_WATCHDOG_CTRL 0x001e4
  219. #define SOFTWARE_RESET (1 << 7)
  220. #define EN_CHIP_RST (1 << 6)
  221. #define EN_SW_RESET (1 << 4)
  222. #define CORE_FAST_AGE_CTRL 0x00220
  223. #define EN_FAST_AGE_STATIC (1 << 0)
  224. #define EN_AGE_DYNAMIC (1 << 1)
  225. #define EN_AGE_PORT (1 << 2)
  226. #define EN_AGE_VLAN (1 << 3)
  227. #define EN_AGE_SPT (1 << 4)
  228. #define EN_AGE_MCAST (1 << 5)
  229. #define FAST_AGE_STR_DONE (1 << 7)
  230. #define CORE_FAST_AGE_PORT 0x00224
  231. #define AGE_PORT_MASK 0xf
  232. #define CORE_FAST_AGE_VID 0x00228
  233. #define AGE_VID_MASK 0x3fff
  234. #define CORE_LNKSTS 0x00400
  235. #define LNK_STS_MASK 0x1ff
  236. #define CORE_SPDSTS 0x00410
  237. #define SPDSTS_10 0
  238. #define SPDSTS_100 1
  239. #define SPDSTS_1000 2
  240. #define SPDSTS_SHIFT 2
  241. #define SPDSTS_MASK 0x3
  242. #define CORE_DUPSTS 0x00420
  243. #define CORE_DUPSTS_MASK 0x1ff
  244. #define CORE_PAUSESTS 0x00428
  245. #define PAUSESTS_TX_PAUSE_SHIFT 9
  246. #define CORE_GMNCFGCFG 0x0800
  247. #define RST_MIB_CNT (1 << 0)
  248. #define RXBPDU_EN (1 << 1)
  249. #define CORE_IMP0_PRT_ID 0x0804
  250. #define CORE_RST_MIB_CNT_EN 0x0950
  251. #define CORE_ARLA_VTBL_RWCTRL 0x1600
  252. #define ARLA_VTBL_CMD_WRITE 0
  253. #define ARLA_VTBL_CMD_READ 1
  254. #define ARLA_VTBL_CMD_CLEAR 2
  255. #define ARLA_VTBL_STDN (1 << 7)
  256. #define CORE_ARLA_VTBL_ADDR 0x1604
  257. #define VTBL_ADDR_INDEX_MASK 0xfff
  258. #define CORE_ARLA_VTBL_ENTRY 0x160c
  259. #define FWD_MAP_MASK 0x1ff
  260. #define UNTAG_MAP_MASK 0x1ff
  261. #define UNTAG_MAP_SHIFT 9
  262. #define MSTP_INDEX_MASK 0x7
  263. #define MSTP_INDEX_SHIFT 18
  264. #define FWD_MODE (1 << 21)
  265. #define CORE_MEM_PSM_VDD_CTRL 0x2380
  266. #define P_TXQ_PSM_VDD_SHIFT 2
  267. #define P_TXQ_PSM_VDD_MASK 0x3
  268. #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
  269. ((x) * P_TXQ_PSM_VDD_SHIFT))
  270. #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10))
  271. #define PRT_TO_QID_MASK 0x3
  272. #define PRT_TO_QID_SHIFT 3
  273. #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
  274. #define PORT_VLAN_CTRL_MASK 0x1ff
  275. #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80
  276. #define TXQ_PAUSE_THD_MASK 0x7ff
  277. #define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \
  278. (x) * 0x8)
  279. #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
  280. #define CFI_SHIFT 12
  281. #define PRI_SHIFT 13
  282. #define PRI_MASK 0x7
  283. #define CORE_JOIN_ALL_VLAN_EN 0xd140
  284. #define CORE_CFP_ACC 0x28000
  285. #define OP_STR_DONE (1 << 0)
  286. #define OP_SEL_SHIFT 1
  287. #define OP_SEL_READ (1 << OP_SEL_SHIFT)
  288. #define OP_SEL_WRITE (2 << OP_SEL_SHIFT)
  289. #define OP_SEL_SEARCH (4 << OP_SEL_SHIFT)
  290. #define OP_SEL_MASK (7 << OP_SEL_SHIFT)
  291. #define CFP_RAM_CLEAR (1 << 4)
  292. #define RAM_SEL_SHIFT 10
  293. #define TCAM_SEL (1 << RAM_SEL_SHIFT)
  294. #define ACT_POL_RAM (2 << RAM_SEL_SHIFT)
  295. #define RATE_METER_RAM (4 << RAM_SEL_SHIFT)
  296. #define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT)
  297. #define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT)
  298. #define RED_STAT_RAM (24 << RAM_SEL_SHIFT)
  299. #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT)
  300. #define TCAM_RESET (1 << 15)
  301. #define XCESS_ADDR_SHIFT 16
  302. #define XCESS_ADDR_MASK 0xff
  303. #define SEARCH_STS (1 << 27)
  304. #define RD_STS_SHIFT 28
  305. #define RD_STS_TCAM (1 << RD_STS_SHIFT)
  306. #define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT)
  307. #define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT)
  308. #define RD_STS_STAT_RAM (8 << RD_STS_SHIFT)
  309. #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010
  310. #define CORE_CFP_DATA_PORT_0 0x28040
  311. #define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \
  312. (x) * 0x10)
  313. /* UDF_DATA7 */
  314. #define L3_FRAMING_SHIFT 24
  315. #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT)
  316. #define IPTOS_SHIFT 16
  317. #define IPTOS_MASK 0xff
  318. #define IPPROTO_SHIFT 8
  319. #define IPPROTO_MASK (0xff << IPPROTO_SHIFT)
  320. #define IP_FRAG_SHIFT 7
  321. #define IP_FRAG (1 << IP_FRAG_SHIFT)
  322. /* UDF_DATA0 */
  323. #define SLICE_VALID 3
  324. #define SLICE_NUM_SHIFT 2
  325. #define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT)
  326. #define SLICE_NUM_MASK 0x3
  327. #define CORE_CFP_MASK_PORT_0 0x280c0
  328. #define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \
  329. (x) * 0x10)
  330. #define CORE_ACT_POL_DATA0 0x28140
  331. #define VLAN_BYP (1 << 0)
  332. #define EAP_BYP (1 << 1)
  333. #define STP_BYP (1 << 2)
  334. #define REASON_CODE_SHIFT 3
  335. #define REASON_CODE_MASK 0x3f
  336. #define LOOP_BK_EN (1 << 9)
  337. #define NEW_TC_SHIFT 10
  338. #define NEW_TC_MASK 0x7
  339. #define CHANGE_TC (1 << 13)
  340. #define DST_MAP_IB_SHIFT 14
  341. #define DST_MAP_IB_MASK 0x1ff
  342. #define CHANGE_FWRD_MAP_IB_SHIFT 24
  343. #define CHANGE_FWRD_MAP_IB_MASK 0x3
  344. #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT)
  345. #define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT)
  346. #define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT)
  347. #define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT)
  348. #define NEW_DSCP_IB_SHIFT 26
  349. #define NEW_DSCP_IB_MASK 0x3f
  350. #define CORE_ACT_POL_DATA1 0x28150
  351. #define CHANGE_DSCP_IB (1 << 0)
  352. #define DST_MAP_OB_SHIFT 1
  353. #define DST_MAP_OB_MASK 0x3ff
  354. #define CHANGE_FWRD_MAP_OB_SHIT 11
  355. #define CHANGE_FWRD_MAP_OB_MASK 0x3
  356. #define NEW_DSCP_OB_SHIFT 13
  357. #define NEW_DSCP_OB_MASK 0x3f
  358. #define CHANGE_DSCP_OB (1 << 19)
  359. #define CHAIN_ID_SHIFT 20
  360. #define CHAIN_ID_MASK 0xff
  361. #define CHANGE_COLOR (1 << 28)
  362. #define NEW_COLOR_SHIFT 29
  363. #define NEW_COLOR_MASK 0x3
  364. #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT)
  365. #define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT)
  366. #define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT)
  367. #define RED_DEFAULT (1 << 31)
  368. #define CORE_ACT_POL_DATA2 0x28160
  369. #define MAC_LIMIT_BYPASS (1 << 0)
  370. #define CHANGE_TC_O (1 << 1)
  371. #define NEW_TC_O_SHIFT 2
  372. #define NEW_TC_O_MASK 0x7
  373. #define SPCP_RMK_DISABLE (1 << 5)
  374. #define CPCP_RMK_DISABLE (1 << 6)
  375. #define DEI_RMK_DISABLE (1 << 7)
  376. #define CORE_RATE_METER0 0x28180
  377. #define COLOR_MODE (1 << 0)
  378. #define POLICER_ACTION (1 << 1)
  379. #define COUPLING_FLAG (1 << 2)
  380. #define POLICER_MODE_SHIFT 3
  381. #define POLICER_MODE_MASK 0x3
  382. #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT)
  383. #define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT)
  384. #define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT)
  385. #define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT)
  386. #define CORE_RATE_METER1 0x28190
  387. #define EIR_TK_BKT_MASK 0x7fffff
  388. #define CORE_RATE_METER2 0x281a0
  389. #define EIR_BKT_SIZE_MASK 0xfffff
  390. #define CORE_RATE_METER3 0x281b0
  391. #define EIR_REF_CNT_MASK 0x7ffff
  392. #define CORE_RATE_METER4 0x281c0
  393. #define CIR_TK_BKT_MASK 0x7fffff
  394. #define CORE_RATE_METER5 0x281d0
  395. #define CIR_BKT_SIZE_MASK 0xfffff
  396. #define CORE_RATE_METER6 0x281e0
  397. #define CIR_REF_CNT_MASK 0x7ffff
  398. #define CORE_STAT_GREEN_CNTR 0x28200
  399. #define CORE_STAT_YELLOW_CNTR 0x28210
  400. #define CORE_STAT_RED_CNTR 0x28220
  401. #define CORE_CFP_CTL_REG 0x28400
  402. #define CFP_EN_MAP_MASK 0x1ff
  403. /* IPv4 slices, 3 of them */
  404. #define CORE_UDF_0_A_0_8_PORT_0 0x28440
  405. #define CFG_UDF_OFFSET_MASK 0x1f
  406. #define CFG_UDF_OFFSET_BASE_SHIFT 5
  407. #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT)
  408. #define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT)
  409. #define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT)
  410. /* IPv6 slices */
  411. #define CORE_UDF_0_B_0_8_PORT_0 0x28500
  412. /* IPv6 chained slices */
  413. #define CORE_UDF_0_D_0_11_PORT_0 0x28680
  414. /* Number of slices for IPv4, IPv6 and non-IP */
  415. #define UDF_NUM_SLICES 4
  416. #define UDFS_PER_SLICE 9
  417. /* Spacing between different slices */
  418. #define UDF_SLICE_OFFSET 0x40
  419. #define CFP_NUM_RULES 256
  420. /* Number of egress queues per port */
  421. #define SF2_NUM_EGRESS_QUEUES 8
  422. #endif /* __BCM_SF2_REGS_H */