mcp251x.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
  3. *
  4. * MCP2510 support and bug fixes by Christian Pellegrin
  5. * <[email protected]>
  6. *
  7. * Copyright 2009 Christian Pellegrin EVOL S.r.l.
  8. *
  9. * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
  10. * Written under contract by:
  11. * Chris Elston, Katalix Systems, Ltd.
  12. *
  13. * Based on Microchip MCP251x CAN controller driver written by
  14. * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
  15. *
  16. * Based on CAN bus driver for the CCAN controller written by
  17. * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
  18. * - Simon Kallweit, intefo AG
  19. * Copyright 2007
  20. */
  21. #include <linux/bitfield.h>
  22. #include <linux/can/core.h>
  23. #include <linux/can/dev.h>
  24. #include <linux/clk.h>
  25. #include <linux/completion.h>
  26. #include <linux/delay.h>
  27. #include <linux/device.h>
  28. #include <linux/ethtool.h>
  29. #include <linux/freezer.h>
  30. #include <linux/gpio.h>
  31. #include <linux/gpio/driver.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/io.h>
  34. #include <linux/iopoll.h>
  35. #include <linux/kernel.h>
  36. #include <linux/module.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/property.h>
  40. #include <linux/regulator/consumer.h>
  41. #include <linux/slab.h>
  42. #include <linux/spi/spi.h>
  43. #include <linux/uaccess.h>
  44. /* SPI interface instruction set */
  45. #define INSTRUCTION_WRITE 0x02
  46. #define INSTRUCTION_READ 0x03
  47. #define INSTRUCTION_BIT_MODIFY 0x05
  48. #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
  49. #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
  50. #define INSTRUCTION_RESET 0xC0
  51. #define RTS_TXB0 0x01
  52. #define RTS_TXB1 0x02
  53. #define RTS_TXB2 0x04
  54. #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
  55. /* MPC251x registers */
  56. #define BFPCTRL 0x0c
  57. # define BFPCTRL_B0BFM BIT(0)
  58. # define BFPCTRL_B1BFM BIT(1)
  59. # define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n))
  60. # define BFPCTRL_BFM_MASK GENMASK(1, 0)
  61. # define BFPCTRL_B0BFE BIT(2)
  62. # define BFPCTRL_B1BFE BIT(3)
  63. # define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n))
  64. # define BFPCTRL_BFE_MASK GENMASK(3, 2)
  65. # define BFPCTRL_B0BFS BIT(4)
  66. # define BFPCTRL_B1BFS BIT(5)
  67. # define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n))
  68. # define BFPCTRL_BFS_MASK GENMASK(5, 4)
  69. #define TXRTSCTRL 0x0d
  70. # define TXRTSCTRL_B0RTSM BIT(0)
  71. # define TXRTSCTRL_B1RTSM BIT(1)
  72. # define TXRTSCTRL_B2RTSM BIT(2)
  73. # define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n))
  74. # define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)
  75. # define TXRTSCTRL_B0RTS BIT(3)
  76. # define TXRTSCTRL_B1RTS BIT(4)
  77. # define TXRTSCTRL_B2RTS BIT(5)
  78. # define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n))
  79. # define TXRTSCTRL_RTS_MASK GENMASK(5, 3)
  80. #define CANSTAT 0x0e
  81. #define CANCTRL 0x0f
  82. # define CANCTRL_REQOP_MASK 0xe0
  83. # define CANCTRL_REQOP_CONF 0x80
  84. # define CANCTRL_REQOP_LISTEN_ONLY 0x60
  85. # define CANCTRL_REQOP_LOOPBACK 0x40
  86. # define CANCTRL_REQOP_SLEEP 0x20
  87. # define CANCTRL_REQOP_NORMAL 0x00
  88. # define CANCTRL_OSM 0x08
  89. # define CANCTRL_ABAT 0x10
  90. #define TEC 0x1c
  91. #define REC 0x1d
  92. #define CNF1 0x2a
  93. # define CNF1_SJW_SHIFT 6
  94. #define CNF2 0x29
  95. # define CNF2_BTLMODE 0x80
  96. # define CNF2_SAM 0x40
  97. # define CNF2_PS1_SHIFT 3
  98. #define CNF3 0x28
  99. # define CNF3_SOF 0x08
  100. # define CNF3_WAKFIL 0x04
  101. # define CNF3_PHSEG2_MASK 0x07
  102. #define CANINTE 0x2b
  103. # define CANINTE_MERRE 0x80
  104. # define CANINTE_WAKIE 0x40
  105. # define CANINTE_ERRIE 0x20
  106. # define CANINTE_TX2IE 0x10
  107. # define CANINTE_TX1IE 0x08
  108. # define CANINTE_TX0IE 0x04
  109. # define CANINTE_RX1IE 0x02
  110. # define CANINTE_RX0IE 0x01
  111. #define CANINTF 0x2c
  112. # define CANINTF_MERRF 0x80
  113. # define CANINTF_WAKIF 0x40
  114. # define CANINTF_ERRIF 0x20
  115. # define CANINTF_TX2IF 0x10
  116. # define CANINTF_TX1IF 0x08
  117. # define CANINTF_TX0IF 0x04
  118. # define CANINTF_RX1IF 0x02
  119. # define CANINTF_RX0IF 0x01
  120. # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
  121. # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
  122. # define CANINTF_ERR (CANINTF_ERRIF)
  123. #define EFLG 0x2d
  124. # define EFLG_EWARN 0x01
  125. # define EFLG_RXWAR 0x02
  126. # define EFLG_TXWAR 0x04
  127. # define EFLG_RXEP 0x08
  128. # define EFLG_TXEP 0x10
  129. # define EFLG_TXBO 0x20
  130. # define EFLG_RX0OVR 0x40
  131. # define EFLG_RX1OVR 0x80
  132. #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
  133. # define TXBCTRL_ABTF 0x40
  134. # define TXBCTRL_MLOA 0x20
  135. # define TXBCTRL_TXERR 0x10
  136. # define TXBCTRL_TXREQ 0x08
  137. #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
  138. # define SIDH_SHIFT 3
  139. #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
  140. # define SIDL_SID_MASK 7
  141. # define SIDL_SID_SHIFT 5
  142. # define SIDL_EXIDE_SHIFT 3
  143. # define SIDL_EID_SHIFT 16
  144. # define SIDL_EID_MASK 3
  145. #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
  146. #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
  147. #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
  148. # define DLC_RTR_SHIFT 6
  149. #define TXBCTRL_OFF 0
  150. #define TXBSIDH_OFF 1
  151. #define TXBSIDL_OFF 2
  152. #define TXBEID8_OFF 3
  153. #define TXBEID0_OFF 4
  154. #define TXBDLC_OFF 5
  155. #define TXBDAT_OFF 6
  156. #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
  157. # define RXBCTRL_BUKT 0x04
  158. # define RXBCTRL_RXM0 0x20
  159. # define RXBCTRL_RXM1 0x40
  160. #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
  161. # define RXBSIDH_SHIFT 3
  162. #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
  163. # define RXBSIDL_IDE 0x08
  164. # define RXBSIDL_SRR 0x10
  165. # define RXBSIDL_EID 3
  166. # define RXBSIDL_SHIFT 5
  167. #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
  168. #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
  169. #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
  170. # define RXBDLC_LEN_MASK 0x0f
  171. # define RXBDLC_RTR 0x40
  172. #define RXBCTRL_OFF 0
  173. #define RXBSIDH_OFF 1
  174. #define RXBSIDL_OFF 2
  175. #define RXBEID8_OFF 3
  176. #define RXBEID0_OFF 4
  177. #define RXBDLC_OFF 5
  178. #define RXBDAT_OFF 6
  179. #define RXFSID(n) ((n < 3) ? 0 : 4)
  180. #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
  181. #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
  182. #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
  183. #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
  184. #define RXMSIDH(n) ((n) * 4 + 0x20)
  185. #define RXMSIDL(n) ((n) * 4 + 0x21)
  186. #define RXMEID8(n) ((n) * 4 + 0x22)
  187. #define RXMEID0(n) ((n) * 4 + 0x23)
  188. #define GET_BYTE(val, byte) \
  189. (((val) >> ((byte) * 8)) & 0xff)
  190. #define SET_BYTE(val, byte) \
  191. (((val) & 0xff) << ((byte) * 8))
  192. /* Buffer size required for the largest SPI transfer (i.e., reading a
  193. * frame)
  194. */
  195. #define CAN_FRAME_MAX_DATA_LEN 8
  196. #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
  197. #define CAN_FRAME_MAX_BITS 128
  198. #define TX_ECHO_SKB_MAX 1
  199. #define MCP251X_OST_DELAY_MS (5)
  200. #define DEVICE_NAME "mcp251x"
  201. static const struct can_bittiming_const mcp251x_bittiming_const = {
  202. .name = DEVICE_NAME,
  203. .tseg1_min = 3,
  204. .tseg1_max = 16,
  205. .tseg2_min = 2,
  206. .tseg2_max = 8,
  207. .sjw_max = 4,
  208. .brp_min = 1,
  209. .brp_max = 64,
  210. .brp_inc = 1,
  211. };
  212. enum mcp251x_model {
  213. CAN_MCP251X_MCP2510 = 0x2510,
  214. CAN_MCP251X_MCP2515 = 0x2515,
  215. CAN_MCP251X_MCP25625 = 0x25625,
  216. };
  217. struct mcp251x_priv {
  218. struct can_priv can;
  219. struct net_device *net;
  220. struct spi_device *spi;
  221. enum mcp251x_model model;
  222. struct mutex mcp_lock; /* SPI device lock */
  223. u8 *spi_tx_buf;
  224. u8 *spi_rx_buf;
  225. struct sk_buff *tx_skb;
  226. struct workqueue_struct *wq;
  227. struct work_struct tx_work;
  228. struct work_struct restart_work;
  229. int force_quit;
  230. int after_suspend;
  231. #define AFTER_SUSPEND_UP 1
  232. #define AFTER_SUSPEND_DOWN 2
  233. #define AFTER_SUSPEND_POWER 4
  234. #define AFTER_SUSPEND_RESTART 8
  235. int restart_tx;
  236. bool tx_busy;
  237. struct regulator *power;
  238. struct regulator *transceiver;
  239. struct clk *clk;
  240. #ifdef CONFIG_GPIOLIB
  241. struct gpio_chip gpio;
  242. u8 reg_bfpctrl;
  243. #endif
  244. };
  245. #define MCP251X_IS(_model) \
  246. static inline int mcp251x_is_##_model(struct spi_device *spi) \
  247. { \
  248. struct mcp251x_priv *priv = spi_get_drvdata(spi); \
  249. return priv->model == CAN_MCP251X_MCP##_model; \
  250. }
  251. MCP251X_IS(2510);
  252. static void mcp251x_clean(struct net_device *net)
  253. {
  254. struct mcp251x_priv *priv = netdev_priv(net);
  255. if (priv->tx_skb || priv->tx_busy)
  256. net->stats.tx_errors++;
  257. dev_kfree_skb(priv->tx_skb);
  258. if (priv->tx_busy)
  259. can_free_echo_skb(priv->net, 0, NULL);
  260. priv->tx_skb = NULL;
  261. priv->tx_busy = false;
  262. }
  263. /* Note about handling of error return of mcp251x_spi_trans: accessing
  264. * registers via SPI is not really different conceptually than using
  265. * normal I/O assembler instructions, although it's much more
  266. * complicated from a practical POV. So it's not advisable to always
  267. * check the return value of this function. Imagine that every
  268. * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
  269. * error();", it would be a great mess (well there are some situation
  270. * when exception handling C++ like could be useful after all). So we
  271. * just check that transfers are OK at the beginning of our
  272. * conversation with the chip and to avoid doing really nasty things
  273. * (like injecting bogus packets in the network stack).
  274. */
  275. static int mcp251x_spi_trans(struct spi_device *spi, int len)
  276. {
  277. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  278. struct spi_transfer t = {
  279. .tx_buf = priv->spi_tx_buf,
  280. .rx_buf = priv->spi_rx_buf,
  281. .len = len,
  282. .cs_change = 0,
  283. };
  284. struct spi_message m;
  285. int ret;
  286. spi_message_init(&m);
  287. spi_message_add_tail(&t, &m);
  288. ret = spi_sync(spi, &m);
  289. if (ret)
  290. dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
  291. return ret;
  292. }
  293. static int mcp251x_spi_write(struct spi_device *spi, int len)
  294. {
  295. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  296. int ret;
  297. ret = spi_write(spi, priv->spi_tx_buf, len);
  298. if (ret)
  299. dev_err(&spi->dev, "spi write failed: ret = %d\n", ret);
  300. return ret;
  301. }
  302. static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
  303. {
  304. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  305. u8 val = 0;
  306. priv->spi_tx_buf[0] = INSTRUCTION_READ;
  307. priv->spi_tx_buf[1] = reg;
  308. if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
  309. spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
  310. } else {
  311. mcp251x_spi_trans(spi, 3);
  312. val = priv->spi_rx_buf[2];
  313. }
  314. return val;
  315. }
  316. static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
  317. {
  318. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  319. priv->spi_tx_buf[0] = INSTRUCTION_READ;
  320. priv->spi_tx_buf[1] = reg;
  321. if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
  322. u8 val[2] = { 0 };
  323. spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
  324. *v1 = val[0];
  325. *v2 = val[1];
  326. } else {
  327. mcp251x_spi_trans(spi, 4);
  328. *v1 = priv->spi_rx_buf[2];
  329. *v2 = priv->spi_rx_buf[3];
  330. }
  331. }
  332. static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
  333. {
  334. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  335. priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
  336. priv->spi_tx_buf[1] = reg;
  337. priv->spi_tx_buf[2] = val;
  338. mcp251x_spi_write(spi, 3);
  339. }
  340. static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
  341. {
  342. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  343. priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
  344. priv->spi_tx_buf[1] = reg;
  345. priv->spi_tx_buf[2] = v1;
  346. priv->spi_tx_buf[3] = v2;
  347. mcp251x_spi_write(spi, 4);
  348. }
  349. static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
  350. u8 mask, u8 val)
  351. {
  352. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  353. priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
  354. priv->spi_tx_buf[1] = reg;
  355. priv->spi_tx_buf[2] = mask;
  356. priv->spi_tx_buf[3] = val;
  357. mcp251x_spi_write(spi, 4);
  358. }
  359. static u8 mcp251x_read_stat(struct spi_device *spi)
  360. {
  361. return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
  362. }
  363. #define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \
  364. readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \
  365. delay_us, timeout_us)
  366. #ifdef CONFIG_GPIOLIB
  367. enum {
  368. MCP251X_GPIO_TX0RTS = 0, /* inputs */
  369. MCP251X_GPIO_TX1RTS,
  370. MCP251X_GPIO_TX2RTS,
  371. MCP251X_GPIO_RX0BF, /* outputs */
  372. MCP251X_GPIO_RX1BF,
  373. };
  374. #define MCP251X_GPIO_INPUT_MASK \
  375. GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)
  376. #define MCP251X_GPIO_OUTPUT_MASK \
  377. GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)
  378. static const char * const mcp251x_gpio_names[] = {
  379. [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */
  380. [MCP251X_GPIO_TX1RTS] = "TX1RTS",
  381. [MCP251X_GPIO_TX2RTS] = "TX2RTS",
  382. [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */
  383. [MCP251X_GPIO_RX1BF] = "RX1BF",
  384. };
  385. static inline bool mcp251x_gpio_is_input(unsigned int offset)
  386. {
  387. return offset <= MCP251X_GPIO_TX2RTS;
  388. }
  389. static int mcp251x_gpio_request(struct gpio_chip *chip,
  390. unsigned int offset)
  391. {
  392. struct mcp251x_priv *priv = gpiochip_get_data(chip);
  393. u8 val;
  394. /* nothing to be done for inputs */
  395. if (mcp251x_gpio_is_input(offset))
  396. return 0;
  397. val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
  398. mutex_lock(&priv->mcp_lock);
  399. mcp251x_write_bits(priv->spi, BFPCTRL, val, val);
  400. mutex_unlock(&priv->mcp_lock);
  401. priv->reg_bfpctrl |= val;
  402. return 0;
  403. }
  404. static void mcp251x_gpio_free(struct gpio_chip *chip,
  405. unsigned int offset)
  406. {
  407. struct mcp251x_priv *priv = gpiochip_get_data(chip);
  408. u8 val;
  409. /* nothing to be done for inputs */
  410. if (mcp251x_gpio_is_input(offset))
  411. return;
  412. val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
  413. mutex_lock(&priv->mcp_lock);
  414. mcp251x_write_bits(priv->spi, BFPCTRL, val, 0);
  415. mutex_unlock(&priv->mcp_lock);
  416. priv->reg_bfpctrl &= ~val;
  417. }
  418. static int mcp251x_gpio_get_direction(struct gpio_chip *chip,
  419. unsigned int offset)
  420. {
  421. if (mcp251x_gpio_is_input(offset))
  422. return GPIOF_DIR_IN;
  423. return GPIOF_DIR_OUT;
  424. }
  425. static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset)
  426. {
  427. struct mcp251x_priv *priv = gpiochip_get_data(chip);
  428. u8 reg, mask, val;
  429. if (mcp251x_gpio_is_input(offset)) {
  430. reg = TXRTSCTRL;
  431. mask = TXRTSCTRL_RTS(offset);
  432. } else {
  433. reg = BFPCTRL;
  434. mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
  435. }
  436. mutex_lock(&priv->mcp_lock);
  437. val = mcp251x_read_reg(priv->spi, reg);
  438. mutex_unlock(&priv->mcp_lock);
  439. return !!(val & mask);
  440. }
  441. static int mcp251x_gpio_get_multiple(struct gpio_chip *chip,
  442. unsigned long *maskp, unsigned long *bitsp)
  443. {
  444. struct mcp251x_priv *priv = gpiochip_get_data(chip);
  445. unsigned long bits = 0;
  446. u8 val;
  447. mutex_lock(&priv->mcp_lock);
  448. if (maskp[0] & MCP251X_GPIO_INPUT_MASK) {
  449. val = mcp251x_read_reg(priv->spi, TXRTSCTRL);
  450. val = FIELD_GET(TXRTSCTRL_RTS_MASK, val);
  451. bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val);
  452. }
  453. if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) {
  454. val = mcp251x_read_reg(priv->spi, BFPCTRL);
  455. val = FIELD_GET(BFPCTRL_BFS_MASK, val);
  456. bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val);
  457. }
  458. mutex_unlock(&priv->mcp_lock);
  459. bitsp[0] = bits;
  460. return 0;
  461. }
  462. static void mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset,
  463. int value)
  464. {
  465. struct mcp251x_priv *priv = gpiochip_get_data(chip);
  466. u8 mask, val;
  467. mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
  468. val = value ? mask : 0;
  469. mutex_lock(&priv->mcp_lock);
  470. mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
  471. mutex_unlock(&priv->mcp_lock);
  472. priv->reg_bfpctrl &= ~mask;
  473. priv->reg_bfpctrl |= val;
  474. }
  475. static void
  476. mcp251x_gpio_set_multiple(struct gpio_chip *chip,
  477. unsigned long *maskp, unsigned long *bitsp)
  478. {
  479. struct mcp251x_priv *priv = gpiochip_get_data(chip);
  480. u8 mask, val;
  481. mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]);
  482. mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask);
  483. val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]);
  484. val = FIELD_PREP(BFPCTRL_BFS_MASK, val);
  485. if (!mask)
  486. return;
  487. mutex_lock(&priv->mcp_lock);
  488. mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
  489. mutex_unlock(&priv->mcp_lock);
  490. priv->reg_bfpctrl &= ~mask;
  491. priv->reg_bfpctrl |= val;
  492. }
  493. static void mcp251x_gpio_restore(struct spi_device *spi)
  494. {
  495. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  496. mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl);
  497. }
  498. static int mcp251x_gpio_setup(struct mcp251x_priv *priv)
  499. {
  500. struct gpio_chip *gpio = &priv->gpio;
  501. if (!device_property_present(&priv->spi->dev, "gpio-controller"))
  502. return 0;
  503. /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */
  504. gpio->label = priv->spi->modalias;
  505. gpio->parent = &priv->spi->dev;
  506. gpio->owner = THIS_MODULE;
  507. gpio->request = mcp251x_gpio_request;
  508. gpio->free = mcp251x_gpio_free;
  509. gpio->get_direction = mcp251x_gpio_get_direction;
  510. gpio->get = mcp251x_gpio_get;
  511. gpio->get_multiple = mcp251x_gpio_get_multiple;
  512. gpio->set = mcp251x_gpio_set;
  513. gpio->set_multiple = mcp251x_gpio_set_multiple;
  514. gpio->base = -1;
  515. gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names);
  516. gpio->names = mcp251x_gpio_names;
  517. gpio->can_sleep = true;
  518. return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv);
  519. }
  520. #else
  521. static inline void mcp251x_gpio_restore(struct spi_device *spi)
  522. {
  523. }
  524. static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv)
  525. {
  526. return 0;
  527. }
  528. #endif
  529. static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
  530. int len, int tx_buf_idx)
  531. {
  532. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  533. if (mcp251x_is_2510(spi)) {
  534. int i;
  535. for (i = 1; i < TXBDAT_OFF + len; i++)
  536. mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
  537. buf[i]);
  538. } else {
  539. memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
  540. mcp251x_spi_write(spi, TXBDAT_OFF + len);
  541. }
  542. }
  543. static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
  544. int tx_buf_idx)
  545. {
  546. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  547. u32 sid, eid, exide, rtr;
  548. u8 buf[SPI_TRANSFER_BUF_LEN];
  549. exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
  550. if (exide)
  551. sid = (frame->can_id & CAN_EFF_MASK) >> 18;
  552. else
  553. sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
  554. eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
  555. rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
  556. buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
  557. buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
  558. buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
  559. (exide << SIDL_EXIDE_SHIFT) |
  560. ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
  561. buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
  562. buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
  563. buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->len;
  564. memcpy(buf + TXBDAT_OFF, frame->data, frame->len);
  565. mcp251x_hw_tx_frame(spi, buf, frame->len, tx_buf_idx);
  566. /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
  567. priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
  568. mcp251x_spi_write(priv->spi, 1);
  569. }
  570. static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
  571. int buf_idx)
  572. {
  573. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  574. if (mcp251x_is_2510(spi)) {
  575. int i, len;
  576. for (i = 1; i < RXBDAT_OFF; i++)
  577. buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
  578. len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
  579. for (; i < (RXBDAT_OFF + len); i++)
  580. buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
  581. } else {
  582. priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
  583. if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
  584. spi_write_then_read(spi, priv->spi_tx_buf, 1,
  585. priv->spi_rx_buf,
  586. SPI_TRANSFER_BUF_LEN);
  587. memcpy(buf + 1, priv->spi_rx_buf,
  588. SPI_TRANSFER_BUF_LEN - 1);
  589. } else {
  590. mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
  591. memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
  592. }
  593. }
  594. }
  595. static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
  596. {
  597. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  598. struct sk_buff *skb;
  599. struct can_frame *frame;
  600. u8 buf[SPI_TRANSFER_BUF_LEN];
  601. skb = alloc_can_skb(priv->net, &frame);
  602. if (!skb) {
  603. dev_err(&spi->dev, "cannot allocate RX skb\n");
  604. priv->net->stats.rx_dropped++;
  605. return;
  606. }
  607. mcp251x_hw_rx_frame(spi, buf, buf_idx);
  608. if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
  609. /* Extended ID format */
  610. frame->can_id = CAN_EFF_FLAG;
  611. frame->can_id |=
  612. /* Extended ID part */
  613. SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
  614. SET_BYTE(buf[RXBEID8_OFF], 1) |
  615. SET_BYTE(buf[RXBEID0_OFF], 0) |
  616. /* Standard ID part */
  617. (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
  618. (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
  619. /* Remote transmission request */
  620. if (buf[RXBDLC_OFF] & RXBDLC_RTR)
  621. frame->can_id |= CAN_RTR_FLAG;
  622. } else {
  623. /* Standard ID format */
  624. frame->can_id =
  625. (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
  626. (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
  627. if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
  628. frame->can_id |= CAN_RTR_FLAG;
  629. }
  630. /* Data length */
  631. frame->len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
  632. if (!(frame->can_id & CAN_RTR_FLAG)) {
  633. memcpy(frame->data, buf + RXBDAT_OFF, frame->len);
  634. priv->net->stats.rx_bytes += frame->len;
  635. }
  636. priv->net->stats.rx_packets++;
  637. netif_rx(skb);
  638. }
  639. static void mcp251x_hw_sleep(struct spi_device *spi)
  640. {
  641. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
  642. }
  643. /* May only be called when device is sleeping! */
  644. static int mcp251x_hw_wake(struct spi_device *spi)
  645. {
  646. u8 value;
  647. int ret;
  648. /* Force wakeup interrupt to wake device, but don't execute IST */
  649. disable_irq(spi->irq);
  650. mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
  651. /* Wait for oscillator startup timer after wake up */
  652. mdelay(MCP251X_OST_DELAY_MS);
  653. /* Put device into config mode */
  654. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
  655. /* Wait for the device to enter config mode */
  656. ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
  657. MCP251X_OST_DELAY_MS * 1000,
  658. USEC_PER_SEC);
  659. if (ret) {
  660. dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
  661. return ret;
  662. }
  663. /* Disable and clear pending interrupts */
  664. mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
  665. enable_irq(spi->irq);
  666. return 0;
  667. }
  668. static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
  669. struct net_device *net)
  670. {
  671. struct mcp251x_priv *priv = netdev_priv(net);
  672. struct spi_device *spi = priv->spi;
  673. if (priv->tx_skb || priv->tx_busy) {
  674. dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
  675. return NETDEV_TX_BUSY;
  676. }
  677. if (can_dev_dropped_skb(net, skb))
  678. return NETDEV_TX_OK;
  679. netif_stop_queue(net);
  680. priv->tx_skb = skb;
  681. queue_work(priv->wq, &priv->tx_work);
  682. return NETDEV_TX_OK;
  683. }
  684. static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
  685. {
  686. struct mcp251x_priv *priv = netdev_priv(net);
  687. switch (mode) {
  688. case CAN_MODE_START:
  689. mcp251x_clean(net);
  690. /* We have to delay work since SPI I/O may sleep */
  691. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  692. priv->restart_tx = 1;
  693. if (priv->can.restart_ms == 0)
  694. priv->after_suspend = AFTER_SUSPEND_RESTART;
  695. queue_work(priv->wq, &priv->restart_work);
  696. break;
  697. default:
  698. return -EOPNOTSUPP;
  699. }
  700. return 0;
  701. }
  702. static int mcp251x_set_normal_mode(struct spi_device *spi)
  703. {
  704. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  705. u8 value;
  706. int ret;
  707. /* Enable interrupts */
  708. mcp251x_write_reg(spi, CANINTE,
  709. CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
  710. CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
  711. if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
  712. /* Put device into loopback mode */
  713. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
  714. } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
  715. /* Put device into listen-only mode */
  716. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
  717. } else {
  718. /* Put device into normal mode */
  719. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
  720. /* Wait for the device to enter normal mode */
  721. ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0,
  722. MCP251X_OST_DELAY_MS * 1000,
  723. USEC_PER_SEC);
  724. if (ret) {
  725. dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
  726. return ret;
  727. }
  728. }
  729. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  730. return 0;
  731. }
  732. static int mcp251x_do_set_bittiming(struct net_device *net)
  733. {
  734. struct mcp251x_priv *priv = netdev_priv(net);
  735. struct can_bittiming *bt = &priv->can.bittiming;
  736. struct spi_device *spi = priv->spi;
  737. mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
  738. (bt->brp - 1));
  739. mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
  740. (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
  741. CNF2_SAM : 0) |
  742. ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
  743. (bt->prop_seg - 1));
  744. mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
  745. (bt->phase_seg2 - 1));
  746. dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
  747. mcp251x_read_reg(spi, CNF1),
  748. mcp251x_read_reg(spi, CNF2),
  749. mcp251x_read_reg(spi, CNF3));
  750. return 0;
  751. }
  752. static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
  753. {
  754. mcp251x_do_set_bittiming(net);
  755. mcp251x_write_reg(spi, RXBCTRL(0),
  756. RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
  757. mcp251x_write_reg(spi, RXBCTRL(1),
  758. RXBCTRL_RXM0 | RXBCTRL_RXM1);
  759. return 0;
  760. }
  761. static int mcp251x_hw_reset(struct spi_device *spi)
  762. {
  763. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  764. u8 value;
  765. int ret;
  766. /* Wait for oscillator startup timer after power up */
  767. mdelay(MCP251X_OST_DELAY_MS);
  768. priv->spi_tx_buf[0] = INSTRUCTION_RESET;
  769. ret = mcp251x_spi_write(spi, 1);
  770. if (ret)
  771. return ret;
  772. /* Wait for oscillator startup timer after reset */
  773. mdelay(MCP251X_OST_DELAY_MS);
  774. /* Wait for reset to finish */
  775. ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
  776. MCP251X_OST_DELAY_MS * 1000,
  777. USEC_PER_SEC);
  778. if (ret)
  779. dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n");
  780. return ret;
  781. }
  782. static int mcp251x_hw_probe(struct spi_device *spi)
  783. {
  784. u8 ctrl;
  785. int ret;
  786. ret = mcp251x_hw_reset(spi);
  787. if (ret)
  788. return ret;
  789. ctrl = mcp251x_read_reg(spi, CANCTRL);
  790. dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
  791. /* Check for power up default value */
  792. if ((ctrl & 0x17) != 0x07)
  793. return -ENODEV;
  794. return 0;
  795. }
  796. static int mcp251x_power_enable(struct regulator *reg, int enable)
  797. {
  798. if (IS_ERR_OR_NULL(reg))
  799. return 0;
  800. if (enable)
  801. return regulator_enable(reg);
  802. else
  803. return regulator_disable(reg);
  804. }
  805. static int mcp251x_stop(struct net_device *net)
  806. {
  807. struct mcp251x_priv *priv = netdev_priv(net);
  808. struct spi_device *spi = priv->spi;
  809. close_candev(net);
  810. priv->force_quit = 1;
  811. free_irq(spi->irq, priv);
  812. mutex_lock(&priv->mcp_lock);
  813. /* Disable and clear pending interrupts */
  814. mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
  815. mcp251x_write_reg(spi, TXBCTRL(0), 0);
  816. mcp251x_clean(net);
  817. mcp251x_hw_sleep(spi);
  818. mcp251x_power_enable(priv->transceiver, 0);
  819. priv->can.state = CAN_STATE_STOPPED;
  820. mutex_unlock(&priv->mcp_lock);
  821. return 0;
  822. }
  823. static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
  824. {
  825. struct sk_buff *skb;
  826. struct can_frame *frame;
  827. skb = alloc_can_err_skb(net, &frame);
  828. if (skb) {
  829. frame->can_id |= can_id;
  830. frame->data[1] = data1;
  831. netif_rx(skb);
  832. } else {
  833. netdev_err(net, "cannot allocate error skb\n");
  834. }
  835. }
  836. static void mcp251x_tx_work_handler(struct work_struct *ws)
  837. {
  838. struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
  839. tx_work);
  840. struct spi_device *spi = priv->spi;
  841. struct net_device *net = priv->net;
  842. struct can_frame *frame;
  843. mutex_lock(&priv->mcp_lock);
  844. if (priv->tx_skb) {
  845. if (priv->can.state == CAN_STATE_BUS_OFF) {
  846. mcp251x_clean(net);
  847. } else {
  848. frame = (struct can_frame *)priv->tx_skb->data;
  849. if (frame->len > CAN_FRAME_MAX_DATA_LEN)
  850. frame->len = CAN_FRAME_MAX_DATA_LEN;
  851. mcp251x_hw_tx(spi, frame, 0);
  852. priv->tx_busy = true;
  853. can_put_echo_skb(priv->tx_skb, net, 0, 0);
  854. priv->tx_skb = NULL;
  855. }
  856. }
  857. mutex_unlock(&priv->mcp_lock);
  858. }
  859. static void mcp251x_restart_work_handler(struct work_struct *ws)
  860. {
  861. struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
  862. restart_work);
  863. struct spi_device *spi = priv->spi;
  864. struct net_device *net = priv->net;
  865. mutex_lock(&priv->mcp_lock);
  866. if (priv->after_suspend) {
  867. if (priv->after_suspend & AFTER_SUSPEND_POWER) {
  868. mcp251x_hw_reset(spi);
  869. mcp251x_setup(net, spi);
  870. mcp251x_gpio_restore(spi);
  871. } else {
  872. mcp251x_hw_wake(spi);
  873. }
  874. priv->force_quit = 0;
  875. if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
  876. mcp251x_set_normal_mode(spi);
  877. } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
  878. netif_device_attach(net);
  879. mcp251x_clean(net);
  880. mcp251x_set_normal_mode(spi);
  881. netif_wake_queue(net);
  882. } else {
  883. mcp251x_hw_sleep(spi);
  884. }
  885. priv->after_suspend = 0;
  886. }
  887. if (priv->restart_tx) {
  888. priv->restart_tx = 0;
  889. mcp251x_write_reg(spi, TXBCTRL(0), 0);
  890. mcp251x_clean(net);
  891. netif_wake_queue(net);
  892. mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
  893. }
  894. mutex_unlock(&priv->mcp_lock);
  895. }
  896. static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
  897. {
  898. struct mcp251x_priv *priv = dev_id;
  899. struct spi_device *spi = priv->spi;
  900. struct net_device *net = priv->net;
  901. mutex_lock(&priv->mcp_lock);
  902. while (!priv->force_quit) {
  903. enum can_state new_state;
  904. u8 intf, eflag;
  905. u8 clear_intf = 0;
  906. int can_id = 0, data1 = 0;
  907. mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
  908. /* receive buffer 0 */
  909. if (intf & CANINTF_RX0IF) {
  910. mcp251x_hw_rx(spi, 0);
  911. /* Free one buffer ASAP
  912. * (The MCP2515/25625 does this automatically.)
  913. */
  914. if (mcp251x_is_2510(spi))
  915. mcp251x_write_bits(spi, CANINTF,
  916. CANINTF_RX0IF, 0x00);
  917. /* check if buffer 1 is already known to be full, no need to re-read */
  918. if (!(intf & CANINTF_RX1IF)) {
  919. u8 intf1, eflag1;
  920. /* intf needs to be read again to avoid a race condition */
  921. mcp251x_read_2regs(spi, CANINTF, &intf1, &eflag1);
  922. /* combine flags from both operations for error handling */
  923. intf |= intf1;
  924. eflag |= eflag1;
  925. }
  926. }
  927. /* receive buffer 1 */
  928. if (intf & CANINTF_RX1IF) {
  929. mcp251x_hw_rx(spi, 1);
  930. /* The MCP2515/25625 does this automatically. */
  931. if (mcp251x_is_2510(spi))
  932. clear_intf |= CANINTF_RX1IF;
  933. }
  934. /* mask out flags we don't care about */
  935. intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
  936. /* any error or tx interrupt we need to clear? */
  937. if (intf & (CANINTF_ERR | CANINTF_TX))
  938. clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
  939. if (clear_intf)
  940. mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
  941. if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
  942. mcp251x_write_bits(spi, EFLG, eflag, 0x00);
  943. /* Update can state */
  944. if (eflag & EFLG_TXBO) {
  945. new_state = CAN_STATE_BUS_OFF;
  946. can_id |= CAN_ERR_BUSOFF;
  947. } else if (eflag & EFLG_TXEP) {
  948. new_state = CAN_STATE_ERROR_PASSIVE;
  949. can_id |= CAN_ERR_CRTL;
  950. data1 |= CAN_ERR_CRTL_TX_PASSIVE;
  951. } else if (eflag & EFLG_RXEP) {
  952. new_state = CAN_STATE_ERROR_PASSIVE;
  953. can_id |= CAN_ERR_CRTL;
  954. data1 |= CAN_ERR_CRTL_RX_PASSIVE;
  955. } else if (eflag & EFLG_TXWAR) {
  956. new_state = CAN_STATE_ERROR_WARNING;
  957. can_id |= CAN_ERR_CRTL;
  958. data1 |= CAN_ERR_CRTL_TX_WARNING;
  959. } else if (eflag & EFLG_RXWAR) {
  960. new_state = CAN_STATE_ERROR_WARNING;
  961. can_id |= CAN_ERR_CRTL;
  962. data1 |= CAN_ERR_CRTL_RX_WARNING;
  963. } else {
  964. new_state = CAN_STATE_ERROR_ACTIVE;
  965. }
  966. /* Update can state statistics */
  967. switch (priv->can.state) {
  968. case CAN_STATE_ERROR_ACTIVE:
  969. if (new_state >= CAN_STATE_ERROR_WARNING &&
  970. new_state <= CAN_STATE_BUS_OFF)
  971. priv->can.can_stats.error_warning++;
  972. fallthrough;
  973. case CAN_STATE_ERROR_WARNING:
  974. if (new_state >= CAN_STATE_ERROR_PASSIVE &&
  975. new_state <= CAN_STATE_BUS_OFF)
  976. priv->can.can_stats.error_passive++;
  977. break;
  978. default:
  979. break;
  980. }
  981. priv->can.state = new_state;
  982. if (intf & CANINTF_ERRIF) {
  983. /* Handle overflow counters */
  984. if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
  985. if (eflag & EFLG_RX0OVR) {
  986. net->stats.rx_over_errors++;
  987. net->stats.rx_errors++;
  988. }
  989. if (eflag & EFLG_RX1OVR) {
  990. net->stats.rx_over_errors++;
  991. net->stats.rx_errors++;
  992. }
  993. can_id |= CAN_ERR_CRTL;
  994. data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
  995. }
  996. mcp251x_error_skb(net, can_id, data1);
  997. }
  998. if (priv->can.state == CAN_STATE_BUS_OFF) {
  999. if (priv->can.restart_ms == 0) {
  1000. priv->force_quit = 1;
  1001. priv->can.can_stats.bus_off++;
  1002. can_bus_off(net);
  1003. mcp251x_hw_sleep(spi);
  1004. break;
  1005. }
  1006. }
  1007. if (intf == 0)
  1008. break;
  1009. if (intf & CANINTF_TX) {
  1010. if (priv->tx_busy) {
  1011. net->stats.tx_packets++;
  1012. net->stats.tx_bytes += can_get_echo_skb(net, 0,
  1013. NULL);
  1014. priv->tx_busy = false;
  1015. }
  1016. netif_wake_queue(net);
  1017. }
  1018. }
  1019. mutex_unlock(&priv->mcp_lock);
  1020. return IRQ_HANDLED;
  1021. }
  1022. static int mcp251x_open(struct net_device *net)
  1023. {
  1024. struct mcp251x_priv *priv = netdev_priv(net);
  1025. struct spi_device *spi = priv->spi;
  1026. unsigned long flags = 0;
  1027. int ret;
  1028. ret = open_candev(net);
  1029. if (ret) {
  1030. dev_err(&spi->dev, "unable to set initial baudrate!\n");
  1031. return ret;
  1032. }
  1033. mutex_lock(&priv->mcp_lock);
  1034. mcp251x_power_enable(priv->transceiver, 1);
  1035. priv->force_quit = 0;
  1036. priv->tx_skb = NULL;
  1037. priv->tx_busy = false;
  1038. if (!dev_fwnode(&spi->dev))
  1039. flags = IRQF_TRIGGER_FALLING;
  1040. ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
  1041. flags | IRQF_ONESHOT, dev_name(&spi->dev),
  1042. priv);
  1043. if (ret) {
  1044. dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
  1045. goto out_close;
  1046. }
  1047. ret = mcp251x_hw_wake(spi);
  1048. if (ret)
  1049. goto out_free_irq;
  1050. ret = mcp251x_setup(net, spi);
  1051. if (ret)
  1052. goto out_free_irq;
  1053. ret = mcp251x_set_normal_mode(spi);
  1054. if (ret)
  1055. goto out_free_irq;
  1056. netif_wake_queue(net);
  1057. mutex_unlock(&priv->mcp_lock);
  1058. return 0;
  1059. out_free_irq:
  1060. free_irq(spi->irq, priv);
  1061. mcp251x_hw_sleep(spi);
  1062. out_close:
  1063. mcp251x_power_enable(priv->transceiver, 0);
  1064. close_candev(net);
  1065. mutex_unlock(&priv->mcp_lock);
  1066. return ret;
  1067. }
  1068. static const struct net_device_ops mcp251x_netdev_ops = {
  1069. .ndo_open = mcp251x_open,
  1070. .ndo_stop = mcp251x_stop,
  1071. .ndo_start_xmit = mcp251x_hard_start_xmit,
  1072. .ndo_change_mtu = can_change_mtu,
  1073. };
  1074. static const struct ethtool_ops mcp251x_ethtool_ops = {
  1075. .get_ts_info = ethtool_op_get_ts_info,
  1076. };
  1077. static const struct of_device_id mcp251x_of_match[] = {
  1078. {
  1079. .compatible = "microchip,mcp2510",
  1080. .data = (void *)CAN_MCP251X_MCP2510,
  1081. },
  1082. {
  1083. .compatible = "microchip,mcp2515",
  1084. .data = (void *)CAN_MCP251X_MCP2515,
  1085. },
  1086. {
  1087. .compatible = "microchip,mcp25625",
  1088. .data = (void *)CAN_MCP251X_MCP25625,
  1089. },
  1090. { }
  1091. };
  1092. MODULE_DEVICE_TABLE(of, mcp251x_of_match);
  1093. static const struct spi_device_id mcp251x_id_table[] = {
  1094. {
  1095. .name = "mcp2510",
  1096. .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
  1097. },
  1098. {
  1099. .name = "mcp2515",
  1100. .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
  1101. },
  1102. {
  1103. .name = "mcp25625",
  1104. .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
  1105. },
  1106. { }
  1107. };
  1108. MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
  1109. static int mcp251x_can_probe(struct spi_device *spi)
  1110. {
  1111. const void *match = device_get_match_data(&spi->dev);
  1112. struct net_device *net;
  1113. struct mcp251x_priv *priv;
  1114. struct clk *clk;
  1115. u32 freq;
  1116. int ret;
  1117. clk = devm_clk_get_optional(&spi->dev, NULL);
  1118. if (IS_ERR(clk))
  1119. return PTR_ERR(clk);
  1120. freq = clk_get_rate(clk);
  1121. if (freq == 0)
  1122. device_property_read_u32(&spi->dev, "clock-frequency", &freq);
  1123. /* Sanity check */
  1124. if (freq < 1000000 || freq > 25000000)
  1125. return -ERANGE;
  1126. /* Allocate can/net device */
  1127. net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
  1128. if (!net)
  1129. return -ENOMEM;
  1130. ret = clk_prepare_enable(clk);
  1131. if (ret)
  1132. goto out_free;
  1133. net->netdev_ops = &mcp251x_netdev_ops;
  1134. net->ethtool_ops = &mcp251x_ethtool_ops;
  1135. net->flags |= IFF_ECHO;
  1136. priv = netdev_priv(net);
  1137. priv->can.bittiming_const = &mcp251x_bittiming_const;
  1138. priv->can.do_set_mode = mcp251x_do_set_mode;
  1139. priv->can.clock.freq = freq / 2;
  1140. priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
  1141. CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
  1142. if (match)
  1143. priv->model = (enum mcp251x_model)(uintptr_t)match;
  1144. else
  1145. priv->model = spi_get_device_id(spi)->driver_data;
  1146. priv->net = net;
  1147. priv->clk = clk;
  1148. spi_set_drvdata(spi, priv);
  1149. /* Configure the SPI bus */
  1150. spi->bits_per_word = 8;
  1151. if (mcp251x_is_2510(spi))
  1152. spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
  1153. else
  1154. spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
  1155. ret = spi_setup(spi);
  1156. if (ret)
  1157. goto out_clk;
  1158. priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
  1159. priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
  1160. if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
  1161. (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
  1162. ret = -EPROBE_DEFER;
  1163. goto out_clk;
  1164. }
  1165. ret = mcp251x_power_enable(priv->power, 1);
  1166. if (ret)
  1167. goto out_clk;
  1168. priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
  1169. 0);
  1170. if (!priv->wq) {
  1171. ret = -ENOMEM;
  1172. goto out_clk;
  1173. }
  1174. INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
  1175. INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
  1176. priv->spi = spi;
  1177. mutex_init(&priv->mcp_lock);
  1178. priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
  1179. GFP_KERNEL);
  1180. if (!priv->spi_tx_buf) {
  1181. ret = -ENOMEM;
  1182. goto error_probe;
  1183. }
  1184. priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
  1185. GFP_KERNEL);
  1186. if (!priv->spi_rx_buf) {
  1187. ret = -ENOMEM;
  1188. goto error_probe;
  1189. }
  1190. SET_NETDEV_DEV(net, &spi->dev);
  1191. /* Here is OK to not lock the MCP, no one knows about it yet */
  1192. ret = mcp251x_hw_probe(spi);
  1193. if (ret) {
  1194. if (ret == -ENODEV)
  1195. dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
  1196. priv->model);
  1197. goto error_probe;
  1198. }
  1199. mcp251x_hw_sleep(spi);
  1200. ret = register_candev(net);
  1201. if (ret)
  1202. goto error_probe;
  1203. ret = mcp251x_gpio_setup(priv);
  1204. if (ret)
  1205. goto out_unregister_candev;
  1206. netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
  1207. return 0;
  1208. out_unregister_candev:
  1209. unregister_candev(net);
  1210. error_probe:
  1211. destroy_workqueue(priv->wq);
  1212. priv->wq = NULL;
  1213. mcp251x_power_enable(priv->power, 0);
  1214. out_clk:
  1215. clk_disable_unprepare(clk);
  1216. out_free:
  1217. free_candev(net);
  1218. dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
  1219. return ret;
  1220. }
  1221. static void mcp251x_can_remove(struct spi_device *spi)
  1222. {
  1223. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  1224. struct net_device *net = priv->net;
  1225. unregister_candev(net);
  1226. mcp251x_power_enable(priv->power, 0);
  1227. destroy_workqueue(priv->wq);
  1228. priv->wq = NULL;
  1229. clk_disable_unprepare(priv->clk);
  1230. free_candev(net);
  1231. }
  1232. static int __maybe_unused mcp251x_can_suspend(struct device *dev)
  1233. {
  1234. struct spi_device *spi = to_spi_device(dev);
  1235. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  1236. struct net_device *net = priv->net;
  1237. priv->force_quit = 1;
  1238. disable_irq(spi->irq);
  1239. /* Note: at this point neither IST nor workqueues are running.
  1240. * open/stop cannot be called anyway so locking is not needed
  1241. */
  1242. if (netif_running(net)) {
  1243. netif_device_detach(net);
  1244. mcp251x_hw_sleep(spi);
  1245. mcp251x_power_enable(priv->transceiver, 0);
  1246. priv->after_suspend = AFTER_SUSPEND_UP;
  1247. } else {
  1248. priv->after_suspend = AFTER_SUSPEND_DOWN;
  1249. }
  1250. mcp251x_power_enable(priv->power, 0);
  1251. priv->after_suspend |= AFTER_SUSPEND_POWER;
  1252. return 0;
  1253. }
  1254. static int __maybe_unused mcp251x_can_resume(struct device *dev)
  1255. {
  1256. struct spi_device *spi = to_spi_device(dev);
  1257. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  1258. if (priv->after_suspend & AFTER_SUSPEND_POWER)
  1259. mcp251x_power_enable(priv->power, 1);
  1260. if (priv->after_suspend & AFTER_SUSPEND_UP)
  1261. mcp251x_power_enable(priv->transceiver, 1);
  1262. if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
  1263. queue_work(priv->wq, &priv->restart_work);
  1264. else
  1265. priv->after_suspend = 0;
  1266. priv->force_quit = 0;
  1267. enable_irq(spi->irq);
  1268. return 0;
  1269. }
  1270. static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
  1271. mcp251x_can_resume);
  1272. static struct spi_driver mcp251x_can_driver = {
  1273. .driver = {
  1274. .name = DEVICE_NAME,
  1275. .of_match_table = mcp251x_of_match,
  1276. .pm = &mcp251x_can_pm_ops,
  1277. },
  1278. .id_table = mcp251x_id_table,
  1279. .probe = mcp251x_can_probe,
  1280. .remove = mcp251x_can_remove,
  1281. };
  1282. module_spi_driver(mcp251x_can_driver);
  1283. MODULE_AUTHOR("Chris Elston <[email protected]>, "
  1284. "Christian Pellegrin <[email protected]>");
  1285. MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
  1286. MODULE_LICENSE("GPL v2");