mscan.h 9.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Definitions of consts/structs to drive the Freescale MSCAN.
  4. *
  5. * Copyright (C) 2005-2006 Andrey Volkov <[email protected]>,
  6. * Varma Electronics Oy
  7. */
  8. #ifndef __MSCAN_H__
  9. #define __MSCAN_H__
  10. #include <linux/clk.h>
  11. #include <linux/types.h>
  12. /* MSCAN control register 0 (CANCTL0) bits */
  13. #define MSCAN_RXFRM 0x80
  14. #define MSCAN_RXACT 0x40
  15. #define MSCAN_CSWAI 0x20
  16. #define MSCAN_SYNCH 0x10
  17. #define MSCAN_TIME 0x08
  18. #define MSCAN_WUPE 0x04
  19. #define MSCAN_SLPRQ 0x02
  20. #define MSCAN_INITRQ 0x01
  21. /* MSCAN control register 1 (CANCTL1) bits */
  22. #define MSCAN_CANE 0x80
  23. #define MSCAN_CLKSRC 0x40
  24. #define MSCAN_LOOPB 0x20
  25. #define MSCAN_LISTEN 0x10
  26. #define MSCAN_BORM 0x08
  27. #define MSCAN_WUPM 0x04
  28. #define MSCAN_SLPAK 0x02
  29. #define MSCAN_INITAK 0x01
  30. /* Use the MPC5XXX MSCAN variant? */
  31. #ifdef CONFIG_PPC
  32. #define MSCAN_FOR_MPC5XXX
  33. #endif
  34. #ifdef MSCAN_FOR_MPC5XXX
  35. #define MSCAN_CLKSRC_BUS 0
  36. #define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC
  37. #define MSCAN_CLKSRC_IPS MSCAN_CLKSRC
  38. #else
  39. #define MSCAN_CLKSRC_BUS MSCAN_CLKSRC
  40. #define MSCAN_CLKSRC_XTAL 0
  41. #endif
  42. /* MSCAN receiver flag register (CANRFLG) bits */
  43. #define MSCAN_WUPIF 0x80
  44. #define MSCAN_CSCIF 0x40
  45. #define MSCAN_RSTAT1 0x20
  46. #define MSCAN_RSTAT0 0x10
  47. #define MSCAN_TSTAT1 0x08
  48. #define MSCAN_TSTAT0 0x04
  49. #define MSCAN_OVRIF 0x02
  50. #define MSCAN_RXF 0x01
  51. #define MSCAN_ERR_IF (MSCAN_OVRIF | MSCAN_CSCIF)
  52. #define MSCAN_RSTAT_MSK (MSCAN_RSTAT1 | MSCAN_RSTAT0)
  53. #define MSCAN_TSTAT_MSK (MSCAN_TSTAT1 | MSCAN_TSTAT0)
  54. #define MSCAN_STAT_MSK (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
  55. #define MSCAN_STATE_BUS_OFF (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
  56. MSCAN_TSTAT1 | MSCAN_TSTAT0)
  57. #define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
  58. #define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
  59. #define MSCAN_STATE_ACTIVE 0
  60. #define MSCAN_STATE_WARNING 1
  61. #define MSCAN_STATE_PASSIVE 2
  62. #define MSCAN_STATE_BUSOFF 3
  63. /* MSCAN receiver interrupt enable register (CANRIER) bits */
  64. #define MSCAN_WUPIE 0x80
  65. #define MSCAN_CSCIE 0x40
  66. #define MSCAN_RSTATE1 0x20
  67. #define MSCAN_RSTATE0 0x10
  68. #define MSCAN_TSTATE1 0x08
  69. #define MSCAN_TSTATE0 0x04
  70. #define MSCAN_OVRIE 0x02
  71. #define MSCAN_RXFIE 0x01
  72. /* MSCAN transmitter flag register (CANTFLG) bits */
  73. #define MSCAN_TXE2 0x04
  74. #define MSCAN_TXE1 0x02
  75. #define MSCAN_TXE0 0x01
  76. #define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
  77. /* MSCAN transmitter interrupt enable register (CANTIER) bits */
  78. #define MSCAN_TXIE2 0x04
  79. #define MSCAN_TXIE1 0x02
  80. #define MSCAN_TXIE0 0x01
  81. #define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
  82. /* MSCAN transmitter message abort request (CANTARQ) bits */
  83. #define MSCAN_ABTRQ2 0x04
  84. #define MSCAN_ABTRQ1 0x02
  85. #define MSCAN_ABTRQ0 0x01
  86. /* MSCAN transmitter message abort ack (CANTAAK) bits */
  87. #define MSCAN_ABTAK2 0x04
  88. #define MSCAN_ABTAK1 0x02
  89. #define MSCAN_ABTAK0 0x01
  90. /* MSCAN transmit buffer selection (CANTBSEL) bits */
  91. #define MSCAN_TX2 0x04
  92. #define MSCAN_TX1 0x02
  93. #define MSCAN_TX0 0x01
  94. /* MSCAN ID acceptance control register (CANIDAC) bits */
  95. #define MSCAN_IDAM1 0x20
  96. #define MSCAN_IDAM0 0x10
  97. #define MSCAN_IDHIT2 0x04
  98. #define MSCAN_IDHIT1 0x02
  99. #define MSCAN_IDHIT0 0x01
  100. #define MSCAN_AF_32BIT 0x00
  101. #define MSCAN_AF_16BIT MSCAN_IDAM0
  102. #define MSCAN_AF_8BIT MSCAN_IDAM1
  103. #define MSCAN_AF_CLOSED (MSCAN_IDAM0|MSCAN_IDAM1)
  104. #define MSCAN_AF_MASK (~(MSCAN_IDAM0|MSCAN_IDAM1))
  105. /* MSCAN Miscellaneous Register (CANMISC) bits */
  106. #define MSCAN_BOHOLD 0x01
  107. /* MSCAN Identifier Register (IDR) bits */
  108. #define MSCAN_SFF_RTR_SHIFT 4
  109. #define MSCAN_EFF_RTR_SHIFT 0
  110. #define MSCAN_EFF_FLAGS 0x18 /* IDE + SRR */
  111. #ifdef MSCAN_FOR_MPC5XXX
  112. #define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
  113. #define _MSCAN_RESERVED_DSR_SIZE 2
  114. #else
  115. #define _MSCAN_RESERVED_(n, num)
  116. #define _MSCAN_RESERVED_DSR_SIZE 0
  117. #endif
  118. /* Structure of the hardware registers */
  119. struct mscan_regs {
  120. /* (see doc S12MSCANV3/D) MPC5200 MSCAN */
  121. u8 canctl0; /* + 0x00 0x00 */
  122. u8 canctl1; /* + 0x01 0x01 */
  123. _MSCAN_RESERVED_(1, 2); /* + 0x02 */
  124. u8 canbtr0; /* + 0x04 0x02 */
  125. u8 canbtr1; /* + 0x05 0x03 */
  126. _MSCAN_RESERVED_(2, 2); /* + 0x06 */
  127. u8 canrflg; /* + 0x08 0x04 */
  128. u8 canrier; /* + 0x09 0x05 */
  129. _MSCAN_RESERVED_(3, 2); /* + 0x0a */
  130. u8 cantflg; /* + 0x0c 0x06 */
  131. u8 cantier; /* + 0x0d 0x07 */
  132. _MSCAN_RESERVED_(4, 2); /* + 0x0e */
  133. u8 cantarq; /* + 0x10 0x08 */
  134. u8 cantaak; /* + 0x11 0x09 */
  135. _MSCAN_RESERVED_(5, 2); /* + 0x12 */
  136. u8 cantbsel; /* + 0x14 0x0a */
  137. u8 canidac; /* + 0x15 0x0b */
  138. u8 reserved; /* + 0x16 0x0c */
  139. _MSCAN_RESERVED_(6, 2); /* + 0x17 */
  140. u8 canmisc; /* + 0x19 0x0d */
  141. _MSCAN_RESERVED_(7, 2); /* + 0x1a */
  142. u8 canrxerr; /* + 0x1c 0x0e */
  143. u8 cantxerr; /* + 0x1d 0x0f */
  144. _MSCAN_RESERVED_(8, 2); /* + 0x1e */
  145. u16 canidar1_0; /* + 0x20 0x10 */
  146. _MSCAN_RESERVED_(9, 2); /* + 0x22 */
  147. u16 canidar3_2; /* + 0x24 0x12 */
  148. _MSCAN_RESERVED_(10, 2); /* + 0x26 */
  149. u16 canidmr1_0; /* + 0x28 0x14 */
  150. _MSCAN_RESERVED_(11, 2); /* + 0x2a */
  151. u16 canidmr3_2; /* + 0x2c 0x16 */
  152. _MSCAN_RESERVED_(12, 2); /* + 0x2e */
  153. u16 canidar5_4; /* + 0x30 0x18 */
  154. _MSCAN_RESERVED_(13, 2); /* + 0x32 */
  155. u16 canidar7_6; /* + 0x34 0x1a */
  156. _MSCAN_RESERVED_(14, 2); /* + 0x36 */
  157. u16 canidmr5_4; /* + 0x38 0x1c */
  158. _MSCAN_RESERVED_(15, 2); /* + 0x3a */
  159. u16 canidmr7_6; /* + 0x3c 0x1e */
  160. _MSCAN_RESERVED_(16, 2); /* + 0x3e */
  161. struct {
  162. u16 idr1_0; /* + 0x40 0x20 */
  163. _MSCAN_RESERVED_(17, 2); /* + 0x42 */
  164. u16 idr3_2; /* + 0x44 0x22 */
  165. _MSCAN_RESERVED_(18, 2); /* + 0x46 */
  166. u16 dsr1_0; /* + 0x48 0x24 */
  167. _MSCAN_RESERVED_(19, 2); /* + 0x4a */
  168. u16 dsr3_2; /* + 0x4c 0x26 */
  169. _MSCAN_RESERVED_(20, 2); /* + 0x4e */
  170. u16 dsr5_4; /* + 0x50 0x28 */
  171. _MSCAN_RESERVED_(21, 2); /* + 0x52 */
  172. u16 dsr7_6; /* + 0x54 0x2a */
  173. _MSCAN_RESERVED_(22, 2); /* + 0x56 */
  174. u8 dlr; /* + 0x58 0x2c */
  175. u8 reserved; /* + 0x59 0x2d */
  176. _MSCAN_RESERVED_(23, 2); /* + 0x5a */
  177. u16 time; /* + 0x5c 0x2e */
  178. } rx;
  179. _MSCAN_RESERVED_(24, 2); /* + 0x5e */
  180. struct {
  181. u16 idr1_0; /* + 0x60 0x30 */
  182. _MSCAN_RESERVED_(25, 2); /* + 0x62 */
  183. u16 idr3_2; /* + 0x64 0x32 */
  184. _MSCAN_RESERVED_(26, 2); /* + 0x66 */
  185. u16 dsr1_0; /* + 0x68 0x34 */
  186. _MSCAN_RESERVED_(27, 2); /* + 0x6a */
  187. u16 dsr3_2; /* + 0x6c 0x36 */
  188. _MSCAN_RESERVED_(28, 2); /* + 0x6e */
  189. u16 dsr5_4; /* + 0x70 0x38 */
  190. _MSCAN_RESERVED_(29, 2); /* + 0x72 */
  191. u16 dsr7_6; /* + 0x74 0x3a */
  192. _MSCAN_RESERVED_(30, 2); /* + 0x76 */
  193. u8 dlr; /* + 0x78 0x3c */
  194. u8 tbpr; /* + 0x79 0x3d */
  195. _MSCAN_RESERVED_(31, 2); /* + 0x7a */
  196. u16 time; /* + 0x7c 0x3e */
  197. } tx;
  198. _MSCAN_RESERVED_(32, 2); /* + 0x7e */
  199. } __packed;
  200. #undef _MSCAN_RESERVED_
  201. #define MSCAN_REGION sizeof(struct mscan)
  202. #define MSCAN_NORMAL_MODE 0
  203. #define MSCAN_SLEEP_MODE MSCAN_SLPRQ
  204. #define MSCAN_INIT_MODE (MSCAN_INITRQ | MSCAN_SLPRQ)
  205. #define MSCAN_POWEROFF_MODE (MSCAN_CSWAI | MSCAN_SLPRQ)
  206. #define MSCAN_SET_MODE_RETRIES 255
  207. #define MSCAN_ECHO_SKB_MAX 3
  208. #define MSCAN_RX_INTS_ENABLE (MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | \
  209. MSCAN_RSTATE1 | MSCAN_RSTATE0 | \
  210. MSCAN_TSTATE1 | MSCAN_TSTATE0)
  211. /* MSCAN type variants */
  212. enum {
  213. MSCAN_TYPE_MPC5200,
  214. MSCAN_TYPE_MPC5121
  215. };
  216. #define BTR0_BRP_MASK 0x3f
  217. #define BTR0_SJW_SHIFT 6
  218. #define BTR0_SJW_MASK (0x3 << BTR0_SJW_SHIFT)
  219. #define BTR1_TSEG1_MASK 0xf
  220. #define BTR1_TSEG2_SHIFT 4
  221. #define BTR1_TSEG2_MASK (0x7 << BTR1_TSEG2_SHIFT)
  222. #define BTR1_SAM_SHIFT 7
  223. #define BTR0_SET_BRP(brp) (((brp) - 1) & BTR0_BRP_MASK)
  224. #define BTR0_SET_SJW(sjw) ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
  225. BTR0_SJW_MASK)
  226. #define BTR1_SET_TSEG1(tseg1) (((tseg1) - 1) & BTR1_TSEG1_MASK)
  227. #define BTR1_SET_TSEG2(tseg2) ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
  228. BTR1_TSEG2_MASK)
  229. #define BTR1_SET_SAM(sam) ((sam) ? 1 << BTR1_SAM_SHIFT : 0)
  230. #define F_RX_PROGRESS 0
  231. #define F_TX_PROGRESS 1
  232. #define F_TX_WAIT_ALL 2
  233. #define TX_QUEUE_SIZE 3
  234. struct tx_queue_entry {
  235. struct list_head list;
  236. u8 mask;
  237. u8 id;
  238. };
  239. struct mscan_priv {
  240. struct can_priv can; /* must be the first member */
  241. unsigned int type; /* MSCAN type variants */
  242. unsigned long flags;
  243. void __iomem *reg_base; /* ioremap'ed address to registers */
  244. struct clk *clk_ipg; /* clock for registers */
  245. struct clk *clk_can; /* clock for bitrates */
  246. u8 shadow_statflg;
  247. u8 shadow_canrier;
  248. u8 cur_pri;
  249. u8 prev_buf_id;
  250. u8 tx_active;
  251. struct list_head tx_head;
  252. struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
  253. struct napi_struct napi;
  254. };
  255. struct net_device *alloc_mscandev(void);
  256. int register_mscandev(struct net_device *dev, int mscan_clksrc);
  257. void unregister_mscandev(struct net_device *dev);
  258. #endif /* __MSCAN_H__ */