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android_kernel_...
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drivers
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mmc
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host
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sdhci-esdhc.h

sdhci-esdhc.h 3.0 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Freescale eSDHC controller driver generics for OF and pltfm.
    4. 

  4.  *
    5. 

  5.  * Copyright (c) 2007 Freescale Semiconductor, Inc.
    6. 

  6.  * Copyright (c) 2009 MontaVista Software, Inc.
    7. 

  7.  * Copyright (c) 2010 Pengutronix e.K.
    8. 

  8.  * Copyright 2020 NXP
    9. 

  9.  *   Author: Wolfram Sang <[email protected]>
    10. 

  10.  */
    11. 

  11. 

  12. #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
    13. 

  13. #define _DRIVERS_MMC_SDHCI_ESDHC_H
    14. 

  14. 

  15. /*
    16. 

  16.  * Ops and quirks for the Freescale eSDHC controller.
    17. 

  17.  */
    18. 

  18. 

  19. #define ESDHC_DEFAULT_QUIRKS	(SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
    20. 

  20. 				SDHCI_QUIRK_32BIT_DMA_ADDR | \
    21. 

  21. 				SDHCI_QUIRK_NO_BUSY_IRQ | \
    22. 

  22. 				SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
    23. 

  23. 				SDHCI_QUIRK_PIO_NEEDS_DELAY | \
    24. 

  24. 				SDHCI_QUIRK_NO_HISPD_BIT)
    25. 

  25. 

  26. /* pltfm-specific */
    27. 

  27. #define ESDHC_HOST_CONTROL_LE	0x20
    28. 

  28. 

  29. /*
    30. 

  30.  * eSDHC register definition
    31. 

  31.  */
    32. 

  32. 

  33. /* Present State Register */
    34. 

  34. #define ESDHC_PRSSTAT			0x24
    35. 

  35. #define ESDHC_CLOCK_GATE_OFF		0x00000080
    36. 

  36. #define ESDHC_CLOCK_STABLE		0x00000008
    37. 

  37. 

  38. /* Protocol Control Register */
    39. 

  39. #define ESDHC_PROCTL			0x28
    40. 

  40. #define ESDHC_VOLT_SEL			0x00000400
    41. 

  41. #define ESDHC_CTRL_4BITBUS		(0x1 << 1)
    42. 

  42. #define ESDHC_CTRL_8BITBUS		(0x2 << 1)
    43. 

  43. #define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)
    44. 

  44. #define ESDHC_HOST_CONTROL_RES		0x01
    45. 

  45. 

  46. /* System Control Register */
    47. 

  47. #define ESDHC_SYSTEM_CONTROL		0x2c
    48. 

  48. #define ESDHC_CLOCK_MASK		0x0000fff0
    49. 

  49. #define ESDHC_PREDIV_SHIFT		8
    50. 

  50. #define ESDHC_DIVIDER_SHIFT		4
    51. 

  51. #define ESDHC_CLOCK_SDCLKEN		0x00000008
    52. 

  52. #define ESDHC_CLOCK_PEREN		0x00000004
    53. 

  53. #define ESDHC_CLOCK_HCKEN		0x00000002
    54. 

  54. #define ESDHC_CLOCK_IPGEN		0x00000001
    55. 

  55. 

  56. /* System Control 2 Register */
    57. 

  57. #define ESDHC_SYSTEM_CONTROL_2		0x3c
    58. 

  58. #define ESDHC_SMPCLKSEL			0x00800000
    59. 

  59. #define ESDHC_EXTN			0x00400000
    60. 

  60. 

  61. /* Host Controller Capabilities Register 2 */
    62. 

  62. #define ESDHC_CAPABILITIES_1		0x114
    63. 

  63. 

  64. /* Tuning Block Control Register */
    65. 

  65. #define ESDHC_TBCTL			0x120
    66. 

  66. #define ESDHC_HS400_WNDW_ADJUST		0x00000040
    67. 

  67. #define ESDHC_HS400_MODE		0x00000010
    68. 

  68. #define ESDHC_TB_EN			0x00000004
    69. 

  69. #define ESDHC_TB_MODE_MASK		0x00000003
    70. 

  70. #define ESDHC_TB_MODE_SW		0x00000003
    71. 

  71. #define ESDHC_TB_MODE_3			0x00000002
    72. 

  72. 

  73. #define ESDHC_TBSTAT			0x124
    74. 

  74. 

  75. #define ESDHC_TBPTR			0x128
    76. 

  76. #define ESDHC_WNDW_STRT_PTR_SHIFT	8
    77. 

  77. #define ESDHC_WNDW_STRT_PTR_MASK	(0x7f << 8)
    78. 

  78. #define ESDHC_WNDW_END_PTR_MASK		0x7f
    79. 

  79. 

  80. /* SD Clock Control Register */
    81. 

  81. #define ESDHC_SDCLKCTL			0x144
    82. 

  82. #define ESDHC_LPBK_CLK_SEL		0x80000000
    83. 

  83. #define ESDHC_CMD_CLK_CTL		0x00008000
    84. 

  84. 

  85. /* SD Timing Control Register */
    86. 

  86. #define ESDHC_SDTIMNGCTL		0x148
    87. 

  87. #define ESDHC_FLW_CTL_BG		0x00008000
    88. 

  88. 

  89. /* DLL Config 0 Register */
    90. 

  90. #define ESDHC_DLLCFG0			0x160
    91. 

  91. #define ESDHC_DLL_ENABLE		0x80000000
    92. 

  92. #define ESDHC_DLL_RESET			0x40000000
    93. 

  93. #define ESDHC_DLL_FREQ_SEL		0x08000000
    94. 

  94. 

  95. /* DLL Config 1 Register */
    96. 

  96. #define ESDHC_DLLCFG1			0x164
    97. 

  97. #define ESDHC_DLL_PD_PULSE_STRETCH_SEL	0x80000000
    98. 

  98. 

  99. /* DLL Status 0 Register */
    100. 

  100. #define ESDHC_DLLSTAT0			0x170
    101. 

  101. #define ESDHC_DLL_STS_SLV_LOCK		0x08000000
    102. 

  102. 

  103. /* Control Register for DMA transfer */
    104. 

  104. #define ESDHC_DMA_SYSCTL		0x40c
    105. 

  105. #define ESDHC_PERIPHERAL_CLK_SEL	0x00080000
    106. 

  106. #define ESDHC_FLUSH_ASYNC_FIFO		0x00040000
    107. 

  107. #define ESDHC_DMA_SNOOP			0x00000040
    108. 

  108. 

  109. #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
    110.