mmc_spi.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Access SD/MMC cards through SPI master controllers
  4. *
  5. * (C) Copyright 2005, Intec Automation,
  6. * Mike Lavender (mike@steroidmicros)
  7. * (C) Copyright 2006-2007, David Brownell
  8. * (C) Copyright 2007, Axis Communications,
  9. * Hans-Peter Nilsson ([email protected])
  10. * (C) Copyright 2007, ATRON electronic GmbH,
  11. * Jan Nikitenko <[email protected]>
  12. */
  13. #include <linux/sched.h>
  14. #include <linux/delay.h>
  15. #include <linux/slab.h>
  16. #include <linux/module.h>
  17. #include <linux/bio.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/crc7.h>
  20. #include <linux/crc-itu-t.h>
  21. #include <linux/scatterlist.h>
  22. #include <linux/mmc/host.h>
  23. #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */
  24. #include <linux/mmc/slot-gpio.h>
  25. #include <linux/spi/spi.h>
  26. #include <linux/spi/mmc_spi.h>
  27. #include <asm/unaligned.h>
  28. /* NOTES:
  29. *
  30. * - For now, we won't try to interoperate with a real mmc/sd/sdio
  31. * controller, although some of them do have hardware support for
  32. * SPI protocol. The main reason for such configs would be mmc-ish
  33. * cards like DataFlash, which don't support that "native" protocol.
  34. *
  35. * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
  36. * switch between driver stacks, and in any case if "native" mode
  37. * is available, it will be faster and hence preferable.
  38. *
  39. * - MMC depends on a different chipselect management policy than the
  40. * SPI interface currently supports for shared bus segments: it needs
  41. * to issue multiple spi_message requests with the chipselect active,
  42. * using the results of one message to decide the next one to issue.
  43. *
  44. * Pending updates to the programming interface, this driver expects
  45. * that it not share the bus with other drivers (precluding conflicts).
  46. *
  47. * - We tell the controller to keep the chipselect active from the
  48. * beginning of an mmc_host_ops.request until the end. So beware
  49. * of SPI controller drivers that mis-handle the cs_change flag!
  50. *
  51. * However, many cards seem OK with chipselect flapping up/down
  52. * during that time ... at least on unshared bus segments.
  53. */
  54. /*
  55. * Local protocol constants, internal to data block protocols.
  56. */
  57. /* Response tokens used to ack each block written: */
  58. #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
  59. #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
  60. #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
  61. #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
  62. /* Read and write blocks start with these tokens and end with crc;
  63. * on error, read tokens act like a subset of R2_SPI_* values.
  64. */
  65. #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
  66. #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
  67. #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
  68. #define MMC_SPI_BLOCKSIZE 512
  69. #define MMC_SPI_R1B_TIMEOUT_MS 3000
  70. #define MMC_SPI_INIT_TIMEOUT_MS 3000
  71. /* One of the critical speed parameters is the amount of data which may
  72. * be transferred in one command. If this value is too low, the SD card
  73. * controller has to do multiple partial block writes (argggh!). With
  74. * today (2008) SD cards there is little speed gain if we transfer more
  75. * than 64 KBytes at a time. So use this value until there is any indication
  76. * that we should do more here.
  77. */
  78. #define MMC_SPI_BLOCKSATONCE 128
  79. /****************************************************************************/
  80. /*
  81. * Local Data Structures
  82. */
  83. /* "scratch" is per-{command,block} data exchanged with the card */
  84. struct scratch {
  85. u8 status[29];
  86. u8 data_token;
  87. __be16 crc_val;
  88. };
  89. struct mmc_spi_host {
  90. struct mmc_host *mmc;
  91. struct spi_device *spi;
  92. unsigned char power_mode;
  93. u16 powerup_msecs;
  94. struct mmc_spi_platform_data *pdata;
  95. /* for bulk data transfers */
  96. struct spi_transfer token, t, crc, early_status;
  97. struct spi_message m;
  98. /* for status readback */
  99. struct spi_transfer status;
  100. struct spi_message readback;
  101. /* underlying DMA-aware controller, or null */
  102. struct device *dma_dev;
  103. /* buffer used for commands and for message "overhead" */
  104. struct scratch *data;
  105. dma_addr_t data_dma;
  106. /* Specs say to write ones most of the time, even when the card
  107. * has no need to read its input data; and many cards won't care.
  108. * This is our source of those ones.
  109. */
  110. void *ones;
  111. dma_addr_t ones_dma;
  112. };
  113. /****************************************************************************/
  114. /*
  115. * MMC-over-SPI protocol glue, used by the MMC stack interface
  116. */
  117. static inline int mmc_cs_off(struct mmc_spi_host *host)
  118. {
  119. /* chipselect will always be inactive after setup() */
  120. return spi_setup(host->spi);
  121. }
  122. static int
  123. mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
  124. {
  125. int status;
  126. if (len > sizeof(*host->data)) {
  127. WARN_ON(1);
  128. return -EIO;
  129. }
  130. host->status.len = len;
  131. if (host->dma_dev)
  132. dma_sync_single_for_device(host->dma_dev,
  133. host->data_dma, sizeof(*host->data),
  134. DMA_FROM_DEVICE);
  135. status = spi_sync_locked(host->spi, &host->readback);
  136. if (host->dma_dev)
  137. dma_sync_single_for_cpu(host->dma_dev,
  138. host->data_dma, sizeof(*host->data),
  139. DMA_FROM_DEVICE);
  140. return status;
  141. }
  142. static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
  143. unsigned n, u8 byte)
  144. {
  145. u8 *cp = host->data->status;
  146. unsigned long start = jiffies;
  147. do {
  148. int status;
  149. unsigned i;
  150. status = mmc_spi_readbytes(host, n);
  151. if (status < 0)
  152. return status;
  153. for (i = 0; i < n; i++) {
  154. if (cp[i] != byte)
  155. return cp[i];
  156. }
  157. /* If we need long timeouts, we may release the CPU */
  158. cond_resched();
  159. } while (time_is_after_jiffies(start + timeout));
  160. return -ETIMEDOUT;
  161. }
  162. static inline int
  163. mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
  164. {
  165. return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
  166. }
  167. static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
  168. {
  169. return mmc_spi_skip(host, timeout, 1, 0xff);
  170. }
  171. /*
  172. * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
  173. * hosts return! The low byte holds R1_SPI bits. The next byte may hold
  174. * R2_SPI bits ... for SEND_STATUS, or after data read errors.
  175. *
  176. * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
  177. * newer cards R7 (IF_COND).
  178. */
  179. static char *maptype(struct mmc_command *cmd)
  180. {
  181. switch (mmc_spi_resp_type(cmd)) {
  182. case MMC_RSP_SPI_R1: return "R1";
  183. case MMC_RSP_SPI_R1B: return "R1B";
  184. case MMC_RSP_SPI_R2: return "R2/R5";
  185. case MMC_RSP_SPI_R3: return "R3/R4/R7";
  186. default: return "?";
  187. }
  188. }
  189. /* return zero, else negative errno after setting cmd->error */
  190. static int mmc_spi_response_get(struct mmc_spi_host *host,
  191. struct mmc_command *cmd, int cs_on)
  192. {
  193. unsigned long timeout_ms;
  194. u8 *cp = host->data->status;
  195. u8 *end = cp + host->t.len;
  196. int value = 0;
  197. int bitshift;
  198. u8 leftover = 0;
  199. unsigned short rotator;
  200. int i;
  201. char tag[32];
  202. snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s",
  203. cmd->opcode, maptype(cmd));
  204. /* Except for data block reads, the whole response will already
  205. * be stored in the scratch buffer. It's somewhere after the
  206. * command and the first byte we read after it. We ignore that
  207. * first byte. After STOP_TRANSMISSION command it may include
  208. * two data bits, but otherwise it's all ones.
  209. */
  210. cp += 8;
  211. while (cp < end && *cp == 0xff)
  212. cp++;
  213. /* Data block reads (R1 response types) may need more data... */
  214. if (cp == end) {
  215. cp = host->data->status;
  216. end = cp+1;
  217. /* Card sends N(CR) (== 1..8) bytes of all-ones then one
  218. * status byte ... and we already scanned 2 bytes.
  219. *
  220. * REVISIT block read paths use nasty byte-at-a-time I/O
  221. * so it can always DMA directly into the target buffer.
  222. * It'd probably be better to memcpy() the first chunk and
  223. * avoid extra i/o calls...
  224. *
  225. * Note we check for more than 8 bytes, because in practice,
  226. * some SD cards are slow...
  227. */
  228. for (i = 2; i < 16; i++) {
  229. value = mmc_spi_readbytes(host, 1);
  230. if (value < 0)
  231. goto done;
  232. if (*cp != 0xff)
  233. goto checkstatus;
  234. }
  235. value = -ETIMEDOUT;
  236. goto done;
  237. }
  238. checkstatus:
  239. bitshift = 0;
  240. if (*cp & 0x80) {
  241. /* Houston, we have an ugly card with a bit-shifted response */
  242. rotator = *cp++ << 8;
  243. /* read the next byte */
  244. if (cp == end) {
  245. value = mmc_spi_readbytes(host, 1);
  246. if (value < 0)
  247. goto done;
  248. cp = host->data->status;
  249. end = cp+1;
  250. }
  251. rotator |= *cp++;
  252. while (rotator & 0x8000) {
  253. bitshift++;
  254. rotator <<= 1;
  255. }
  256. cmd->resp[0] = rotator >> 8;
  257. leftover = rotator;
  258. } else {
  259. cmd->resp[0] = *cp++;
  260. }
  261. cmd->error = 0;
  262. /* Status byte: the entire seven-bit R1 response. */
  263. if (cmd->resp[0] != 0) {
  264. if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
  265. & cmd->resp[0])
  266. value = -EFAULT; /* Bad address */
  267. else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
  268. value = -ENOSYS; /* Function not implemented */
  269. else if (R1_SPI_COM_CRC & cmd->resp[0])
  270. value = -EILSEQ; /* Illegal byte sequence */
  271. else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
  272. & cmd->resp[0])
  273. value = -EIO; /* I/O error */
  274. /* else R1_SPI_IDLE, "it's resetting" */
  275. }
  276. switch (mmc_spi_resp_type(cmd)) {
  277. /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
  278. * and less-common stuff like various erase operations.
  279. */
  280. case MMC_RSP_SPI_R1B:
  281. /* maybe we read all the busy tokens already */
  282. while (cp < end && *cp == 0)
  283. cp++;
  284. if (cp == end) {
  285. timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
  286. MMC_SPI_R1B_TIMEOUT_MS;
  287. mmc_spi_wait_unbusy(host, msecs_to_jiffies(timeout_ms));
  288. }
  289. break;
  290. /* SPI R2 == R1 + second status byte; SEND_STATUS
  291. * SPI R5 == R1 + data byte; IO_RW_DIRECT
  292. */
  293. case MMC_RSP_SPI_R2:
  294. /* read the next byte */
  295. if (cp == end) {
  296. value = mmc_spi_readbytes(host, 1);
  297. if (value < 0)
  298. goto done;
  299. cp = host->data->status;
  300. end = cp+1;
  301. }
  302. if (bitshift) {
  303. rotator = leftover << 8;
  304. rotator |= *cp << bitshift;
  305. cmd->resp[0] |= (rotator & 0xFF00);
  306. } else {
  307. cmd->resp[0] |= *cp << 8;
  308. }
  309. break;
  310. /* SPI R3, R4, or R7 == R1 + 4 bytes */
  311. case MMC_RSP_SPI_R3:
  312. rotator = leftover << 8;
  313. cmd->resp[1] = 0;
  314. for (i = 0; i < 4; i++) {
  315. cmd->resp[1] <<= 8;
  316. /* read the next byte */
  317. if (cp == end) {
  318. value = mmc_spi_readbytes(host, 1);
  319. if (value < 0)
  320. goto done;
  321. cp = host->data->status;
  322. end = cp+1;
  323. }
  324. if (bitshift) {
  325. rotator |= *cp++ << bitshift;
  326. cmd->resp[1] |= (rotator >> 8);
  327. rotator <<= 8;
  328. } else {
  329. cmd->resp[1] |= *cp++;
  330. }
  331. }
  332. break;
  333. /* SPI R1 == just one status byte */
  334. case MMC_RSP_SPI_R1:
  335. break;
  336. default:
  337. dev_dbg(&host->spi->dev, "bad response type %04x\n",
  338. mmc_spi_resp_type(cmd));
  339. if (value >= 0)
  340. value = -EINVAL;
  341. goto done;
  342. }
  343. if (value < 0)
  344. dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
  345. tag, cmd->resp[0], cmd->resp[1]);
  346. /* disable chipselect on errors and some success cases */
  347. if (value >= 0 && cs_on)
  348. return value;
  349. done:
  350. if (value < 0)
  351. cmd->error = value;
  352. mmc_cs_off(host);
  353. return value;
  354. }
  355. /* Issue command and read its response.
  356. * Returns zero on success, negative for error.
  357. *
  358. * On error, caller must cope with mmc core retry mechanism. That
  359. * means immediate low-level resubmit, which affects the bus lock...
  360. */
  361. static int
  362. mmc_spi_command_send(struct mmc_spi_host *host,
  363. struct mmc_request *mrq,
  364. struct mmc_command *cmd, int cs_on)
  365. {
  366. struct scratch *data = host->data;
  367. u8 *cp = data->status;
  368. int status;
  369. struct spi_transfer *t;
  370. /* We can handle most commands (except block reads) in one full
  371. * duplex I/O operation before either starting the next transfer
  372. * (data block or command) or else deselecting the card.
  373. *
  374. * First, write 7 bytes:
  375. * - an all-ones byte to ensure the card is ready
  376. * - opcode byte (plus start and transmission bits)
  377. * - four bytes of big-endian argument
  378. * - crc7 (plus end bit) ... always computed, it's cheap
  379. *
  380. * We init the whole buffer to all-ones, which is what we need
  381. * to write while we're reading (later) response data.
  382. */
  383. memset(cp, 0xff, sizeof(data->status));
  384. cp[1] = 0x40 | cmd->opcode;
  385. put_unaligned_be32(cmd->arg, cp + 2);
  386. cp[6] = crc7_be(0, cp + 1, 5) | 0x01;
  387. cp += 7;
  388. /* Then, read up to 13 bytes (while writing all-ones):
  389. * - N(CR) (== 1..8) bytes of all-ones
  390. * - status byte (for all response types)
  391. * - the rest of the response, either:
  392. * + nothing, for R1 or R1B responses
  393. * + second status byte, for R2 responses
  394. * + four data bytes, for R3 and R7 responses
  395. *
  396. * Finally, read some more bytes ... in the nice cases we know in
  397. * advance how many, and reading 1 more is always OK:
  398. * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
  399. * - N(RC) (== 1..N) bytes of all-ones, before next command
  400. * - N(WR) (== 1..N) bytes of all-ones, before data write
  401. *
  402. * So in those cases one full duplex I/O of at most 21 bytes will
  403. * handle the whole command, leaving the card ready to receive a
  404. * data block or new command. We do that whenever we can, shaving
  405. * CPU and IRQ costs (especially when using DMA or FIFOs).
  406. *
  407. * There are two other cases, where it's not generally practical
  408. * to rely on a single I/O:
  409. *
  410. * - R1B responses need at least N(EC) bytes of all-zeroes.
  411. *
  412. * In this case we can *try* to fit it into one I/O, then
  413. * maybe read more data later.
  414. *
  415. * - Data block reads are more troublesome, since a variable
  416. * number of padding bytes precede the token and data.
  417. * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
  418. * + N(AC) (== 1..many) bytes of all-ones
  419. *
  420. * In this case we currently only have minimal speedups here:
  421. * when N(CR) == 1 we can avoid I/O in response_get().
  422. */
  423. if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
  424. cp += 2; /* min(N(CR)) + status */
  425. /* R1 */
  426. } else {
  427. cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */
  428. if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */
  429. cp++;
  430. else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */
  431. cp += 4;
  432. else if (cmd->flags & MMC_RSP_BUSY) /* R1B */
  433. cp = data->status + sizeof(data->status);
  434. /* else: R1 (most commands) */
  435. }
  436. dev_dbg(&host->spi->dev, " CMD%d, resp %s\n",
  437. cmd->opcode, maptype(cmd));
  438. /* send command, leaving chipselect active */
  439. spi_message_init(&host->m);
  440. t = &host->t;
  441. memset(t, 0, sizeof(*t));
  442. t->tx_buf = t->rx_buf = data->status;
  443. t->tx_dma = t->rx_dma = host->data_dma;
  444. t->len = cp - data->status;
  445. t->cs_change = 1;
  446. spi_message_add_tail(t, &host->m);
  447. if (host->dma_dev) {
  448. host->m.is_dma_mapped = 1;
  449. dma_sync_single_for_device(host->dma_dev,
  450. host->data_dma, sizeof(*host->data),
  451. DMA_BIDIRECTIONAL);
  452. }
  453. status = spi_sync_locked(host->spi, &host->m);
  454. if (host->dma_dev)
  455. dma_sync_single_for_cpu(host->dma_dev,
  456. host->data_dma, sizeof(*host->data),
  457. DMA_BIDIRECTIONAL);
  458. if (status < 0) {
  459. dev_dbg(&host->spi->dev, " ... write returned %d\n", status);
  460. cmd->error = status;
  461. return status;
  462. }
  463. /* after no-data commands and STOP_TRANSMISSION, chipselect off */
  464. return mmc_spi_response_get(host, cmd, cs_on);
  465. }
  466. /* Build data message with up to four separate transfers. For TX, we
  467. * start by writing the data token. And in most cases, we finish with
  468. * a status transfer.
  469. *
  470. * We always provide TX data for data and CRC. The MMC/SD protocol
  471. * requires us to write ones; but Linux defaults to writing zeroes;
  472. * so we explicitly initialize it to all ones on RX paths.
  473. *
  474. * We also handle DMA mapping, so the underlying SPI controller does
  475. * not need to (re)do it for each message.
  476. */
  477. static void
  478. mmc_spi_setup_data_message(
  479. struct mmc_spi_host *host,
  480. bool multiple,
  481. enum dma_data_direction direction)
  482. {
  483. struct spi_transfer *t;
  484. struct scratch *scratch = host->data;
  485. dma_addr_t dma = host->data_dma;
  486. spi_message_init(&host->m);
  487. if (dma)
  488. host->m.is_dma_mapped = 1;
  489. /* for reads, readblock() skips 0xff bytes before finding
  490. * the token; for writes, this transfer issues that token.
  491. */
  492. if (direction == DMA_TO_DEVICE) {
  493. t = &host->token;
  494. memset(t, 0, sizeof(*t));
  495. t->len = 1;
  496. if (multiple)
  497. scratch->data_token = SPI_TOKEN_MULTI_WRITE;
  498. else
  499. scratch->data_token = SPI_TOKEN_SINGLE;
  500. t->tx_buf = &scratch->data_token;
  501. if (dma)
  502. t->tx_dma = dma + offsetof(struct scratch, data_token);
  503. spi_message_add_tail(t, &host->m);
  504. }
  505. /* Body of transfer is buffer, then CRC ...
  506. * either TX-only, or RX with TX-ones.
  507. */
  508. t = &host->t;
  509. memset(t, 0, sizeof(*t));
  510. t->tx_buf = host->ones;
  511. t->tx_dma = host->ones_dma;
  512. /* length and actual buffer info are written later */
  513. spi_message_add_tail(t, &host->m);
  514. t = &host->crc;
  515. memset(t, 0, sizeof(*t));
  516. t->len = 2;
  517. if (direction == DMA_TO_DEVICE) {
  518. /* the actual CRC may get written later */
  519. t->tx_buf = &scratch->crc_val;
  520. if (dma)
  521. t->tx_dma = dma + offsetof(struct scratch, crc_val);
  522. } else {
  523. t->tx_buf = host->ones;
  524. t->tx_dma = host->ones_dma;
  525. t->rx_buf = &scratch->crc_val;
  526. if (dma)
  527. t->rx_dma = dma + offsetof(struct scratch, crc_val);
  528. }
  529. spi_message_add_tail(t, &host->m);
  530. /*
  531. * A single block read is followed by N(EC) [0+] all-ones bytes
  532. * before deselect ... don't bother.
  533. *
  534. * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
  535. * the next block is read, or a STOP_TRANSMISSION is issued. We'll
  536. * collect that single byte, so readblock() doesn't need to.
  537. *
  538. * For a write, the one-byte data response follows immediately, then
  539. * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
  540. * Then single block reads may deselect, and multiblock ones issue
  541. * the next token (next data block, or STOP_TRAN). We can try to
  542. * minimize I/O ops by using a single read to collect end-of-busy.
  543. */
  544. if (multiple || direction == DMA_TO_DEVICE) {
  545. t = &host->early_status;
  546. memset(t, 0, sizeof(*t));
  547. t->len = (direction == DMA_TO_DEVICE) ? sizeof(scratch->status) : 1;
  548. t->tx_buf = host->ones;
  549. t->tx_dma = host->ones_dma;
  550. t->rx_buf = scratch->status;
  551. if (dma)
  552. t->rx_dma = dma + offsetof(struct scratch, status);
  553. t->cs_change = 1;
  554. spi_message_add_tail(t, &host->m);
  555. }
  556. }
  557. /*
  558. * Write one block:
  559. * - caller handled preceding N(WR) [1+] all-ones bytes
  560. * - data block
  561. * + token
  562. * + data bytes
  563. * + crc16
  564. * - an all-ones byte ... card writes a data-response byte
  565. * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
  566. *
  567. * Return negative errno, else success.
  568. */
  569. static int
  570. mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
  571. unsigned long timeout)
  572. {
  573. struct spi_device *spi = host->spi;
  574. int status, i;
  575. struct scratch *scratch = host->data;
  576. u32 pattern;
  577. if (host->mmc->use_spi_crc)
  578. scratch->crc_val = cpu_to_be16(crc_itu_t(0, t->tx_buf, t->len));
  579. if (host->dma_dev)
  580. dma_sync_single_for_device(host->dma_dev,
  581. host->data_dma, sizeof(*scratch),
  582. DMA_BIDIRECTIONAL);
  583. status = spi_sync_locked(spi, &host->m);
  584. if (status != 0) {
  585. dev_dbg(&spi->dev, "write error (%d)\n", status);
  586. return status;
  587. }
  588. if (host->dma_dev)
  589. dma_sync_single_for_cpu(host->dma_dev,
  590. host->data_dma, sizeof(*scratch),
  591. DMA_BIDIRECTIONAL);
  592. /*
  593. * Get the transmission data-response reply. It must follow
  594. * immediately after the data block we transferred. This reply
  595. * doesn't necessarily tell whether the write operation succeeded;
  596. * it just says if the transmission was ok and whether *earlier*
  597. * writes succeeded; see the standard.
  598. *
  599. * In practice, there are (even modern SDHC-)cards which are late
  600. * in sending the response, and miss the time frame by a few bits,
  601. * so we have to cope with this situation and check the response
  602. * bit-by-bit. Arggh!!!
  603. */
  604. pattern = get_unaligned_be32(scratch->status);
  605. /* First 3 bit of pattern are undefined */
  606. pattern |= 0xE0000000;
  607. /* left-adjust to leading 0 bit */
  608. while (pattern & 0x80000000)
  609. pattern <<= 1;
  610. /* right-adjust for pattern matching. Code is in bit 4..0 now. */
  611. pattern >>= 27;
  612. switch (pattern) {
  613. case SPI_RESPONSE_ACCEPTED:
  614. status = 0;
  615. break;
  616. case SPI_RESPONSE_CRC_ERR:
  617. /* host shall then issue MMC_STOP_TRANSMISSION */
  618. status = -EILSEQ;
  619. break;
  620. case SPI_RESPONSE_WRITE_ERR:
  621. /* host shall then issue MMC_STOP_TRANSMISSION,
  622. * and should MMC_SEND_STATUS to sort it out
  623. */
  624. status = -EIO;
  625. break;
  626. default:
  627. status = -EPROTO;
  628. break;
  629. }
  630. if (status != 0) {
  631. dev_dbg(&spi->dev, "write error %02x (%d)\n",
  632. scratch->status[0], status);
  633. return status;
  634. }
  635. t->tx_buf += t->len;
  636. if (host->dma_dev)
  637. t->tx_dma += t->len;
  638. /* Return when not busy. If we didn't collect that status yet,
  639. * we'll need some more I/O.
  640. */
  641. for (i = 4; i < sizeof(scratch->status); i++) {
  642. /* card is non-busy if the most recent bit is 1 */
  643. if (scratch->status[i] & 0x01)
  644. return 0;
  645. }
  646. return mmc_spi_wait_unbusy(host, timeout);
  647. }
  648. /*
  649. * Read one block:
  650. * - skip leading all-ones bytes ... either
  651. * + N(AC) [1..f(clock,CSD)] usually, else
  652. * + N(CX) [0..8] when reading CSD or CID
  653. * - data block
  654. * + token ... if error token, no data or crc
  655. * + data bytes
  656. * + crc16
  657. *
  658. * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
  659. * before dropping chipselect.
  660. *
  661. * For multiblock reads, caller either reads the next block or issues a
  662. * STOP_TRANSMISSION command.
  663. */
  664. static int
  665. mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
  666. unsigned long timeout)
  667. {
  668. struct spi_device *spi = host->spi;
  669. int status;
  670. struct scratch *scratch = host->data;
  671. unsigned int bitshift;
  672. u8 leftover;
  673. /* At least one SD card sends an all-zeroes byte when N(CX)
  674. * applies, before the all-ones bytes ... just cope with that.
  675. */
  676. status = mmc_spi_readbytes(host, 1);
  677. if (status < 0)
  678. return status;
  679. status = scratch->status[0];
  680. if (status == 0xff || status == 0)
  681. status = mmc_spi_readtoken(host, timeout);
  682. if (status < 0) {
  683. dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
  684. return status;
  685. }
  686. /* The token may be bit-shifted...
  687. * the first 0-bit precedes the data stream.
  688. */
  689. bitshift = 7;
  690. while (status & 0x80) {
  691. status <<= 1;
  692. bitshift--;
  693. }
  694. leftover = status << 1;
  695. if (host->dma_dev) {
  696. dma_sync_single_for_device(host->dma_dev,
  697. host->data_dma, sizeof(*scratch),
  698. DMA_BIDIRECTIONAL);
  699. dma_sync_single_for_device(host->dma_dev,
  700. t->rx_dma, t->len,
  701. DMA_FROM_DEVICE);
  702. }
  703. status = spi_sync_locked(spi, &host->m);
  704. if (status < 0) {
  705. dev_dbg(&spi->dev, "read error %d\n", status);
  706. return status;
  707. }
  708. if (host->dma_dev) {
  709. dma_sync_single_for_cpu(host->dma_dev,
  710. host->data_dma, sizeof(*scratch),
  711. DMA_BIDIRECTIONAL);
  712. dma_sync_single_for_cpu(host->dma_dev,
  713. t->rx_dma, t->len,
  714. DMA_FROM_DEVICE);
  715. }
  716. if (bitshift) {
  717. /* Walk through the data and the crc and do
  718. * all the magic to get byte-aligned data.
  719. */
  720. u8 *cp = t->rx_buf;
  721. unsigned int len;
  722. unsigned int bitright = 8 - bitshift;
  723. u8 temp;
  724. for (len = t->len; len; len--) {
  725. temp = *cp;
  726. *cp++ = leftover | (temp >> bitshift);
  727. leftover = temp << bitright;
  728. }
  729. cp = (u8 *) &scratch->crc_val;
  730. temp = *cp;
  731. *cp++ = leftover | (temp >> bitshift);
  732. leftover = temp << bitright;
  733. temp = *cp;
  734. *cp = leftover | (temp >> bitshift);
  735. }
  736. if (host->mmc->use_spi_crc) {
  737. u16 crc = crc_itu_t(0, t->rx_buf, t->len);
  738. be16_to_cpus(&scratch->crc_val);
  739. if (scratch->crc_val != crc) {
  740. dev_dbg(&spi->dev,
  741. "read - crc error: crc_val=0x%04x, computed=0x%04x len=%d\n",
  742. scratch->crc_val, crc, t->len);
  743. return -EILSEQ;
  744. }
  745. }
  746. t->rx_buf += t->len;
  747. if (host->dma_dev)
  748. t->rx_dma += t->len;
  749. return 0;
  750. }
  751. /*
  752. * An MMC/SD data stage includes one or more blocks, optional CRCs,
  753. * and inline handshaking. That handhaking makes it unlike most
  754. * other SPI protocol stacks.
  755. */
  756. static void
  757. mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
  758. struct mmc_data *data, u32 blk_size)
  759. {
  760. struct spi_device *spi = host->spi;
  761. struct device *dma_dev = host->dma_dev;
  762. struct spi_transfer *t;
  763. enum dma_data_direction direction = mmc_get_dma_dir(data);
  764. struct scatterlist *sg;
  765. unsigned n_sg;
  766. bool multiple = (data->blocks > 1);
  767. const char *write_or_read = (direction == DMA_TO_DEVICE) ? "write" : "read";
  768. u32 clock_rate;
  769. unsigned long timeout;
  770. mmc_spi_setup_data_message(host, multiple, direction);
  771. t = &host->t;
  772. if (t->speed_hz)
  773. clock_rate = t->speed_hz;
  774. else
  775. clock_rate = spi->max_speed_hz;
  776. timeout = data->timeout_ns / 1000 +
  777. data->timeout_clks * 1000000 / clock_rate;
  778. timeout = usecs_to_jiffies((unsigned int)timeout) + 1;
  779. /* Handle scatterlist segments one at a time, with synch for
  780. * each 512-byte block
  781. */
  782. for_each_sg(data->sg, sg, data->sg_len, n_sg) {
  783. int status = 0;
  784. dma_addr_t dma_addr = 0;
  785. void *kmap_addr;
  786. unsigned length = sg->length;
  787. enum dma_data_direction dir = direction;
  788. /* set up dma mapping for controller drivers that might
  789. * use DMA ... though they may fall back to PIO
  790. */
  791. if (dma_dev) {
  792. /* never invalidate whole *shared* pages ... */
  793. if ((sg->offset != 0 || length != PAGE_SIZE)
  794. && dir == DMA_FROM_DEVICE)
  795. dir = DMA_BIDIRECTIONAL;
  796. dma_addr = dma_map_page(dma_dev, sg_page(sg), 0,
  797. PAGE_SIZE, dir);
  798. if (dma_mapping_error(dma_dev, dma_addr)) {
  799. data->error = -EFAULT;
  800. break;
  801. }
  802. if (direction == DMA_TO_DEVICE)
  803. t->tx_dma = dma_addr + sg->offset;
  804. else
  805. t->rx_dma = dma_addr + sg->offset;
  806. }
  807. /* allow pio too; we don't allow highmem */
  808. kmap_addr = kmap(sg_page(sg));
  809. if (direction == DMA_TO_DEVICE)
  810. t->tx_buf = kmap_addr + sg->offset;
  811. else
  812. t->rx_buf = kmap_addr + sg->offset;
  813. /* transfer each block, and update request status */
  814. while (length) {
  815. t->len = min(length, blk_size);
  816. dev_dbg(&spi->dev, " %s block, %d bytes\n", write_or_read, t->len);
  817. if (direction == DMA_TO_DEVICE)
  818. status = mmc_spi_writeblock(host, t, timeout);
  819. else
  820. status = mmc_spi_readblock(host, t, timeout);
  821. if (status < 0)
  822. break;
  823. data->bytes_xfered += t->len;
  824. length -= t->len;
  825. if (!multiple)
  826. break;
  827. }
  828. /* discard mappings */
  829. if (direction == DMA_FROM_DEVICE)
  830. flush_dcache_page(sg_page(sg));
  831. kunmap(sg_page(sg));
  832. if (dma_dev)
  833. dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);
  834. if (status < 0) {
  835. data->error = status;
  836. dev_dbg(&spi->dev, "%s status %d\n", write_or_read, status);
  837. break;
  838. }
  839. }
  840. /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
  841. * can be issued before multiblock writes. Unlike its more widely
  842. * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
  843. * that can affect the STOP_TRAN logic. Complete (and current)
  844. * MMC specs should sort that out before Linux starts using CMD23.
  845. */
  846. if (direction == DMA_TO_DEVICE && multiple) {
  847. struct scratch *scratch = host->data;
  848. int tmp;
  849. const unsigned statlen = sizeof(scratch->status);
  850. dev_dbg(&spi->dev, " STOP_TRAN\n");
  851. /* Tweak the per-block message we set up earlier by morphing
  852. * it to hold single buffer with the token followed by some
  853. * all-ones bytes ... skip N(BR) (0..1), scan the rest for
  854. * "not busy any longer" status, and leave chip selected.
  855. */
  856. INIT_LIST_HEAD(&host->m.transfers);
  857. list_add(&host->early_status.transfer_list,
  858. &host->m.transfers);
  859. memset(scratch->status, 0xff, statlen);
  860. scratch->status[0] = SPI_TOKEN_STOP_TRAN;
  861. host->early_status.tx_buf = host->early_status.rx_buf;
  862. host->early_status.tx_dma = host->early_status.rx_dma;
  863. host->early_status.len = statlen;
  864. if (host->dma_dev)
  865. dma_sync_single_for_device(host->dma_dev,
  866. host->data_dma, sizeof(*scratch),
  867. DMA_BIDIRECTIONAL);
  868. tmp = spi_sync_locked(spi, &host->m);
  869. if (host->dma_dev)
  870. dma_sync_single_for_cpu(host->dma_dev,
  871. host->data_dma, sizeof(*scratch),
  872. DMA_BIDIRECTIONAL);
  873. if (tmp < 0) {
  874. if (!data->error)
  875. data->error = tmp;
  876. return;
  877. }
  878. /* Ideally we collected "not busy" status with one I/O,
  879. * avoiding wasteful byte-at-a-time scanning... but more
  880. * I/O is often needed.
  881. */
  882. for (tmp = 2; tmp < statlen; tmp++) {
  883. if (scratch->status[tmp] != 0)
  884. return;
  885. }
  886. tmp = mmc_spi_wait_unbusy(host, timeout);
  887. if (tmp < 0 && !data->error)
  888. data->error = tmp;
  889. }
  890. }
  891. /****************************************************************************/
  892. /*
  893. * MMC driver implementation -- the interface to the MMC stack
  894. */
  895. static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
  896. {
  897. struct mmc_spi_host *host = mmc_priv(mmc);
  898. int status = -EINVAL;
  899. int crc_retry = 5;
  900. struct mmc_command stop;
  901. #ifdef DEBUG
  902. /* MMC core and layered drivers *MUST* issue SPI-aware commands */
  903. {
  904. struct mmc_command *cmd;
  905. int invalid = 0;
  906. cmd = mrq->cmd;
  907. if (!mmc_spi_resp_type(cmd)) {
  908. dev_dbg(&host->spi->dev, "bogus command\n");
  909. cmd->error = -EINVAL;
  910. invalid = 1;
  911. }
  912. cmd = mrq->stop;
  913. if (cmd && !mmc_spi_resp_type(cmd)) {
  914. dev_dbg(&host->spi->dev, "bogus STOP command\n");
  915. cmd->error = -EINVAL;
  916. invalid = 1;
  917. }
  918. if (invalid) {
  919. dump_stack();
  920. mmc_request_done(host->mmc, mrq);
  921. return;
  922. }
  923. }
  924. #endif
  925. /* request exclusive bus access */
  926. spi_bus_lock(host->spi->master);
  927. crc_recover:
  928. /* issue command; then optionally data and stop */
  929. status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
  930. if (status == 0 && mrq->data) {
  931. mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
  932. /*
  933. * The SPI bus is not always reliable for large data transfers.
  934. * If an occasional crc error is reported by the SD device with
  935. * data read/write over SPI, it may be recovered by repeating
  936. * the last SD command again. The retry count is set to 5 to
  937. * ensure the driver passes stress tests.
  938. */
  939. if (mrq->data->error == -EILSEQ && crc_retry) {
  940. stop.opcode = MMC_STOP_TRANSMISSION;
  941. stop.arg = 0;
  942. stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
  943. status = mmc_spi_command_send(host, mrq, &stop, 0);
  944. crc_retry--;
  945. mrq->data->error = 0;
  946. goto crc_recover;
  947. }
  948. if (mrq->stop)
  949. status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
  950. else
  951. mmc_cs_off(host);
  952. }
  953. /* release the bus */
  954. spi_bus_unlock(host->spi->master);
  955. mmc_request_done(host->mmc, mrq);
  956. }
  957. /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
  958. *
  959. * NOTE that here we can't know that the card has just been powered up;
  960. * not all MMC/SD sockets support power switching.
  961. *
  962. * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
  963. * this doesn't seem to do the right thing at all...
  964. */
  965. static void mmc_spi_initsequence(struct mmc_spi_host *host)
  966. {
  967. /* Try to be very sure any previous command has completed;
  968. * wait till not-busy, skip debris from any old commands.
  969. */
  970. mmc_spi_wait_unbusy(host, msecs_to_jiffies(MMC_SPI_INIT_TIMEOUT_MS));
  971. mmc_spi_readbytes(host, 10);
  972. /*
  973. * Do a burst with chipselect active-high. We need to do this to
  974. * meet the requirement of 74 clock cycles with both chipselect
  975. * and CMD (MOSI) high before CMD0 ... after the card has been
  976. * powered up to Vdd(min), and so is ready to take commands.
  977. *
  978. * Some cards are particularly needy of this (e.g. Viking "SD256")
  979. * while most others don't seem to care.
  980. *
  981. * Note that this is one of the places MMC/SD plays games with the
  982. * SPI protocol. Another is that when chipselect is released while
  983. * the card returns BUSY status, the clock must issue several cycles
  984. * with chipselect high before the card will stop driving its output.
  985. *
  986. * SPI_CS_HIGH means "asserted" here. In some cases like when using
  987. * GPIOs for chip select, SPI_CS_HIGH is set but this will be logically
  988. * inverted by gpiolib, so if we want to ascertain to drive it high
  989. * we should toggle the default with an XOR as we do here.
  990. */
  991. host->spi->mode ^= SPI_CS_HIGH;
  992. if (spi_setup(host->spi) != 0) {
  993. /* Just warn; most cards work without it. */
  994. dev_warn(&host->spi->dev,
  995. "can't change chip-select polarity\n");
  996. host->spi->mode ^= SPI_CS_HIGH;
  997. } else {
  998. mmc_spi_readbytes(host, 18);
  999. host->spi->mode ^= SPI_CS_HIGH;
  1000. if (spi_setup(host->spi) != 0) {
  1001. /* Wot, we can't get the same setup we had before? */
  1002. dev_err(&host->spi->dev,
  1003. "can't restore chip-select polarity\n");
  1004. }
  1005. }
  1006. }
  1007. static char *mmc_powerstring(u8 power_mode)
  1008. {
  1009. switch (power_mode) {
  1010. case MMC_POWER_OFF: return "off";
  1011. case MMC_POWER_UP: return "up";
  1012. case MMC_POWER_ON: return "on";
  1013. }
  1014. return "?";
  1015. }
  1016. static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1017. {
  1018. struct mmc_spi_host *host = mmc_priv(mmc);
  1019. if (host->power_mode != ios->power_mode) {
  1020. int canpower;
  1021. canpower = host->pdata && host->pdata->setpower;
  1022. dev_dbg(&host->spi->dev, "power %s (%d)%s\n",
  1023. mmc_powerstring(ios->power_mode),
  1024. ios->vdd,
  1025. canpower ? ", can switch" : "");
  1026. /* switch power on/off if possible, accounting for
  1027. * max 250msec powerup time if needed.
  1028. */
  1029. if (canpower) {
  1030. switch (ios->power_mode) {
  1031. case MMC_POWER_OFF:
  1032. case MMC_POWER_UP:
  1033. host->pdata->setpower(&host->spi->dev,
  1034. ios->vdd);
  1035. if (ios->power_mode == MMC_POWER_UP)
  1036. msleep(host->powerup_msecs);
  1037. }
  1038. }
  1039. /* See 6.4.1 in the simplified SD card physical spec 2.0 */
  1040. if (ios->power_mode == MMC_POWER_ON)
  1041. mmc_spi_initsequence(host);
  1042. /* If powering down, ground all card inputs to avoid power
  1043. * delivery from data lines! On a shared SPI bus, this
  1044. * will probably be temporary; 6.4.2 of the simplified SD
  1045. * spec says this must last at least 1msec.
  1046. *
  1047. * - Clock low means CPOL 0, e.g. mode 0
  1048. * - MOSI low comes from writing zero
  1049. * - Chipselect is usually active low...
  1050. */
  1051. if (canpower && ios->power_mode == MMC_POWER_OFF) {
  1052. int mres;
  1053. u8 nullbyte = 0;
  1054. host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
  1055. mres = spi_setup(host->spi);
  1056. if (mres < 0)
  1057. dev_dbg(&host->spi->dev,
  1058. "switch to SPI mode 0 failed\n");
  1059. if (spi_write(host->spi, &nullbyte, 1) < 0)
  1060. dev_dbg(&host->spi->dev,
  1061. "put spi signals to low failed\n");
  1062. /*
  1063. * Now clock should be low due to spi mode 0;
  1064. * MOSI should be low because of written 0x00;
  1065. * chipselect should be low (it is active low)
  1066. * power supply is off, so now MMC is off too!
  1067. *
  1068. * FIXME no, chipselect can be high since the
  1069. * device is inactive and SPI_CS_HIGH is clear...
  1070. */
  1071. msleep(10);
  1072. if (mres == 0) {
  1073. host->spi->mode |= (SPI_CPOL|SPI_CPHA);
  1074. mres = spi_setup(host->spi);
  1075. if (mres < 0)
  1076. dev_dbg(&host->spi->dev,
  1077. "switch back to SPI mode 3 failed\n");
  1078. }
  1079. }
  1080. host->power_mode = ios->power_mode;
  1081. }
  1082. if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
  1083. int status;
  1084. host->spi->max_speed_hz = ios->clock;
  1085. status = spi_setup(host->spi);
  1086. dev_dbg(&host->spi->dev, " clock to %d Hz, %d\n",
  1087. host->spi->max_speed_hz, status);
  1088. }
  1089. }
  1090. static const struct mmc_host_ops mmc_spi_ops = {
  1091. .request = mmc_spi_request,
  1092. .set_ios = mmc_spi_set_ios,
  1093. .get_ro = mmc_gpio_get_ro,
  1094. .get_cd = mmc_gpio_get_cd,
  1095. };
  1096. /****************************************************************************/
  1097. /*
  1098. * SPI driver implementation
  1099. */
  1100. static irqreturn_t
  1101. mmc_spi_detect_irq(int irq, void *mmc)
  1102. {
  1103. struct mmc_spi_host *host = mmc_priv(mmc);
  1104. u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
  1105. mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
  1106. return IRQ_HANDLED;
  1107. }
  1108. #ifdef CONFIG_HAS_DMA
  1109. static int mmc_spi_dma_alloc(struct mmc_spi_host *host)
  1110. {
  1111. struct spi_device *spi = host->spi;
  1112. struct device *dev;
  1113. if (!spi->master->dev.parent->dma_mask)
  1114. return 0;
  1115. dev = spi->master->dev.parent;
  1116. host->ones_dma = dma_map_single(dev, host->ones, MMC_SPI_BLOCKSIZE,
  1117. DMA_TO_DEVICE);
  1118. if (dma_mapping_error(dev, host->ones_dma))
  1119. return -ENOMEM;
  1120. host->data_dma = dma_map_single(dev, host->data, sizeof(*host->data),
  1121. DMA_BIDIRECTIONAL);
  1122. if (dma_mapping_error(dev, host->data_dma)) {
  1123. dma_unmap_single(dev, host->ones_dma, MMC_SPI_BLOCKSIZE,
  1124. DMA_TO_DEVICE);
  1125. return -ENOMEM;
  1126. }
  1127. dma_sync_single_for_cpu(dev, host->data_dma, sizeof(*host->data),
  1128. DMA_BIDIRECTIONAL);
  1129. host->dma_dev = dev;
  1130. return 0;
  1131. }
  1132. static void mmc_spi_dma_free(struct mmc_spi_host *host)
  1133. {
  1134. if (!host->dma_dev)
  1135. return;
  1136. dma_unmap_single(host->dma_dev, host->ones_dma, MMC_SPI_BLOCKSIZE,
  1137. DMA_TO_DEVICE);
  1138. dma_unmap_single(host->dma_dev, host->data_dma, sizeof(*host->data),
  1139. DMA_BIDIRECTIONAL);
  1140. }
  1141. #else
  1142. static inline int mmc_spi_dma_alloc(struct mmc_spi_host *host) { return 0; }
  1143. static inline void mmc_spi_dma_free(struct mmc_spi_host *host) {}
  1144. #endif
  1145. static int mmc_spi_probe(struct spi_device *spi)
  1146. {
  1147. void *ones;
  1148. struct mmc_host *mmc;
  1149. struct mmc_spi_host *host;
  1150. int status;
  1151. bool has_ro = false;
  1152. /* We rely on full duplex transfers, mostly to reduce
  1153. * per-transfer overheads (by making fewer transfers).
  1154. */
  1155. if (spi->master->flags & SPI_MASTER_HALF_DUPLEX)
  1156. return -EINVAL;
  1157. /* MMC and SD specs only seem to care that sampling is on the
  1158. * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
  1159. * should be legit. We'll use mode 0 since the steady state is 0,
  1160. * which is appropriate for hotplugging, unless the platform data
  1161. * specify mode 3 (if hardware is not compatible to mode 0).
  1162. */
  1163. if (spi->mode != SPI_MODE_3)
  1164. spi->mode = SPI_MODE_0;
  1165. spi->bits_per_word = 8;
  1166. status = spi_setup(spi);
  1167. if (status < 0) {
  1168. dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
  1169. spi->mode, spi->max_speed_hz / 1000,
  1170. status);
  1171. return status;
  1172. }
  1173. /* We need a supply of ones to transmit. This is the only time
  1174. * the CPU touches these, so cache coherency isn't a concern.
  1175. *
  1176. * NOTE if many systems use more than one MMC-over-SPI connector
  1177. * it'd save some memory to share this. That's evidently rare.
  1178. */
  1179. status = -ENOMEM;
  1180. ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
  1181. if (!ones)
  1182. goto nomem;
  1183. memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
  1184. mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
  1185. if (!mmc)
  1186. goto nomem;
  1187. mmc->ops = &mmc_spi_ops;
  1188. mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
  1189. mmc->max_segs = MMC_SPI_BLOCKSATONCE;
  1190. mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
  1191. mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
  1192. mmc->caps = MMC_CAP_SPI;
  1193. /* SPI doesn't need the lowspeed device identification thing for
  1194. * MMC or SD cards, since it never comes up in open drain mode.
  1195. * That's good; some SPI masters can't handle very low speeds!
  1196. *
  1197. * However, low speed SDIO cards need not handle over 400 KHz;
  1198. * that's the only reason not to use a few MHz for f_min (until
  1199. * the upper layer reads the target frequency from the CSD).
  1200. */
  1201. mmc->f_min = 400000;
  1202. mmc->f_max = spi->max_speed_hz;
  1203. host = mmc_priv(mmc);
  1204. host->mmc = mmc;
  1205. host->spi = spi;
  1206. host->ones = ones;
  1207. dev_set_drvdata(&spi->dev, mmc);
  1208. /* Platform data is used to hook up things like card sensing
  1209. * and power switching gpios.
  1210. */
  1211. host->pdata = mmc_spi_get_pdata(spi);
  1212. if (host->pdata)
  1213. mmc->ocr_avail = host->pdata->ocr_mask;
  1214. if (!mmc->ocr_avail) {
  1215. dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
  1216. mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
  1217. }
  1218. if (host->pdata && host->pdata->setpower) {
  1219. host->powerup_msecs = host->pdata->powerup_msecs;
  1220. if (!host->powerup_msecs || host->powerup_msecs > 250)
  1221. host->powerup_msecs = 250;
  1222. }
  1223. /* preallocate dma buffers */
  1224. host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
  1225. if (!host->data)
  1226. goto fail_nobuf1;
  1227. status = mmc_spi_dma_alloc(host);
  1228. if (status)
  1229. goto fail_dma;
  1230. /* setup message for status/busy readback */
  1231. spi_message_init(&host->readback);
  1232. host->readback.is_dma_mapped = (host->dma_dev != NULL);
  1233. spi_message_add_tail(&host->status, &host->readback);
  1234. host->status.tx_buf = host->ones;
  1235. host->status.tx_dma = host->ones_dma;
  1236. host->status.rx_buf = &host->data->status;
  1237. host->status.rx_dma = host->data_dma + offsetof(struct scratch, status);
  1238. host->status.cs_change = 1;
  1239. /* register card detect irq */
  1240. if (host->pdata && host->pdata->init) {
  1241. status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
  1242. if (status != 0)
  1243. goto fail_glue_init;
  1244. }
  1245. /* pass platform capabilities, if any */
  1246. if (host->pdata) {
  1247. mmc->caps |= host->pdata->caps;
  1248. mmc->caps2 |= host->pdata->caps2;
  1249. }
  1250. status = mmc_add_host(mmc);
  1251. if (status != 0)
  1252. goto fail_glue_init;
  1253. /*
  1254. * Index 0 is card detect
  1255. * Old boardfiles were specifying 1 ms as debounce
  1256. */
  1257. status = mmc_gpiod_request_cd(mmc, NULL, 0, false, 1000);
  1258. if (status == -EPROBE_DEFER)
  1259. goto fail_gpiod_request;
  1260. if (!status) {
  1261. /*
  1262. * The platform has a CD GPIO signal that may support
  1263. * interrupts, so let mmc_gpiod_request_cd_irq() decide
  1264. * if polling is needed or not.
  1265. */
  1266. mmc->caps &= ~MMC_CAP_NEEDS_POLL;
  1267. mmc_gpiod_request_cd_irq(mmc);
  1268. }
  1269. mmc_detect_change(mmc, 0);
  1270. /* Index 1 is write protect/read only */
  1271. status = mmc_gpiod_request_ro(mmc, NULL, 1, 0);
  1272. if (status == -EPROBE_DEFER)
  1273. goto fail_gpiod_request;
  1274. if (!status)
  1275. has_ro = true;
  1276. dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n",
  1277. dev_name(&mmc->class_dev),
  1278. host->dma_dev ? "" : ", no DMA",
  1279. has_ro ? "" : ", no WP",
  1280. (host->pdata && host->pdata->setpower)
  1281. ? "" : ", no poweroff",
  1282. (mmc->caps & MMC_CAP_NEEDS_POLL)
  1283. ? ", cd polling" : "");
  1284. return 0;
  1285. fail_gpiod_request:
  1286. mmc_remove_host(mmc);
  1287. fail_glue_init:
  1288. mmc_spi_dma_free(host);
  1289. fail_dma:
  1290. kfree(host->data);
  1291. fail_nobuf1:
  1292. mmc_spi_put_pdata(spi);
  1293. mmc_free_host(mmc);
  1294. nomem:
  1295. kfree(ones);
  1296. return status;
  1297. }
  1298. static void mmc_spi_remove(struct spi_device *spi)
  1299. {
  1300. struct mmc_host *mmc = dev_get_drvdata(&spi->dev);
  1301. struct mmc_spi_host *host = mmc_priv(mmc);
  1302. /* prevent new mmc_detect_change() calls */
  1303. if (host->pdata && host->pdata->exit)
  1304. host->pdata->exit(&spi->dev, mmc);
  1305. mmc_remove_host(mmc);
  1306. mmc_spi_dma_free(host);
  1307. kfree(host->data);
  1308. kfree(host->ones);
  1309. spi->max_speed_hz = mmc->f_max;
  1310. mmc_spi_put_pdata(spi);
  1311. mmc_free_host(mmc);
  1312. }
  1313. static const struct spi_device_id mmc_spi_dev_ids[] = {
  1314. { "mmc-spi-slot"},
  1315. { },
  1316. };
  1317. MODULE_DEVICE_TABLE(spi, mmc_spi_dev_ids);
  1318. static const struct of_device_id mmc_spi_of_match_table[] = {
  1319. { .compatible = "mmc-spi-slot", },
  1320. {},
  1321. };
  1322. MODULE_DEVICE_TABLE(of, mmc_spi_of_match_table);
  1323. static struct spi_driver mmc_spi_driver = {
  1324. .driver = {
  1325. .name = "mmc_spi",
  1326. .of_match_table = mmc_spi_of_match_table,
  1327. },
  1328. .id_table = mmc_spi_dev_ids,
  1329. .probe = mmc_spi_probe,
  1330. .remove = mmc_spi_remove,
  1331. };
  1332. module_spi_driver(mmc_spi_driver);
  1333. MODULE_AUTHOR("Mike Lavender, David Brownell, Hans-Peter Nilsson, Jan Nikitenko");
  1334. MODULE_DESCRIPTION("SPI SD/MMC host driver");
  1335. MODULE_LICENSE("GPL");
  1336. MODULE_ALIAS("spi:mmc_spi");