bcm2835.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * bcm2835 sdhost driver.
  4. *
  5. * The 2835 has two SD controllers: The Arasan sdhci controller
  6. * (supported by the iproc driver) and a custom sdhost controller
  7. * (supported by this driver).
  8. *
  9. * The sdhci controller supports both sdcard and sdio. The sdhost
  10. * controller supports the sdcard only, but has better performance.
  11. * Also note that the rpi3 has sdio wifi, so driving the sdcard with
  12. * the sdhost controller allows to use the sdhci controller for wifi
  13. * support.
  14. *
  15. * The configuration is done by devicetree via pin muxing. Both
  16. * SD controller are available on the same pins (2 pin groups = pin 22
  17. * to 27 + pin 48 to 53). So it's possible to use both SD controllers
  18. * at the same time with different pin groups.
  19. *
  20. * Author: Phil Elwell <[email protected]>
  21. * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
  22. *
  23. * Based on
  24. * mmc-bcm2835.c by Gellert Weisz
  25. * which is, in turn, based on
  26. * sdhci-bcm2708.c by Broadcom
  27. * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
  28. * sdhci.c and sdhci-pci.c by Pierre Ossman
  29. */
  30. #include <linux/clk.h>
  31. #include <linux/delay.h>
  32. #include <linux/device.h>
  33. #include <linux/dmaengine.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/err.h>
  36. #include <linux/highmem.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/io.h>
  39. #include <linux/iopoll.h>
  40. #include <linux/module.h>
  41. #include <linux/of_address.h>
  42. #include <linux/of_irq.h>
  43. #include <linux/platform_device.h>
  44. #include <linux/scatterlist.h>
  45. #include <linux/time.h>
  46. #include <linux/workqueue.h>
  47. #include <linux/mmc/host.h>
  48. #include <linux/mmc/mmc.h>
  49. #include <linux/mmc/sd.h>
  50. #define SDCMD 0x00 /* Command to SD card - 16 R/W */
  51. #define SDARG 0x04 /* Argument to SD card - 32 R/W */
  52. #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
  53. #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
  54. #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
  55. #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
  56. #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
  57. #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
  58. #define SDHSTS 0x20 /* SD host status - 11 R/W */
  59. #define SDVDD 0x30 /* SD card power control - 1 R/W */
  60. #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
  61. #define SDHCFG 0x38 /* Host configuration - 2 R/W */
  62. #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
  63. #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
  64. #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
  65. #define SDCMD_NEW_FLAG 0x8000
  66. #define SDCMD_FAIL_FLAG 0x4000
  67. #define SDCMD_BUSYWAIT 0x800
  68. #define SDCMD_NO_RESPONSE 0x400
  69. #define SDCMD_LONG_RESPONSE 0x200
  70. #define SDCMD_WRITE_CMD 0x80
  71. #define SDCMD_READ_CMD 0x40
  72. #define SDCMD_CMD_MASK 0x3f
  73. #define SDCDIV_MAX_CDIV 0x7ff
  74. #define SDHSTS_BUSY_IRPT 0x400
  75. #define SDHSTS_BLOCK_IRPT 0x200
  76. #define SDHSTS_SDIO_IRPT 0x100
  77. #define SDHSTS_REW_TIME_OUT 0x80
  78. #define SDHSTS_CMD_TIME_OUT 0x40
  79. #define SDHSTS_CRC16_ERROR 0x20
  80. #define SDHSTS_CRC7_ERROR 0x10
  81. #define SDHSTS_FIFO_ERROR 0x08
  82. /* Reserved */
  83. /* Reserved */
  84. #define SDHSTS_DATA_FLAG 0x01
  85. #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
  86. SDHSTS_CRC16_ERROR | \
  87. SDHSTS_REW_TIME_OUT | \
  88. SDHSTS_FIFO_ERROR)
  89. #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
  90. SDHSTS_TRANSFER_ERROR_MASK)
  91. #define SDHCFG_BUSY_IRPT_EN BIT(10)
  92. #define SDHCFG_BLOCK_IRPT_EN BIT(8)
  93. #define SDHCFG_SDIO_IRPT_EN BIT(5)
  94. #define SDHCFG_DATA_IRPT_EN BIT(4)
  95. #define SDHCFG_SLOW_CARD BIT(3)
  96. #define SDHCFG_WIDE_EXT_BUS BIT(2)
  97. #define SDHCFG_WIDE_INT_BUS BIT(1)
  98. #define SDHCFG_REL_CMD_LINE BIT(0)
  99. #define SDVDD_POWER_OFF 0
  100. #define SDVDD_POWER_ON 1
  101. #define SDEDM_FORCE_DATA_MODE BIT(19)
  102. #define SDEDM_CLOCK_PULSE BIT(20)
  103. #define SDEDM_BYPASS BIT(21)
  104. #define SDEDM_WRITE_THRESHOLD_SHIFT 9
  105. #define SDEDM_READ_THRESHOLD_SHIFT 14
  106. #define SDEDM_THRESHOLD_MASK 0x1f
  107. #define SDEDM_FSM_MASK 0xf
  108. #define SDEDM_FSM_IDENTMODE 0x0
  109. #define SDEDM_FSM_DATAMODE 0x1
  110. #define SDEDM_FSM_READDATA 0x2
  111. #define SDEDM_FSM_WRITEDATA 0x3
  112. #define SDEDM_FSM_READWAIT 0x4
  113. #define SDEDM_FSM_READCRC 0x5
  114. #define SDEDM_FSM_WRITECRC 0x6
  115. #define SDEDM_FSM_WRITEWAIT1 0x7
  116. #define SDEDM_FSM_POWERDOWN 0x8
  117. #define SDEDM_FSM_POWERUP 0x9
  118. #define SDEDM_FSM_WRITESTART1 0xa
  119. #define SDEDM_FSM_WRITESTART2 0xb
  120. #define SDEDM_FSM_GENPULSES 0xc
  121. #define SDEDM_FSM_WRITEWAIT2 0xd
  122. #define SDEDM_FSM_STARTPOWDOWN 0xf
  123. #define SDDATA_FIFO_WORDS 16
  124. #define FIFO_READ_THRESHOLD 4
  125. #define FIFO_WRITE_THRESHOLD 4
  126. #define SDDATA_FIFO_PIO_BURST 8
  127. #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */
  128. struct bcm2835_host {
  129. spinlock_t lock;
  130. struct mutex mutex;
  131. void __iomem *ioaddr;
  132. u32 phys_addr;
  133. struct platform_device *pdev;
  134. int clock; /* Current clock speed */
  135. unsigned int max_clk; /* Max possible freq */
  136. struct work_struct dma_work;
  137. struct delayed_work timeout_work; /* Timer for timeouts */
  138. struct sg_mapping_iter sg_miter; /* SG state for PIO */
  139. unsigned int blocks; /* remaining PIO blocks */
  140. int irq; /* Device IRQ */
  141. u32 ns_per_fifo_word;
  142. /* cached registers */
  143. u32 hcfg;
  144. u32 cdiv;
  145. struct mmc_request *mrq; /* Current request */
  146. struct mmc_command *cmd; /* Current command */
  147. struct mmc_data *data; /* Current data request */
  148. bool data_complete:1;/* Data finished before cmd */
  149. bool use_busy:1; /* Wait for busy interrupt */
  150. bool use_sbc:1; /* Send CMD23 */
  151. /* for threaded irq handler */
  152. bool irq_block;
  153. bool irq_busy;
  154. bool irq_data;
  155. /* DMA part */
  156. struct dma_chan *dma_chan_rxtx;
  157. struct dma_chan *dma_chan;
  158. struct dma_slave_config dma_cfg_rx;
  159. struct dma_slave_config dma_cfg_tx;
  160. struct dma_async_tx_descriptor *dma_desc;
  161. u32 dma_dir;
  162. u32 drain_words;
  163. struct page *drain_page;
  164. u32 drain_offset;
  165. bool use_dma;
  166. };
  167. static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd,
  168. const char *label)
  169. {
  170. struct device *dev = &host->pdev->dev;
  171. if (!cmd)
  172. return;
  173. dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
  174. (cmd == host->cmd) ? '>' : ' ',
  175. label, cmd->opcode, cmd->arg, cmd->flags,
  176. cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
  177. cmd->error);
  178. }
  179. static void bcm2835_dumpregs(struct bcm2835_host *host)
  180. {
  181. struct mmc_request *mrq = host->mrq;
  182. struct device *dev = &host->pdev->dev;
  183. if (mrq) {
  184. bcm2835_dumpcmd(host, mrq->sbc, "sbc");
  185. bcm2835_dumpcmd(host, mrq->cmd, "cmd");
  186. if (mrq->data) {
  187. dev_dbg(dev, "data blocks %x blksz %x - err %d\n",
  188. mrq->data->blocks,
  189. mrq->data->blksz,
  190. mrq->data->error);
  191. }
  192. bcm2835_dumpcmd(host, mrq->stop, "stop");
  193. }
  194. dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
  195. dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
  196. dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
  197. dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
  198. dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
  199. dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
  200. dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
  201. dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
  202. dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
  203. dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
  204. dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
  205. dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
  206. dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
  207. dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
  208. dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
  209. dev_dbg(dev, "===========================================\n");
  210. }
  211. static void bcm2835_reset_internal(struct bcm2835_host *host)
  212. {
  213. u32 temp;
  214. writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
  215. writel(0, host->ioaddr + SDCMD);
  216. writel(0, host->ioaddr + SDARG);
  217. writel(0xf00000, host->ioaddr + SDTOUT);
  218. writel(0, host->ioaddr + SDCDIV);
  219. writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */
  220. writel(0, host->ioaddr + SDHCFG);
  221. writel(0, host->ioaddr + SDHBCT);
  222. writel(0, host->ioaddr + SDHBLC);
  223. /* Limit fifo usage due to silicon bug */
  224. temp = readl(host->ioaddr + SDEDM);
  225. temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
  226. (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
  227. temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
  228. (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
  229. writel(temp, host->ioaddr + SDEDM);
  230. msleep(20);
  231. writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
  232. msleep(20);
  233. host->clock = 0;
  234. writel(host->hcfg, host->ioaddr + SDHCFG);
  235. writel(host->cdiv, host->ioaddr + SDCDIV);
  236. }
  237. static void bcm2835_reset(struct mmc_host *mmc)
  238. {
  239. struct bcm2835_host *host = mmc_priv(mmc);
  240. if (host->dma_chan)
  241. dmaengine_terminate_sync(host->dma_chan);
  242. host->dma_chan = NULL;
  243. bcm2835_reset_internal(host);
  244. }
  245. static void bcm2835_finish_command(struct bcm2835_host *host);
  246. static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
  247. {
  248. int timediff;
  249. u32 alternate_idle;
  250. alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
  251. SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
  252. timediff = 0;
  253. while (1) {
  254. u32 edm, fsm;
  255. edm = readl(host->ioaddr + SDEDM);
  256. fsm = edm & SDEDM_FSM_MASK;
  257. if ((fsm == SDEDM_FSM_IDENTMODE) ||
  258. (fsm == SDEDM_FSM_DATAMODE))
  259. break;
  260. if (fsm == alternate_idle) {
  261. writel(edm | SDEDM_FORCE_DATA_MODE,
  262. host->ioaddr + SDEDM);
  263. break;
  264. }
  265. timediff++;
  266. if (timediff == 100000) {
  267. dev_err(&host->pdev->dev,
  268. "wait_transfer_complete - still waiting after %d retries\n",
  269. timediff);
  270. bcm2835_dumpregs(host);
  271. host->mrq->data->error = -ETIMEDOUT;
  272. return;
  273. }
  274. cpu_relax();
  275. }
  276. }
  277. static void bcm2835_dma_complete(void *param)
  278. {
  279. struct bcm2835_host *host = param;
  280. schedule_work(&host->dma_work);
  281. }
  282. static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
  283. {
  284. unsigned long flags;
  285. size_t blksize;
  286. unsigned long wait_max;
  287. blksize = host->data->blksz;
  288. wait_max = jiffies + msecs_to_jiffies(500);
  289. local_irq_save(flags);
  290. while (blksize) {
  291. int copy_words;
  292. u32 hsts = 0;
  293. size_t len;
  294. u32 *buf;
  295. if (!sg_miter_next(&host->sg_miter)) {
  296. host->data->error = -EINVAL;
  297. break;
  298. }
  299. len = min(host->sg_miter.length, blksize);
  300. if (len % 4) {
  301. host->data->error = -EINVAL;
  302. break;
  303. }
  304. blksize -= len;
  305. host->sg_miter.consumed = len;
  306. buf = (u32 *)host->sg_miter.addr;
  307. copy_words = len / 4;
  308. while (copy_words) {
  309. int burst_words, words;
  310. u32 edm;
  311. burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
  312. edm = readl(host->ioaddr + SDEDM);
  313. if (is_read)
  314. words = ((edm >> 4) & 0x1f);
  315. else
  316. words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
  317. if (words < burst_words) {
  318. int fsm_state = (edm & SDEDM_FSM_MASK);
  319. struct device *dev = &host->pdev->dev;
  320. if ((is_read &&
  321. (fsm_state != SDEDM_FSM_READDATA &&
  322. fsm_state != SDEDM_FSM_READWAIT &&
  323. fsm_state != SDEDM_FSM_READCRC)) ||
  324. (!is_read &&
  325. (fsm_state != SDEDM_FSM_WRITEDATA &&
  326. fsm_state != SDEDM_FSM_WRITESTART1 &&
  327. fsm_state != SDEDM_FSM_WRITESTART2))) {
  328. hsts = readl(host->ioaddr + SDHSTS);
  329. dev_err(dev, "fsm %x, hsts %08x\n",
  330. fsm_state, hsts);
  331. if (hsts & SDHSTS_ERROR_MASK)
  332. break;
  333. }
  334. if (time_after(jiffies, wait_max)) {
  335. dev_err(dev, "PIO %s timeout - EDM %08x\n",
  336. is_read ? "read" : "write",
  337. edm);
  338. hsts = SDHSTS_REW_TIME_OUT;
  339. break;
  340. }
  341. ndelay((burst_words - words) *
  342. host->ns_per_fifo_word);
  343. continue;
  344. } else if (words > copy_words) {
  345. words = copy_words;
  346. }
  347. copy_words -= words;
  348. while (words) {
  349. if (is_read)
  350. *(buf++) = readl(host->ioaddr + SDDATA);
  351. else
  352. writel(*(buf++), host->ioaddr + SDDATA);
  353. words--;
  354. }
  355. }
  356. if (hsts & SDHSTS_ERROR_MASK)
  357. break;
  358. }
  359. sg_miter_stop(&host->sg_miter);
  360. local_irq_restore(flags);
  361. }
  362. static void bcm2835_transfer_pio(struct bcm2835_host *host)
  363. {
  364. struct device *dev = &host->pdev->dev;
  365. u32 sdhsts;
  366. bool is_read;
  367. is_read = (host->data->flags & MMC_DATA_READ) != 0;
  368. bcm2835_transfer_block_pio(host, is_read);
  369. sdhsts = readl(host->ioaddr + SDHSTS);
  370. if (sdhsts & (SDHSTS_CRC16_ERROR |
  371. SDHSTS_CRC7_ERROR |
  372. SDHSTS_FIFO_ERROR)) {
  373. dev_err(dev, "%s transfer error - HSTS %08x\n",
  374. is_read ? "read" : "write", sdhsts);
  375. host->data->error = -EILSEQ;
  376. } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
  377. SDHSTS_REW_TIME_OUT))) {
  378. dev_err(dev, "%s timeout error - HSTS %08x\n",
  379. is_read ? "read" : "write", sdhsts);
  380. host->data->error = -ETIMEDOUT;
  381. }
  382. }
  383. static
  384. void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
  385. {
  386. int sg_len, dir_data, dir_slave;
  387. struct dma_async_tx_descriptor *desc = NULL;
  388. struct dma_chan *dma_chan;
  389. dma_chan = host->dma_chan_rxtx;
  390. if (data->flags & MMC_DATA_READ) {
  391. dir_data = DMA_FROM_DEVICE;
  392. dir_slave = DMA_DEV_TO_MEM;
  393. } else {
  394. dir_data = DMA_TO_DEVICE;
  395. dir_slave = DMA_MEM_TO_DEV;
  396. }
  397. /* The block doesn't manage the FIFO DREQs properly for
  398. * multi-block transfers, so don't attempt to DMA the final
  399. * few words. Unfortunately this requires the final sg entry
  400. * to be trimmed. N.B. This code demands that the overspill
  401. * is contained in a single sg entry.
  402. */
  403. host->drain_words = 0;
  404. if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
  405. struct scatterlist *sg;
  406. u32 len;
  407. int i;
  408. len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
  409. (u32)data->blocks * data->blksz);
  410. for_each_sg(data->sg, sg, data->sg_len, i) {
  411. if (sg_is_last(sg)) {
  412. WARN_ON(sg->length < len);
  413. sg->length -= len;
  414. host->drain_page = sg_page(sg);
  415. host->drain_offset = sg->offset + sg->length;
  416. }
  417. }
  418. host->drain_words = len / 4;
  419. }
  420. /* The parameters have already been validated, so this will not fail */
  421. (void)dmaengine_slave_config(dma_chan,
  422. (dir_data == DMA_FROM_DEVICE) ?
  423. &host->dma_cfg_rx :
  424. &host->dma_cfg_tx);
  425. sg_len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
  426. dir_data);
  427. if (!sg_len)
  428. return;
  429. desc = dmaengine_prep_slave_sg(dma_chan, data->sg, sg_len, dir_slave,
  430. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  431. if (!desc) {
  432. dma_unmap_sg(dma_chan->device->dev, data->sg, sg_len, dir_data);
  433. return;
  434. }
  435. desc->callback = bcm2835_dma_complete;
  436. desc->callback_param = host;
  437. host->dma_desc = desc;
  438. host->dma_chan = dma_chan;
  439. host->dma_dir = dir_data;
  440. }
  441. static void bcm2835_start_dma(struct bcm2835_host *host)
  442. {
  443. dmaengine_submit(host->dma_desc);
  444. dma_async_issue_pending(host->dma_chan);
  445. }
  446. static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
  447. {
  448. u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
  449. SDHCFG_BUSY_IRPT_EN;
  450. if (host->dma_desc) {
  451. host->hcfg = (host->hcfg & ~all_irqs) |
  452. SDHCFG_BUSY_IRPT_EN;
  453. } else {
  454. host->hcfg = (host->hcfg & ~all_irqs) |
  455. SDHCFG_DATA_IRPT_EN |
  456. SDHCFG_BUSY_IRPT_EN;
  457. }
  458. writel(host->hcfg, host->ioaddr + SDHCFG);
  459. }
  460. static
  461. void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
  462. {
  463. struct mmc_data *data = cmd->data;
  464. WARN_ON(host->data);
  465. host->data = data;
  466. if (!data)
  467. return;
  468. host->data_complete = false;
  469. host->data->bytes_xfered = 0;
  470. if (!host->dma_desc) {
  471. /* Use PIO */
  472. int flags = SG_MITER_ATOMIC;
  473. if (data->flags & MMC_DATA_READ)
  474. flags |= SG_MITER_TO_SG;
  475. else
  476. flags |= SG_MITER_FROM_SG;
  477. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  478. host->blocks = data->blocks;
  479. }
  480. bcm2835_set_transfer_irqs(host);
  481. writel(data->blksz, host->ioaddr + SDHBCT);
  482. writel(data->blocks, host->ioaddr + SDHBLC);
  483. }
  484. static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms)
  485. {
  486. struct device *dev = &host->pdev->dev;
  487. u32 value;
  488. int ret;
  489. ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
  490. !(value & SDCMD_NEW_FLAG), 1, 10);
  491. if (ret == -ETIMEDOUT)
  492. /* if it takes a while make poll interval bigger */
  493. ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
  494. !(value & SDCMD_NEW_FLAG),
  495. 10, max_ms * 1000);
  496. if (ret == -ETIMEDOUT)
  497. dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms);
  498. return value;
  499. }
  500. static void bcm2835_finish_request(struct bcm2835_host *host)
  501. {
  502. struct dma_chan *terminate_chan = NULL;
  503. struct mmc_request *mrq;
  504. cancel_delayed_work(&host->timeout_work);
  505. mrq = host->mrq;
  506. host->mrq = NULL;
  507. host->cmd = NULL;
  508. host->data = NULL;
  509. host->dma_desc = NULL;
  510. terminate_chan = host->dma_chan;
  511. host->dma_chan = NULL;
  512. if (terminate_chan) {
  513. int err = dmaengine_terminate_all(terminate_chan);
  514. if (err)
  515. dev_err(&host->pdev->dev,
  516. "failed to terminate DMA (%d)\n", err);
  517. }
  518. mmc_request_done(mmc_from_priv(host), mrq);
  519. }
  520. static
  521. bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
  522. {
  523. struct device *dev = &host->pdev->dev;
  524. u32 sdcmd, sdhsts;
  525. unsigned long timeout;
  526. WARN_ON(host->cmd);
  527. sdcmd = bcm2835_read_wait_sdcmd(host, 100);
  528. if (sdcmd & SDCMD_NEW_FLAG) {
  529. dev_err(dev, "previous command never completed.\n");
  530. bcm2835_dumpregs(host);
  531. cmd->error = -EILSEQ;
  532. bcm2835_finish_request(host);
  533. return false;
  534. }
  535. if (!cmd->data && cmd->busy_timeout > 9000)
  536. timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
  537. else
  538. timeout = 10 * HZ;
  539. schedule_delayed_work(&host->timeout_work, timeout);
  540. host->cmd = cmd;
  541. /* Clear any error flags */
  542. sdhsts = readl(host->ioaddr + SDHSTS);
  543. if (sdhsts & SDHSTS_ERROR_MASK)
  544. writel(sdhsts, host->ioaddr + SDHSTS);
  545. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  546. dev_err(dev, "unsupported response type!\n");
  547. cmd->error = -EINVAL;
  548. bcm2835_finish_request(host);
  549. return false;
  550. }
  551. bcm2835_prepare_data(host, cmd);
  552. writel(cmd->arg, host->ioaddr + SDARG);
  553. sdcmd = cmd->opcode & SDCMD_CMD_MASK;
  554. host->use_busy = false;
  555. if (!(cmd->flags & MMC_RSP_PRESENT)) {
  556. sdcmd |= SDCMD_NO_RESPONSE;
  557. } else {
  558. if (cmd->flags & MMC_RSP_136)
  559. sdcmd |= SDCMD_LONG_RESPONSE;
  560. if (cmd->flags & MMC_RSP_BUSY) {
  561. sdcmd |= SDCMD_BUSYWAIT;
  562. host->use_busy = true;
  563. }
  564. }
  565. if (cmd->data) {
  566. if (cmd->data->flags & MMC_DATA_WRITE)
  567. sdcmd |= SDCMD_WRITE_CMD;
  568. if (cmd->data->flags & MMC_DATA_READ)
  569. sdcmd |= SDCMD_READ_CMD;
  570. }
  571. writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
  572. return true;
  573. }
  574. static void bcm2835_transfer_complete(struct bcm2835_host *host)
  575. {
  576. struct mmc_data *data;
  577. WARN_ON(!host->data_complete);
  578. data = host->data;
  579. host->data = NULL;
  580. /* Need to send CMD12 if -
  581. * a) open-ended multiblock transfer (no CMD23)
  582. * b) error in multiblock transfer
  583. */
  584. if (host->mrq->stop && (data->error || !host->use_sbc)) {
  585. if (bcm2835_send_command(host, host->mrq->stop)) {
  586. /* No busy, so poll for completion */
  587. if (!host->use_busy)
  588. bcm2835_finish_command(host);
  589. }
  590. } else {
  591. bcm2835_wait_transfer_complete(host);
  592. bcm2835_finish_request(host);
  593. }
  594. }
  595. static void bcm2835_finish_data(struct bcm2835_host *host)
  596. {
  597. struct device *dev = &host->pdev->dev;
  598. struct mmc_data *data;
  599. data = host->data;
  600. host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
  601. writel(host->hcfg, host->ioaddr + SDHCFG);
  602. data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
  603. host->data_complete = true;
  604. if (host->cmd) {
  605. /* Data managed to finish before the
  606. * command completed. Make sure we do
  607. * things in the proper order.
  608. */
  609. dev_dbg(dev, "Finished early - HSTS %08x\n",
  610. readl(host->ioaddr + SDHSTS));
  611. } else {
  612. bcm2835_transfer_complete(host);
  613. }
  614. }
  615. static void bcm2835_finish_command(struct bcm2835_host *host)
  616. {
  617. struct device *dev = &host->pdev->dev;
  618. struct mmc_command *cmd = host->cmd;
  619. u32 sdcmd;
  620. sdcmd = bcm2835_read_wait_sdcmd(host, 100);
  621. /* Check for errors */
  622. if (sdcmd & SDCMD_NEW_FLAG) {
  623. dev_err(dev, "command never completed.\n");
  624. bcm2835_dumpregs(host);
  625. host->cmd->error = -EIO;
  626. bcm2835_finish_request(host);
  627. return;
  628. } else if (sdcmd & SDCMD_FAIL_FLAG) {
  629. u32 sdhsts = readl(host->ioaddr + SDHSTS);
  630. /* Clear the errors */
  631. writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
  632. if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
  633. (host->cmd->opcode != MMC_SEND_OP_COND)) {
  634. u32 edm, fsm;
  635. if (sdhsts & SDHSTS_CMD_TIME_OUT) {
  636. host->cmd->error = -ETIMEDOUT;
  637. } else {
  638. dev_err(dev, "unexpected command %d error\n",
  639. host->cmd->opcode);
  640. bcm2835_dumpregs(host);
  641. host->cmd->error = -EILSEQ;
  642. }
  643. edm = readl(host->ioaddr + SDEDM);
  644. fsm = edm & SDEDM_FSM_MASK;
  645. if (fsm == SDEDM_FSM_READWAIT ||
  646. fsm == SDEDM_FSM_WRITESTART1)
  647. /* Kick the FSM out of its wait */
  648. writel(edm | SDEDM_FORCE_DATA_MODE,
  649. host->ioaddr + SDEDM);
  650. bcm2835_finish_request(host);
  651. return;
  652. }
  653. }
  654. if (cmd->flags & MMC_RSP_PRESENT) {
  655. if (cmd->flags & MMC_RSP_136) {
  656. int i;
  657. for (i = 0; i < 4; i++) {
  658. cmd->resp[3 - i] =
  659. readl(host->ioaddr + SDRSP0 + i * 4);
  660. }
  661. } else {
  662. cmd->resp[0] = readl(host->ioaddr + SDRSP0);
  663. }
  664. }
  665. if (cmd == host->mrq->sbc) {
  666. /* Finished CMD23, now send actual command. */
  667. host->cmd = NULL;
  668. if (bcm2835_send_command(host, host->mrq->cmd)) {
  669. if (host->data && host->dma_desc)
  670. /* DMA transfer starts now, PIO starts
  671. * after irq
  672. */
  673. bcm2835_start_dma(host);
  674. if (!host->use_busy)
  675. bcm2835_finish_command(host);
  676. }
  677. } else if (cmd == host->mrq->stop) {
  678. /* Finished CMD12 */
  679. bcm2835_finish_request(host);
  680. } else {
  681. /* Processed actual command. */
  682. host->cmd = NULL;
  683. if (!host->data)
  684. bcm2835_finish_request(host);
  685. else if (host->data_complete)
  686. bcm2835_transfer_complete(host);
  687. }
  688. }
  689. static void bcm2835_timeout(struct work_struct *work)
  690. {
  691. struct delayed_work *d = to_delayed_work(work);
  692. struct bcm2835_host *host =
  693. container_of(d, struct bcm2835_host, timeout_work);
  694. struct device *dev = &host->pdev->dev;
  695. mutex_lock(&host->mutex);
  696. if (host->mrq) {
  697. dev_err(dev, "timeout waiting for hardware interrupt.\n");
  698. bcm2835_dumpregs(host);
  699. bcm2835_reset(mmc_from_priv(host));
  700. if (host->data) {
  701. host->data->error = -ETIMEDOUT;
  702. bcm2835_finish_data(host);
  703. } else {
  704. if (host->cmd)
  705. host->cmd->error = -ETIMEDOUT;
  706. else
  707. host->mrq->cmd->error = -ETIMEDOUT;
  708. bcm2835_finish_request(host);
  709. }
  710. }
  711. mutex_unlock(&host->mutex);
  712. }
  713. static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
  714. {
  715. struct device *dev = &host->pdev->dev;
  716. if (!(intmask & SDHSTS_ERROR_MASK))
  717. return false;
  718. if (!host->cmd)
  719. return true;
  720. dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask);
  721. if (intmask & SDHSTS_CRC7_ERROR) {
  722. host->cmd->error = -EILSEQ;
  723. } else if (intmask & (SDHSTS_CRC16_ERROR |
  724. SDHSTS_FIFO_ERROR)) {
  725. if (host->mrq->data)
  726. host->mrq->data->error = -EILSEQ;
  727. else
  728. host->cmd->error = -EILSEQ;
  729. } else if (intmask & SDHSTS_REW_TIME_OUT) {
  730. if (host->mrq->data)
  731. host->mrq->data->error = -ETIMEDOUT;
  732. else
  733. host->cmd->error = -ETIMEDOUT;
  734. } else if (intmask & SDHSTS_CMD_TIME_OUT) {
  735. host->cmd->error = -ETIMEDOUT;
  736. }
  737. bcm2835_dumpregs(host);
  738. return true;
  739. }
  740. static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
  741. {
  742. if (!host->data)
  743. return;
  744. if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
  745. host->data->error = -EILSEQ;
  746. if (intmask & SDHSTS_REW_TIME_OUT)
  747. host->data->error = -ETIMEDOUT;
  748. }
  749. static void bcm2835_busy_irq(struct bcm2835_host *host)
  750. {
  751. if (WARN_ON(!host->cmd)) {
  752. bcm2835_dumpregs(host);
  753. return;
  754. }
  755. if (WARN_ON(!host->use_busy)) {
  756. bcm2835_dumpregs(host);
  757. return;
  758. }
  759. host->use_busy = false;
  760. bcm2835_finish_command(host);
  761. }
  762. static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
  763. {
  764. /* There are no dedicated data/space available interrupt
  765. * status bits, so it is necessary to use the single shared
  766. * data/space available FIFO status bits. It is therefore not
  767. * an error to get here when there is no data transfer in
  768. * progress.
  769. */
  770. if (!host->data)
  771. return;
  772. bcm2835_check_data_error(host, intmask);
  773. if (host->data->error)
  774. goto finished;
  775. if (host->data->flags & MMC_DATA_WRITE) {
  776. /* Use the block interrupt for writes after the first block */
  777. host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
  778. host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
  779. writel(host->hcfg, host->ioaddr + SDHCFG);
  780. bcm2835_transfer_pio(host);
  781. } else {
  782. bcm2835_transfer_pio(host);
  783. host->blocks--;
  784. if ((host->blocks == 0) || host->data->error)
  785. goto finished;
  786. }
  787. return;
  788. finished:
  789. host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
  790. writel(host->hcfg, host->ioaddr + SDHCFG);
  791. }
  792. static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
  793. {
  794. if (!host->data)
  795. return;
  796. if ((host->blocks == 0) || host->data->error)
  797. bcm2835_finish_data(host);
  798. }
  799. static void bcm2835_block_irq(struct bcm2835_host *host)
  800. {
  801. if (WARN_ON(!host->data)) {
  802. bcm2835_dumpregs(host);
  803. return;
  804. }
  805. if (!host->dma_desc) {
  806. WARN_ON(!host->blocks);
  807. if (host->data->error || (--host->blocks == 0))
  808. bcm2835_finish_data(host);
  809. else
  810. bcm2835_transfer_pio(host);
  811. } else if (host->data->flags & MMC_DATA_WRITE) {
  812. bcm2835_finish_data(host);
  813. }
  814. }
  815. static irqreturn_t bcm2835_irq(int irq, void *dev_id)
  816. {
  817. irqreturn_t result = IRQ_NONE;
  818. struct bcm2835_host *host = dev_id;
  819. u32 intmask;
  820. spin_lock(&host->lock);
  821. intmask = readl(host->ioaddr + SDHSTS);
  822. writel(SDHSTS_BUSY_IRPT |
  823. SDHSTS_BLOCK_IRPT |
  824. SDHSTS_SDIO_IRPT |
  825. SDHSTS_DATA_FLAG,
  826. host->ioaddr + SDHSTS);
  827. if (intmask & SDHSTS_BLOCK_IRPT) {
  828. bcm2835_check_data_error(host, intmask);
  829. host->irq_block = true;
  830. result = IRQ_WAKE_THREAD;
  831. }
  832. if (intmask & SDHSTS_BUSY_IRPT) {
  833. if (!bcm2835_check_cmd_error(host, intmask)) {
  834. host->irq_busy = true;
  835. result = IRQ_WAKE_THREAD;
  836. } else {
  837. result = IRQ_HANDLED;
  838. }
  839. }
  840. /* There is no true data interrupt status bit, so it is
  841. * necessary to qualify the data flag with the interrupt
  842. * enable bit.
  843. */
  844. if ((intmask & SDHSTS_DATA_FLAG) &&
  845. (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
  846. bcm2835_data_irq(host, intmask);
  847. host->irq_data = true;
  848. result = IRQ_WAKE_THREAD;
  849. }
  850. spin_unlock(&host->lock);
  851. return result;
  852. }
  853. static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
  854. {
  855. struct bcm2835_host *host = dev_id;
  856. unsigned long flags;
  857. bool block, busy, data;
  858. spin_lock_irqsave(&host->lock, flags);
  859. block = host->irq_block;
  860. busy = host->irq_busy;
  861. data = host->irq_data;
  862. host->irq_block = false;
  863. host->irq_busy = false;
  864. host->irq_data = false;
  865. spin_unlock_irqrestore(&host->lock, flags);
  866. mutex_lock(&host->mutex);
  867. if (block)
  868. bcm2835_block_irq(host);
  869. if (busy)
  870. bcm2835_busy_irq(host);
  871. if (data)
  872. bcm2835_data_threaded_irq(host);
  873. mutex_unlock(&host->mutex);
  874. return IRQ_HANDLED;
  875. }
  876. static void bcm2835_dma_complete_work(struct work_struct *work)
  877. {
  878. struct bcm2835_host *host =
  879. container_of(work, struct bcm2835_host, dma_work);
  880. struct mmc_data *data;
  881. mutex_lock(&host->mutex);
  882. data = host->data;
  883. if (host->dma_chan) {
  884. dma_unmap_sg(host->dma_chan->device->dev,
  885. data->sg, data->sg_len,
  886. host->dma_dir);
  887. host->dma_chan = NULL;
  888. }
  889. if (host->drain_words) {
  890. unsigned long flags;
  891. void *page;
  892. u32 *buf;
  893. if (host->drain_offset & PAGE_MASK) {
  894. host->drain_page += host->drain_offset >> PAGE_SHIFT;
  895. host->drain_offset &= ~PAGE_MASK;
  896. }
  897. local_irq_save(flags);
  898. page = kmap_atomic(host->drain_page);
  899. buf = page + host->drain_offset;
  900. while (host->drain_words) {
  901. u32 edm = readl(host->ioaddr + SDEDM);
  902. if ((edm >> 4) & 0x1f)
  903. *(buf++) = readl(host->ioaddr + SDDATA);
  904. host->drain_words--;
  905. }
  906. kunmap_atomic(page);
  907. local_irq_restore(flags);
  908. }
  909. bcm2835_finish_data(host);
  910. mutex_unlock(&host->mutex);
  911. }
  912. static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
  913. {
  914. struct mmc_host *mmc = mmc_from_priv(host);
  915. int div;
  916. /* The SDCDIV register has 11 bits, and holds (div - 2). But
  917. * in data mode the max is 50MHz wihout a minimum, and only
  918. * the bottom 3 bits are used. Since the switch over is
  919. * automatic (unless we have marked the card as slow...),
  920. * chosen values have to make sense in both modes. Ident mode
  921. * must be 100-400KHz, so can range check the requested
  922. * clock. CMD15 must be used to return to data mode, so this
  923. * can be monitored.
  924. *
  925. * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
  926. * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
  927. *
  928. * 623->400KHz/27.8MHz
  929. * reset value (507)->491159/50MHz
  930. *
  931. * BUT, the 3-bit clock divisor in data mode is too small if
  932. * the core clock is higher than 250MHz, so instead use the
  933. * SLOW_CARD configuration bit to force the use of the ident
  934. * clock divisor at all times.
  935. */
  936. if (clock < 100000) {
  937. /* Can't stop the clock, but make it as slow as possible
  938. * to show willing
  939. */
  940. host->cdiv = SDCDIV_MAX_CDIV;
  941. writel(host->cdiv, host->ioaddr + SDCDIV);
  942. return;
  943. }
  944. div = host->max_clk / clock;
  945. if (div < 2)
  946. div = 2;
  947. if ((host->max_clk / div) > clock)
  948. div++;
  949. div -= 2;
  950. if (div > SDCDIV_MAX_CDIV)
  951. div = SDCDIV_MAX_CDIV;
  952. clock = host->max_clk / (div + 2);
  953. mmc->actual_clock = clock;
  954. /* Calibrate some delays */
  955. host->ns_per_fifo_word = (1000000000 / clock) *
  956. ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
  957. host->cdiv = div;
  958. writel(host->cdiv, host->ioaddr + SDCDIV);
  959. /* Set the timeout to 500ms */
  960. writel(mmc->actual_clock / 2, host->ioaddr + SDTOUT);
  961. }
  962. static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq)
  963. {
  964. struct bcm2835_host *host = mmc_priv(mmc);
  965. struct device *dev = &host->pdev->dev;
  966. u32 edm, fsm;
  967. /* Reset the error statuses in case this is a retry */
  968. if (mrq->sbc)
  969. mrq->sbc->error = 0;
  970. if (mrq->cmd)
  971. mrq->cmd->error = 0;
  972. if (mrq->data)
  973. mrq->data->error = 0;
  974. if (mrq->stop)
  975. mrq->stop->error = 0;
  976. if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
  977. dev_err(dev, "unsupported block size (%d bytes)\n",
  978. mrq->data->blksz);
  979. if (mrq->cmd)
  980. mrq->cmd->error = -EINVAL;
  981. mmc_request_done(mmc, mrq);
  982. return;
  983. }
  984. mutex_lock(&host->mutex);
  985. WARN_ON(host->mrq);
  986. host->mrq = mrq;
  987. edm = readl(host->ioaddr + SDEDM);
  988. fsm = edm & SDEDM_FSM_MASK;
  989. if ((fsm != SDEDM_FSM_IDENTMODE) &&
  990. (fsm != SDEDM_FSM_DATAMODE)) {
  991. dev_err(dev, "previous command (%d) not complete (EDM %08x)\n",
  992. readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK,
  993. edm);
  994. bcm2835_dumpregs(host);
  995. if (mrq->cmd)
  996. mrq->cmd->error = -EILSEQ;
  997. bcm2835_finish_request(host);
  998. mutex_unlock(&host->mutex);
  999. return;
  1000. }
  1001. if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
  1002. bcm2835_prepare_dma(host, mrq->data);
  1003. host->use_sbc = !!mrq->sbc && host->mrq->data &&
  1004. (host->mrq->data->flags & MMC_DATA_READ);
  1005. if (host->use_sbc) {
  1006. if (bcm2835_send_command(host, mrq->sbc)) {
  1007. if (!host->use_busy)
  1008. bcm2835_finish_command(host);
  1009. }
  1010. } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) {
  1011. if (host->data && host->dma_desc) {
  1012. /* DMA transfer starts now, PIO starts after irq */
  1013. bcm2835_start_dma(host);
  1014. }
  1015. if (!host->use_busy)
  1016. bcm2835_finish_command(host);
  1017. }
  1018. mutex_unlock(&host->mutex);
  1019. }
  1020. static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1021. {
  1022. struct bcm2835_host *host = mmc_priv(mmc);
  1023. mutex_lock(&host->mutex);
  1024. if (!ios->clock || ios->clock != host->clock) {
  1025. bcm2835_set_clock(host, ios->clock);
  1026. host->clock = ios->clock;
  1027. }
  1028. /* set bus width */
  1029. host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
  1030. if (ios->bus_width == MMC_BUS_WIDTH_4)
  1031. host->hcfg |= SDHCFG_WIDE_EXT_BUS;
  1032. host->hcfg |= SDHCFG_WIDE_INT_BUS;
  1033. /* Disable clever clock switching, to cope with fast core clocks */
  1034. host->hcfg |= SDHCFG_SLOW_CARD;
  1035. writel(host->hcfg, host->ioaddr + SDHCFG);
  1036. mutex_unlock(&host->mutex);
  1037. }
  1038. static const struct mmc_host_ops bcm2835_ops = {
  1039. .request = bcm2835_request,
  1040. .set_ios = bcm2835_set_ios,
  1041. .card_hw_reset = bcm2835_reset,
  1042. };
  1043. static int bcm2835_add_host(struct bcm2835_host *host)
  1044. {
  1045. struct mmc_host *mmc = mmc_from_priv(host);
  1046. struct device *dev = &host->pdev->dev;
  1047. char pio_limit_string[20];
  1048. int ret;
  1049. if (!mmc->f_max || mmc->f_max > host->max_clk)
  1050. mmc->f_max = host->max_clk;
  1051. mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
  1052. mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000);
  1053. dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n",
  1054. mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
  1055. /* host controller capabilities */
  1056. mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
  1057. MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_CMD23;
  1058. spin_lock_init(&host->lock);
  1059. mutex_init(&host->mutex);
  1060. if (!host->dma_chan_rxtx) {
  1061. dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n");
  1062. host->use_dma = false;
  1063. } else {
  1064. host->use_dma = true;
  1065. host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1066. host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1067. host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
  1068. host->dma_cfg_tx.src_addr = 0;
  1069. host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA;
  1070. host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1071. host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1072. host->dma_cfg_rx.direction = DMA_DEV_TO_MEM;
  1073. host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
  1074. host->dma_cfg_rx.dst_addr = 0;
  1075. if (dmaengine_slave_config(host->dma_chan_rxtx,
  1076. &host->dma_cfg_tx) != 0 ||
  1077. dmaengine_slave_config(host->dma_chan_rxtx,
  1078. &host->dma_cfg_rx) != 0)
  1079. host->use_dma = false;
  1080. }
  1081. mmc->max_segs = 128;
  1082. mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev));
  1083. mmc->max_seg_size = mmc->max_req_size;
  1084. mmc->max_blk_size = 1024;
  1085. mmc->max_blk_count = 65535;
  1086. /* report supported voltage ranges */
  1087. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  1088. INIT_WORK(&host->dma_work, bcm2835_dma_complete_work);
  1089. INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout);
  1090. /* Set interrupt enables */
  1091. host->hcfg = SDHCFG_BUSY_IRPT_EN;
  1092. bcm2835_reset_internal(host);
  1093. ret = request_threaded_irq(host->irq, bcm2835_irq,
  1094. bcm2835_threaded_irq,
  1095. 0, mmc_hostname(mmc), host);
  1096. if (ret) {
  1097. dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret);
  1098. return ret;
  1099. }
  1100. ret = mmc_add_host(mmc);
  1101. if (ret) {
  1102. free_irq(host->irq, host);
  1103. return ret;
  1104. }
  1105. pio_limit_string[0] = '\0';
  1106. if (host->use_dma && (PIO_THRESHOLD > 0))
  1107. sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD);
  1108. dev_info(dev, "loaded - DMA %s%s\n",
  1109. host->use_dma ? "enabled" : "disabled", pio_limit_string);
  1110. return 0;
  1111. }
  1112. static int bcm2835_probe(struct platform_device *pdev)
  1113. {
  1114. struct device *dev = &pdev->dev;
  1115. struct clk *clk;
  1116. struct bcm2835_host *host;
  1117. struct mmc_host *mmc;
  1118. const __be32 *regaddr_p;
  1119. int ret;
  1120. dev_dbg(dev, "%s\n", __func__);
  1121. mmc = mmc_alloc_host(sizeof(*host), dev);
  1122. if (!mmc)
  1123. return -ENOMEM;
  1124. mmc->ops = &bcm2835_ops;
  1125. host = mmc_priv(mmc);
  1126. host->pdev = pdev;
  1127. spin_lock_init(&host->lock);
  1128. host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
  1129. if (IS_ERR(host->ioaddr)) {
  1130. ret = PTR_ERR(host->ioaddr);
  1131. goto err;
  1132. }
  1133. /* Parse OF address directly to get the physical address for
  1134. * DMA to our registers.
  1135. */
  1136. regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
  1137. if (!regaddr_p) {
  1138. dev_err(dev, "Can't get phys address\n");
  1139. ret = -EINVAL;
  1140. goto err;
  1141. }
  1142. host->phys_addr = be32_to_cpup(regaddr_p);
  1143. host->dma_chan = NULL;
  1144. host->dma_desc = NULL;
  1145. host->dma_chan_rxtx = dma_request_chan(dev, "rx-tx");
  1146. if (IS_ERR(host->dma_chan_rxtx)) {
  1147. ret = PTR_ERR(host->dma_chan_rxtx);
  1148. host->dma_chan_rxtx = NULL;
  1149. if (ret == -EPROBE_DEFER)
  1150. goto err;
  1151. /* Ignore errors to fall back to PIO mode */
  1152. }
  1153. clk = devm_clk_get(dev, NULL);
  1154. if (IS_ERR(clk)) {
  1155. ret = dev_err_probe(dev, PTR_ERR(clk), "could not get clk\n");
  1156. goto err;
  1157. }
  1158. host->max_clk = clk_get_rate(clk);
  1159. host->irq = platform_get_irq(pdev, 0);
  1160. if (host->irq < 0) {
  1161. ret = host->irq;
  1162. goto err;
  1163. }
  1164. ret = mmc_of_parse(mmc);
  1165. if (ret)
  1166. goto err;
  1167. ret = bcm2835_add_host(host);
  1168. if (ret)
  1169. goto err;
  1170. platform_set_drvdata(pdev, host);
  1171. dev_dbg(dev, "%s -> OK\n", __func__);
  1172. return 0;
  1173. err:
  1174. dev_dbg(dev, "%s -> err %d\n", __func__, ret);
  1175. if (host->dma_chan_rxtx)
  1176. dma_release_channel(host->dma_chan_rxtx);
  1177. mmc_free_host(mmc);
  1178. return ret;
  1179. }
  1180. static int bcm2835_remove(struct platform_device *pdev)
  1181. {
  1182. struct bcm2835_host *host = platform_get_drvdata(pdev);
  1183. struct mmc_host *mmc = mmc_from_priv(host);
  1184. mmc_remove_host(mmc);
  1185. writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
  1186. free_irq(host->irq, host);
  1187. cancel_work_sync(&host->dma_work);
  1188. cancel_delayed_work_sync(&host->timeout_work);
  1189. if (host->dma_chan_rxtx)
  1190. dma_release_channel(host->dma_chan_rxtx);
  1191. mmc_free_host(mmc);
  1192. return 0;
  1193. }
  1194. static const struct of_device_id bcm2835_match[] = {
  1195. { .compatible = "brcm,bcm2835-sdhost" },
  1196. { }
  1197. };
  1198. MODULE_DEVICE_TABLE(of, bcm2835_match);
  1199. static struct platform_driver bcm2835_driver = {
  1200. .probe = bcm2835_probe,
  1201. .remove = bcm2835_remove,
  1202. .driver = {
  1203. .name = "sdhost-bcm2835",
  1204. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1205. .of_match_table = bcm2835_match,
  1206. },
  1207. };
  1208. module_platform_driver(bcm2835_driver);
  1209. MODULE_ALIAS("platform:sdhost-bcm2835");
  1210. MODULE_DESCRIPTION("BCM2835 SDHost driver");
  1211. MODULE_LICENSE("GPL v2");
  1212. MODULE_AUTHOR("Phil Elwell");