wm97xx-core.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Wolfson WM97xx -- Core device
  4. *
  5. * Copyright (C) 2017 Robert Jarzmik
  6. *
  7. * Features:
  8. * - an AC97 audio codec
  9. * - a touchscreen driver
  10. * - a GPIO block
  11. */
  12. #include <linux/device.h>
  13. #include <linux/mfd/core.h>
  14. #include <linux/mfd/wm97xx.h>
  15. #include <linux/module.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <linux/wm97xx.h>
  19. #include <sound/ac97/codec.h>
  20. #include <sound/ac97/compat.h>
  21. #define WM9705_VENDOR_ID 0x574d4c05
  22. #define WM9712_VENDOR_ID 0x574d4c12
  23. #define WM9713_VENDOR_ID 0x574d4c13
  24. #define WM97xx_VENDOR_ID_MASK 0xffffffff
  25. struct wm97xx_priv {
  26. struct regmap *regmap;
  27. struct snd_ac97 *ac97;
  28. struct device *dev;
  29. struct wm97xx_platform_data codec_pdata;
  30. };
  31. static bool wm97xx_readable_reg(struct device *dev, unsigned int reg)
  32. {
  33. switch (reg) {
  34. case AC97_RESET ... AC97_PCM_SURR_DAC_RATE:
  35. case AC97_PCM_LR_ADC_RATE:
  36. case AC97_CENTER_LFE_MASTER:
  37. case AC97_SPDIF ... AC97_LINE1_LEVEL:
  38. case AC97_GPIO_CFG ... 0x5c:
  39. case AC97_CODEC_CLASS_REV ... AC97_PCI_SID:
  40. case 0x74 ... AC97_VENDOR_ID2:
  41. return true;
  42. default:
  43. return false;
  44. }
  45. }
  46. static bool wm97xx_writeable_reg(struct device *dev, unsigned int reg)
  47. {
  48. switch (reg) {
  49. case AC97_VENDOR_ID1:
  50. case AC97_VENDOR_ID2:
  51. return false;
  52. default:
  53. return wm97xx_readable_reg(dev, reg);
  54. }
  55. }
  56. static const struct reg_default wm9705_reg_defaults[] = {
  57. { 0x02, 0x8000 },
  58. { 0x04, 0x8000 },
  59. { 0x06, 0x8000 },
  60. { 0x0a, 0x8000 },
  61. { 0x0c, 0x8008 },
  62. { 0x0e, 0x8008 },
  63. { 0x10, 0x8808 },
  64. { 0x12, 0x8808 },
  65. { 0x14, 0x8808 },
  66. { 0x16, 0x8808 },
  67. { 0x18, 0x8808 },
  68. { 0x1a, 0x0000 },
  69. { 0x1c, 0x8000 },
  70. { 0x20, 0x0000 },
  71. { 0x22, 0x0000 },
  72. { 0x26, 0x000f },
  73. { 0x28, 0x0605 },
  74. { 0x2a, 0x0000 },
  75. { 0x2c, 0xbb80 },
  76. { 0x32, 0xbb80 },
  77. { 0x34, 0x2000 },
  78. { 0x5a, 0x0000 },
  79. { 0x5c, 0x0000 },
  80. { 0x72, 0x0808 },
  81. { 0x74, 0x0000 },
  82. { 0x76, 0x0006 },
  83. { 0x78, 0x0000 },
  84. { 0x7a, 0x0000 },
  85. };
  86. static const struct regmap_config wm9705_regmap_config = {
  87. .reg_bits = 16,
  88. .reg_stride = 2,
  89. .val_bits = 16,
  90. .max_register = 0x7e,
  91. .cache_type = REGCACHE_RBTREE,
  92. .reg_defaults = wm9705_reg_defaults,
  93. .num_reg_defaults = ARRAY_SIZE(wm9705_reg_defaults),
  94. .volatile_reg = regmap_ac97_default_volatile,
  95. .readable_reg = wm97xx_readable_reg,
  96. .writeable_reg = wm97xx_writeable_reg,
  97. };
  98. static struct mfd_cell wm9705_cells[] = {
  99. { .name = "wm9705-codec", },
  100. { .name = "wm97xx-ts", },
  101. };
  102. static bool wm9712_volatile_reg(struct device *dev, unsigned int reg)
  103. {
  104. switch (reg) {
  105. case AC97_REC_GAIN:
  106. return true;
  107. default:
  108. return regmap_ac97_default_volatile(dev, reg);
  109. }
  110. }
  111. static const struct reg_default wm9712_reg_defaults[] = {
  112. { 0x02, 0x8000 },
  113. { 0x04, 0x8000 },
  114. { 0x06, 0x8000 },
  115. { 0x08, 0x0f0f },
  116. { 0x0a, 0xaaa0 },
  117. { 0x0c, 0xc008 },
  118. { 0x0e, 0x6808 },
  119. { 0x10, 0xe808 },
  120. { 0x12, 0xaaa0 },
  121. { 0x14, 0xad00 },
  122. { 0x16, 0x8000 },
  123. { 0x18, 0xe808 },
  124. { 0x1a, 0x3000 },
  125. { 0x1c, 0x8000 },
  126. { 0x20, 0x0000 },
  127. { 0x22, 0x0000 },
  128. { 0x26, 0x000f },
  129. { 0x28, 0x0605 },
  130. { 0x2a, 0x0410 },
  131. { 0x2c, 0xbb80 },
  132. { 0x2e, 0xbb80 },
  133. { 0x32, 0xbb80 },
  134. { 0x34, 0x2000 },
  135. { 0x4c, 0xf83e },
  136. { 0x4e, 0xffff },
  137. { 0x50, 0x0000 },
  138. { 0x52, 0x0000 },
  139. { 0x56, 0xf83e },
  140. { 0x58, 0x0008 },
  141. { 0x5c, 0x0000 },
  142. { 0x60, 0xb032 },
  143. { 0x62, 0x3e00 },
  144. { 0x64, 0x0000 },
  145. { 0x76, 0x0006 },
  146. { 0x78, 0x0001 },
  147. { 0x7a, 0x0000 },
  148. };
  149. static const struct regmap_config wm9712_regmap_config = {
  150. .reg_bits = 16,
  151. .reg_stride = 2,
  152. .val_bits = 16,
  153. .max_register = 0x7e,
  154. .cache_type = REGCACHE_RBTREE,
  155. .reg_defaults = wm9712_reg_defaults,
  156. .num_reg_defaults = ARRAY_SIZE(wm9712_reg_defaults),
  157. .volatile_reg = wm9712_volatile_reg,
  158. .readable_reg = wm97xx_readable_reg,
  159. .writeable_reg = wm97xx_writeable_reg,
  160. };
  161. static struct mfd_cell wm9712_cells[] = {
  162. { .name = "wm9712-codec", },
  163. { .name = "wm97xx-ts", },
  164. };
  165. static const struct reg_default wm9713_reg_defaults[] = {
  166. { 0x02, 0x8080 }, /* Speaker Output Volume */
  167. { 0x04, 0x8080 }, /* Headphone Output Volume */
  168. { 0x06, 0x8080 }, /* Out3/OUT4 Volume */
  169. { 0x08, 0xc880 }, /* Mono Volume */
  170. { 0x0a, 0xe808 }, /* LINEIN Volume */
  171. { 0x0c, 0xe808 }, /* DAC PGA Volume */
  172. { 0x0e, 0x0808 }, /* MIC PGA Volume */
  173. { 0x10, 0x00da }, /* MIC Routing Control */
  174. { 0x12, 0x8000 }, /* Record PGA Volume */
  175. { 0x14, 0xd600 }, /* Record Routing */
  176. { 0x16, 0xaaa0 }, /* PCBEEP Volume */
  177. { 0x18, 0xaaa0 }, /* VxDAC Volume */
  178. { 0x1a, 0xaaa0 }, /* AUXDAC Volume */
  179. { 0x1c, 0x0000 }, /* Output PGA Mux */
  180. { 0x1e, 0x0000 }, /* DAC 3D control */
  181. { 0x20, 0x0f0f }, /* DAC Tone Control*/
  182. { 0x22, 0x0040 }, /* MIC Input Select & Bias */
  183. { 0x24, 0x0000 }, /* Output Volume Mapping & Jack */
  184. { 0x26, 0x7f00 }, /* Powerdown Ctrl/Stat*/
  185. { 0x28, 0x0405 }, /* Extended Audio ID */
  186. { 0x2a, 0x0410 }, /* Extended Audio Start/Ctrl */
  187. { 0x2c, 0xbb80 }, /* Audio DACs Sample Rate */
  188. { 0x2e, 0xbb80 }, /* AUXDAC Sample Rate */
  189. { 0x32, 0xbb80 }, /* Audio ADCs Sample Rate */
  190. { 0x36, 0x4523 }, /* PCM codec control */
  191. { 0x3a, 0x2000 }, /* SPDIF control */
  192. { 0x3c, 0xfdff }, /* Powerdown 1 */
  193. { 0x3e, 0xffff }, /* Powerdown 2 */
  194. { 0x40, 0x0000 }, /* General Purpose */
  195. { 0x42, 0x0000 }, /* Fast Power-Up Control */
  196. { 0x44, 0x0080 }, /* MCLK/PLL Control */
  197. { 0x46, 0x0000 }, /* MCLK/PLL Control */
  198. { 0x4c, 0xfffe }, /* GPIO Pin Configuration */
  199. { 0x4e, 0xffff }, /* GPIO Pin Polarity / Type */
  200. { 0x50, 0x0000 }, /* GPIO Pin Sticky */
  201. { 0x52, 0x0000 }, /* GPIO Pin Wake-Up */
  202. /* GPIO Pin Status */
  203. { 0x56, 0xfffe }, /* GPIO Pin Sharing */
  204. { 0x58, 0x4000 }, /* GPIO PullUp/PullDown */
  205. { 0x5a, 0x0000 }, /* Additional Functions 1 */
  206. { 0x5c, 0x0000 }, /* Additional Functions 2 */
  207. { 0x60, 0xb032 }, /* ALC Control */
  208. { 0x62, 0x3e00 }, /* ALC / Noise Gate Control */
  209. { 0x64, 0x0000 }, /* AUXDAC input control */
  210. { 0x74, 0x0000 }, /* Digitiser Reg 1 */
  211. { 0x76, 0x0006 }, /* Digitiser Reg 2 */
  212. { 0x78, 0x0001 }, /* Digitiser Reg 3 */
  213. { 0x7a, 0x0000 }, /* Digitiser Read Back */
  214. };
  215. static const struct regmap_config wm9713_regmap_config = {
  216. .reg_bits = 16,
  217. .reg_stride = 2,
  218. .val_bits = 16,
  219. .max_register = 0x7e,
  220. .cache_type = REGCACHE_RBTREE,
  221. .reg_defaults = wm9713_reg_defaults,
  222. .num_reg_defaults = ARRAY_SIZE(wm9713_reg_defaults),
  223. .volatile_reg = regmap_ac97_default_volatile,
  224. .readable_reg = wm97xx_readable_reg,
  225. .writeable_reg = wm97xx_writeable_reg,
  226. };
  227. static struct mfd_cell wm9713_cells[] = {
  228. { .name = "wm9713-codec", },
  229. { .name = "wm97xx-ts", },
  230. };
  231. static int wm97xx_ac97_probe(struct ac97_codec_device *adev)
  232. {
  233. struct wm97xx_priv *wm97xx;
  234. const struct regmap_config *config;
  235. struct wm97xx_platform_data *codec_pdata;
  236. struct mfd_cell *cells;
  237. int ret = -ENODEV, nb_cells, i;
  238. struct wm97xx_pdata *pdata = snd_ac97_codec_get_platdata(adev);
  239. wm97xx = devm_kzalloc(ac97_codec_dev2dev(adev),
  240. sizeof(*wm97xx), GFP_KERNEL);
  241. if (!wm97xx)
  242. return -ENOMEM;
  243. wm97xx->dev = ac97_codec_dev2dev(adev);
  244. wm97xx->ac97 = snd_ac97_compat_alloc(adev);
  245. if (IS_ERR(wm97xx->ac97))
  246. return PTR_ERR(wm97xx->ac97);
  247. ac97_set_drvdata(adev, wm97xx);
  248. dev_info(wm97xx->dev, "wm97xx core found, id=0x%x\n",
  249. adev->vendor_id);
  250. codec_pdata = &wm97xx->codec_pdata;
  251. codec_pdata->ac97 = wm97xx->ac97;
  252. codec_pdata->batt_pdata = pdata ? pdata->batt_pdata : NULL;
  253. switch (adev->vendor_id) {
  254. case WM9705_VENDOR_ID:
  255. config = &wm9705_regmap_config;
  256. cells = wm9705_cells;
  257. nb_cells = ARRAY_SIZE(wm9705_cells);
  258. break;
  259. case WM9712_VENDOR_ID:
  260. config = &wm9712_regmap_config;
  261. cells = wm9712_cells;
  262. nb_cells = ARRAY_SIZE(wm9712_cells);
  263. break;
  264. case WM9713_VENDOR_ID:
  265. config = &wm9713_regmap_config;
  266. cells = wm9713_cells;
  267. nb_cells = ARRAY_SIZE(wm9713_cells);
  268. break;
  269. default:
  270. goto err_free_compat;
  271. }
  272. for (i = 0; i < nb_cells; i++) {
  273. cells[i].platform_data = codec_pdata;
  274. cells[i].pdata_size = sizeof(*codec_pdata);
  275. }
  276. codec_pdata->regmap = devm_regmap_init_ac97(wm97xx->ac97, config);
  277. if (IS_ERR(codec_pdata->regmap)) {
  278. ret = PTR_ERR(codec_pdata->regmap);
  279. goto err_free_compat;
  280. }
  281. ret = devm_mfd_add_devices(wm97xx->dev, PLATFORM_DEVID_NONE,
  282. cells, nb_cells, NULL, 0, NULL);
  283. if (ret)
  284. goto err_free_compat;
  285. return ret;
  286. err_free_compat:
  287. snd_ac97_compat_release(wm97xx->ac97);
  288. return ret;
  289. }
  290. static int wm97xx_ac97_remove(struct ac97_codec_device *adev)
  291. {
  292. struct wm97xx_priv *wm97xx = ac97_get_drvdata(adev);
  293. snd_ac97_compat_release(wm97xx->ac97);
  294. return 0;
  295. }
  296. static const struct ac97_id wm97xx_ac97_ids[] = {
  297. { .id = WM9705_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
  298. { .id = WM9712_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
  299. { .id = WM9713_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
  300. { }
  301. };
  302. static struct ac97_codec_driver wm97xx_ac97_driver = {
  303. .driver = {
  304. .name = "wm97xx-core",
  305. },
  306. .probe = wm97xx_ac97_probe,
  307. .remove = wm97xx_ac97_remove,
  308. .id_table = wm97xx_ac97_ids,
  309. };
  310. static int __init wm97xx_module_init(void)
  311. {
  312. return snd_ac97_codec_driver_register(&wm97xx_ac97_driver);
  313. }
  314. module_init(wm97xx_module_init);
  315. static void __exit wm97xx_module_exit(void)
  316. {
  317. snd_ac97_codec_driver_unregister(&wm97xx_ac97_driver);
  318. }
  319. module_exit(wm97xx_module_exit);
  320. MODULE_DESCRIPTION("WM9712, WM9713 core driver");
  321. MODULE_AUTHOR("Robert Jarzmik <[email protected]>");
  322. MODULE_LICENSE("GPL");