gs1662.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * GS1662 device registration.
  4. *
  5. * Copyright (C) 2015-2016 Nexvision
  6. * Author: Charles-Antoine Couret <[email protected]>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/spi/spi.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/ctype.h>
  13. #include <linux/err.h>
  14. #include <linux/device.h>
  15. #include <linux/module.h>
  16. #include <linux/videodev2.h>
  17. #include <media/v4l2-common.h>
  18. #include <media/v4l2-ctrls.h>
  19. #include <media/v4l2-device.h>
  20. #include <media/v4l2-subdev.h>
  21. #include <media/v4l2-dv-timings.h>
  22. #include <linux/v4l2-dv-timings.h>
  23. #define REG_STATUS 0x04
  24. #define REG_FORCE_FMT 0x06
  25. #define REG_LINES_PER_FRAME 0x12
  26. #define REG_WORDS_PER_LINE 0x13
  27. #define REG_WORDS_PER_ACT_LINE 0x14
  28. #define REG_ACT_LINES_PER_FRAME 0x15
  29. #define MASK_H_LOCK 0x001
  30. #define MASK_V_LOCK 0x002
  31. #define MASK_STD_LOCK 0x004
  32. #define MASK_FORCE_STD 0x020
  33. #define MASK_STD_STATUS 0x3E0
  34. #define GS_WIDTH_MIN 720
  35. #define GS_WIDTH_MAX 2048
  36. #define GS_HEIGHT_MIN 487
  37. #define GS_HEIGHT_MAX 1080
  38. #define GS_PIXELCLOCK_MIN 10519200
  39. #define GS_PIXELCLOCK_MAX 74250000
  40. struct gs {
  41. struct spi_device *pdev;
  42. struct v4l2_subdev sd;
  43. struct v4l2_dv_timings current_timings;
  44. int enabled;
  45. };
  46. struct gs_reg_fmt {
  47. u16 reg_value;
  48. struct v4l2_dv_timings format;
  49. };
  50. struct gs_reg_fmt_custom {
  51. u16 reg_value;
  52. __u32 width;
  53. __u32 height;
  54. __u64 pixelclock;
  55. __u32 interlaced;
  56. };
  57. static const struct spi_device_id gs_id[] = {
  58. { "gs1662", 0 },
  59. { }
  60. };
  61. MODULE_DEVICE_TABLE(spi, gs_id);
  62. static const struct v4l2_dv_timings fmt_cap[] = {
  63. V4L2_DV_BT_SDI_720X487I60,
  64. V4L2_DV_BT_CEA_720X576P50,
  65. V4L2_DV_BT_CEA_1280X720P24,
  66. V4L2_DV_BT_CEA_1280X720P25,
  67. V4L2_DV_BT_CEA_1280X720P30,
  68. V4L2_DV_BT_CEA_1280X720P50,
  69. V4L2_DV_BT_CEA_1280X720P60,
  70. V4L2_DV_BT_CEA_1920X1080P24,
  71. V4L2_DV_BT_CEA_1920X1080P25,
  72. V4L2_DV_BT_CEA_1920X1080P30,
  73. V4L2_DV_BT_CEA_1920X1080I50,
  74. V4L2_DV_BT_CEA_1920X1080I60,
  75. };
  76. static const struct gs_reg_fmt reg_fmt[] = {
  77. { 0x00, V4L2_DV_BT_CEA_1280X720P60 },
  78. { 0x01, V4L2_DV_BT_CEA_1280X720P60 },
  79. { 0x02, V4L2_DV_BT_CEA_1280X720P30 },
  80. { 0x03, V4L2_DV_BT_CEA_1280X720P30 },
  81. { 0x04, V4L2_DV_BT_CEA_1280X720P50 },
  82. { 0x05, V4L2_DV_BT_CEA_1280X720P50 },
  83. { 0x06, V4L2_DV_BT_CEA_1280X720P25 },
  84. { 0x07, V4L2_DV_BT_CEA_1280X720P25 },
  85. { 0x08, V4L2_DV_BT_CEA_1280X720P24 },
  86. { 0x09, V4L2_DV_BT_CEA_1280X720P24 },
  87. { 0x0A, V4L2_DV_BT_CEA_1920X1080I60 },
  88. { 0x0B, V4L2_DV_BT_CEA_1920X1080P30 },
  89. /* Default value: keep this field before 0xC */
  90. { 0x14, V4L2_DV_BT_CEA_1920X1080I50 },
  91. { 0x0C, V4L2_DV_BT_CEA_1920X1080I50 },
  92. { 0x0D, V4L2_DV_BT_CEA_1920X1080P25 },
  93. { 0x0E, V4L2_DV_BT_CEA_1920X1080P25 },
  94. { 0x10, V4L2_DV_BT_CEA_1920X1080P24 },
  95. { 0x12, V4L2_DV_BT_CEA_1920X1080P24 },
  96. { 0x16, V4L2_DV_BT_SDI_720X487I60 },
  97. { 0x19, V4L2_DV_BT_SDI_720X487I60 },
  98. { 0x18, V4L2_DV_BT_CEA_720X576P50 },
  99. { 0x1A, V4L2_DV_BT_CEA_720X576P50 },
  100. /* Implement following timings before enable it.
  101. * Because of we don't have access to these theoretical timings yet.
  102. * Workaround: use functions to get and set registers for these formats.
  103. */
  104. #if 0
  105. { 0x0F, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */
  106. { 0x11, V4L2_DV_BT_XXX_1920X1080I24 }, /* SMPTE 274M */
  107. { 0x13, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */
  108. { 0x15, V4L2_DV_BT_XXX_1920X1035I60 }, /* SMPTE 260M */
  109. { 0x17, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */
  110. { 0x1B, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */
  111. { 0x1C, V4L2_DV_BT_XXX_2048X1080P25 }, /* SMPTE 428.1M */
  112. #endif
  113. };
  114. static const struct v4l2_dv_timings_cap gs_timings_cap = {
  115. .type = V4L2_DV_BT_656_1120,
  116. /* keep this initialization for compatibility with GCC < 4.4.6 */
  117. .reserved = { 0 },
  118. V4L2_INIT_BT_TIMINGS(GS_WIDTH_MIN, GS_WIDTH_MAX, GS_HEIGHT_MIN,
  119. GS_HEIGHT_MAX, GS_PIXELCLOCK_MIN,
  120. GS_PIXELCLOCK_MAX,
  121. V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI,
  122. V4L2_DV_BT_CAP_PROGRESSIVE
  123. | V4L2_DV_BT_CAP_INTERLACED)
  124. };
  125. static int gs_read_register(struct spi_device *spi, u16 addr, u16 *value)
  126. {
  127. int ret;
  128. u16 buf_addr = (0x8000 | (0x0FFF & addr));
  129. u16 buf_value = 0;
  130. struct spi_message msg;
  131. struct spi_transfer tx[] = {
  132. {
  133. .tx_buf = &buf_addr,
  134. .len = 2,
  135. .delay = {
  136. .value = 1,
  137. .unit = SPI_DELAY_UNIT_USECS
  138. },
  139. }, {
  140. .rx_buf = &buf_value,
  141. .len = 2,
  142. .delay = {
  143. .value = 1,
  144. .unit = SPI_DELAY_UNIT_USECS
  145. },
  146. },
  147. };
  148. spi_message_init(&msg);
  149. spi_message_add_tail(&tx[0], &msg);
  150. spi_message_add_tail(&tx[1], &msg);
  151. ret = spi_sync(spi, &msg);
  152. *value = buf_value;
  153. return ret;
  154. }
  155. static int gs_write_register(struct spi_device *spi, u16 addr, u16 value)
  156. {
  157. int ret;
  158. u16 buf_addr = addr;
  159. u16 buf_value = value;
  160. struct spi_message msg;
  161. struct spi_transfer tx[] = {
  162. {
  163. .tx_buf = &buf_addr,
  164. .len = 2,
  165. .delay = {
  166. .value = 1,
  167. .unit = SPI_DELAY_UNIT_USECS
  168. },
  169. }, {
  170. .tx_buf = &buf_value,
  171. .len = 2,
  172. .delay = {
  173. .value = 1,
  174. .unit = SPI_DELAY_UNIT_USECS
  175. },
  176. },
  177. };
  178. spi_message_init(&msg);
  179. spi_message_add_tail(&tx[0], &msg);
  180. spi_message_add_tail(&tx[1], &msg);
  181. ret = spi_sync(spi, &msg);
  182. return ret;
  183. }
  184. #ifdef CONFIG_VIDEO_ADV_DEBUG
  185. static int gs_g_register(struct v4l2_subdev *sd,
  186. struct v4l2_dbg_register *reg)
  187. {
  188. struct spi_device *spi = v4l2_get_subdevdata(sd);
  189. u16 val;
  190. int ret;
  191. ret = gs_read_register(spi, reg->reg & 0xFFFF, &val);
  192. reg->val = val;
  193. reg->size = 2;
  194. return ret;
  195. }
  196. static int gs_s_register(struct v4l2_subdev *sd,
  197. const struct v4l2_dbg_register *reg)
  198. {
  199. struct spi_device *spi = v4l2_get_subdevdata(sd);
  200. return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF);
  201. }
  202. #endif
  203. static int gs_status_format(u16 status, struct v4l2_dv_timings *timings)
  204. {
  205. int std = (status & MASK_STD_STATUS) >> 5;
  206. int i;
  207. for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) {
  208. if (reg_fmt[i].reg_value == std) {
  209. *timings = reg_fmt[i].format;
  210. return 0;
  211. }
  212. }
  213. return -ERANGE;
  214. }
  215. static u16 get_register_timings(struct v4l2_dv_timings *timings)
  216. {
  217. int i;
  218. for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) {
  219. if (v4l2_match_dv_timings(timings, &reg_fmt[i].format, 0,
  220. false))
  221. return reg_fmt[i].reg_value | MASK_FORCE_STD;
  222. }
  223. return 0x0;
  224. }
  225. static inline struct gs *to_gs(struct v4l2_subdev *sd)
  226. {
  227. return container_of(sd, struct gs, sd);
  228. }
  229. static int gs_s_dv_timings(struct v4l2_subdev *sd,
  230. struct v4l2_dv_timings *timings)
  231. {
  232. struct gs *gs = to_gs(sd);
  233. int reg_value;
  234. reg_value = get_register_timings(timings);
  235. if (reg_value == 0x0)
  236. return -EINVAL;
  237. gs->current_timings = *timings;
  238. return 0;
  239. }
  240. static int gs_g_dv_timings(struct v4l2_subdev *sd,
  241. struct v4l2_dv_timings *timings)
  242. {
  243. struct gs *gs = to_gs(sd);
  244. *timings = gs->current_timings;
  245. return 0;
  246. }
  247. static int gs_query_dv_timings(struct v4l2_subdev *sd,
  248. struct v4l2_dv_timings *timings)
  249. {
  250. struct gs *gs = to_gs(sd);
  251. struct v4l2_dv_timings fmt;
  252. u16 reg_value, i;
  253. int ret;
  254. if (gs->enabled)
  255. return -EBUSY;
  256. /*
  257. * Check if the component detect a line, a frame or something else
  258. * which looks like a video signal activity.
  259. */
  260. for (i = 0; i < 4; i++) {
  261. gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, &reg_value);
  262. if (reg_value)
  263. break;
  264. }
  265. /* If no register reports a video signal */
  266. if (i >= 4)
  267. return -ENOLINK;
  268. gs_read_register(gs->pdev, REG_STATUS, &reg_value);
  269. if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK))
  270. return -ENOLCK;
  271. if (!(reg_value & MASK_STD_LOCK))
  272. return -ERANGE;
  273. ret = gs_status_format(reg_value, &fmt);
  274. if (ret < 0)
  275. return ret;
  276. *timings = fmt;
  277. return 0;
  278. }
  279. static int gs_enum_dv_timings(struct v4l2_subdev *sd,
  280. struct v4l2_enum_dv_timings *timings)
  281. {
  282. if (timings->index >= ARRAY_SIZE(fmt_cap))
  283. return -EINVAL;
  284. if (timings->pad != 0)
  285. return -EINVAL;
  286. timings->timings = fmt_cap[timings->index];
  287. return 0;
  288. }
  289. static int gs_s_stream(struct v4l2_subdev *sd, int enable)
  290. {
  291. struct gs *gs = to_gs(sd);
  292. int reg_value;
  293. if (gs->enabled == enable)
  294. return 0;
  295. gs->enabled = enable;
  296. if (enable) {
  297. /* To force the specific format */
  298. reg_value = get_register_timings(&gs->current_timings);
  299. return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value);
  300. }
  301. /* To renable auto-detection mode */
  302. return gs_write_register(gs->pdev, REG_FORCE_FMT, 0x0);
  303. }
  304. static int gs_g_input_status(struct v4l2_subdev *sd, u32 *status)
  305. {
  306. struct gs *gs = to_gs(sd);
  307. u16 reg_value, i;
  308. int ret;
  309. /*
  310. * Check if the component detect a line, a frame or something else
  311. * which looks like a video signal activity.
  312. */
  313. for (i = 0; i < 4; i++) {
  314. ret = gs_read_register(gs->pdev,
  315. REG_LINES_PER_FRAME + i, &reg_value);
  316. if (reg_value)
  317. break;
  318. if (ret) {
  319. *status = V4L2_IN_ST_NO_POWER;
  320. return ret;
  321. }
  322. }
  323. /* If no register reports a video signal */
  324. if (i >= 4)
  325. *status |= V4L2_IN_ST_NO_SIGNAL;
  326. ret = gs_read_register(gs->pdev, REG_STATUS, &reg_value);
  327. if (!(reg_value & MASK_H_LOCK))
  328. *status |= V4L2_IN_ST_NO_H_LOCK;
  329. if (!(reg_value & MASK_V_LOCK))
  330. *status |= V4L2_IN_ST_NO_V_LOCK;
  331. if (!(reg_value & MASK_STD_LOCK))
  332. *status |= V4L2_IN_ST_NO_STD_LOCK;
  333. return ret;
  334. }
  335. static int gs_dv_timings_cap(struct v4l2_subdev *sd,
  336. struct v4l2_dv_timings_cap *cap)
  337. {
  338. if (cap->pad != 0)
  339. return -EINVAL;
  340. *cap = gs_timings_cap;
  341. return 0;
  342. }
  343. /* V4L2 core operation handlers */
  344. static const struct v4l2_subdev_core_ops gs_core_ops = {
  345. #ifdef CONFIG_VIDEO_ADV_DEBUG
  346. .g_register = gs_g_register,
  347. .s_register = gs_s_register,
  348. #endif
  349. };
  350. static const struct v4l2_subdev_video_ops gs_video_ops = {
  351. .s_dv_timings = gs_s_dv_timings,
  352. .g_dv_timings = gs_g_dv_timings,
  353. .s_stream = gs_s_stream,
  354. .g_input_status = gs_g_input_status,
  355. .query_dv_timings = gs_query_dv_timings,
  356. };
  357. static const struct v4l2_subdev_pad_ops gs_pad_ops = {
  358. .enum_dv_timings = gs_enum_dv_timings,
  359. .dv_timings_cap = gs_dv_timings_cap,
  360. };
  361. /* V4L2 top level operation handlers */
  362. static const struct v4l2_subdev_ops gs_ops = {
  363. .core = &gs_core_ops,
  364. .video = &gs_video_ops,
  365. .pad = &gs_pad_ops,
  366. };
  367. static int gs_probe(struct spi_device *spi)
  368. {
  369. int ret;
  370. struct gs *gs;
  371. struct v4l2_subdev *sd;
  372. gs = devm_kzalloc(&spi->dev, sizeof(struct gs), GFP_KERNEL);
  373. if (!gs)
  374. return -ENOMEM;
  375. gs->pdev = spi;
  376. sd = &gs->sd;
  377. spi->mode = SPI_MODE_0;
  378. spi->irq = -1;
  379. spi->max_speed_hz = 10000000;
  380. spi->bits_per_word = 16;
  381. ret = spi_setup(spi);
  382. v4l2_spi_subdev_init(sd, spi, &gs_ops);
  383. gs->current_timings = reg_fmt[0].format;
  384. gs->enabled = 0;
  385. /* Set H_CONFIG to SMPTE timings */
  386. gs_write_register(spi, 0x0, 0x300);
  387. return ret;
  388. }
  389. static void gs_remove(struct spi_device *spi)
  390. {
  391. struct v4l2_subdev *sd = spi_get_drvdata(spi);
  392. v4l2_device_unregister_subdev(sd);
  393. }
  394. static struct spi_driver gs_driver = {
  395. .driver = {
  396. .name = "gs1662",
  397. },
  398. .probe = gs_probe,
  399. .remove = gs_remove,
  400. .id_table = gs_id,
  401. };
  402. module_spi_driver(gs_driver);
  403. MODULE_LICENSE("GPL");
  404. MODULE_AUTHOR("Charles-Antoine Couret <[email protected]>");
  405. MODULE_DESCRIPTION("Gennum GS1662 HD/SD-SDI Serializer driver");